Merge "qcacmn: Initial changes for Pebble bring up"
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révision
7307b0f02e
2332
hal/wifi3.0/qcn6432/hal_6432.c
Fichier normal
2332
hal/wifi3.0/qcn6432/hal_6432.c
Fichier normal
Fichier diff supprimé car celui-ci est trop grand
Voir la Diff
123
hal/wifi3.0/qcn6432/hal_6432_rx.h
Fichier normal
123
hal/wifi3.0/qcn6432/hal_6432_rx.h
Fichier normal
@@ -0,0 +1,123 @@
|
||||
/*
|
||||
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _HAL_6432_RX_H_
|
||||
#define _HAL_6432_RX_H_
|
||||
#include "qdf_util.h"
|
||||
#include "qdf_types.h"
|
||||
#include "qdf_lock.h"
|
||||
#include "qdf_mem.h"
|
||||
#include "qdf_nbuf.h"
|
||||
#include "tcl_data_cmd.h"
|
||||
#include "phyrx_rssi_legacy.h"
|
||||
#include "rx_msdu_start.h"
|
||||
#include "tlv_tag_def.h"
|
||||
#include "hal_hw_headers.h"
|
||||
#include "hal_internal.h"
|
||||
#include "cdp_txrx_mon_struct.h"
|
||||
#include "qdf_trace.h"
|
||||
#include "hal_rx.h"
|
||||
#include "hal_tx.h"
|
||||
#include "dp_types.h"
|
||||
#include "hal_api_mon.h"
|
||||
#include "phyrx_other_receive_info_ru_details.h"
|
||||
|
||||
#define HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va) \
|
||||
(uint8_t *)(link_desc_va) + \
|
||||
RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
|
||||
|
||||
#define HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0) \
|
||||
(uint8_t *)(msdu0) + \
|
||||
RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
|
||||
|
||||
#define HAL_ENT_MPDU_DESC_INFO(ent_ring_desc) \
|
||||
(uint8_t *)(ent_ring_desc) + \
|
||||
RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
|
||||
|
||||
#define HAL_DST_MPDU_DESC_INFO(dst_ring_desc) \
|
||||
(uint8_t *)(dst_ring_desc) + \
|
||||
REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
|
||||
|
||||
#define HAL_RX_GET_MAC_ADDR1_VALID(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, MAC_ADDR_AD1_VALID)
|
||||
|
||||
#define HAL_RX_GET_SW_FRAME_GROUP_ID(rx_mpdu_start) \
|
||||
HAL_RX_GET(rx_mpdu_start, RX_MPDU_INFO, SW_FRAME_GROUP_ID)
|
||||
|
||||
/*
|
||||
* In Beryllium chipset msdu_start was removed and merged in msdu_end.
|
||||
* Due to this valid contents will be present only in last msdu.
|
||||
* After setting the 5th bit of spare control field, REO will copy the contents
|
||||
* from last buffer to all the other buffers of MSDU.
|
||||
*/
|
||||
#define HAL_REO_MSDU_END_COPY 0x20
|
||||
#define HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0
|
||||
|
||||
#define HAL_REO_R0_CONFIG(soc, reg_val, reo_params) \
|
||||
do { \
|
||||
reg_val &= \
|
||||
~(HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK |\
|
||||
HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK); \
|
||||
reg_val |= \
|
||||
HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
|
||||
AGING_LIST_ENABLE, 1) | \
|
||||
HAL_SM(HWIO_REO_R0_GENERAL_ENABLE, \
|
||||
AGING_FLUSH_ENABLE, 1); \
|
||||
HAL_REG_WRITE(soc, \
|
||||
HWIO_REO_R0_GENERAL_ENABLE_ADDR( \
|
||||
REO_REG_REG_BASE), \
|
||||
reg_val); \
|
||||
reg_val = HAL_REG_READ(soc, \
|
||||
HWIO_REO_R0_MISC_CTL_ADDR( \
|
||||
REO_REG_REG_BASE)); \
|
||||
reg_val &= ~(HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK); \
|
||||
reg_val |= HAL_SM(HWIO_REO_R0_MISC_CTL, \
|
||||
FRAGMENT_DEST_RING, \
|
||||
(reo_params)->frag_dst_ring); \
|
||||
reg_val |= ((HAL_REO_MSDU_END_COPY) << \
|
||||
HAL_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT); \
|
||||
HAL_REG_WRITE(soc, \
|
||||
HWIO_REO_R0_MISC_CTL_ADDR(REO_REG_REG_BASE), \
|
||||
reg_val); \
|
||||
} while (0)
|
||||
|
||||
#define HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr) \
|
||||
((struct rx_msdu_desc_info *) \
|
||||
_OFFSET_TO_BYTE_PTR(msdu_details_ptr, \
|
||||
UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET))
|
||||
|
||||
#define HAL_RX_TLV_MSDU_DONE_COPY_GET(_rx_pkt_tlv) \
|
||||
HAL_RX_MSDU_END(_rx_pkt_tlv).msdu_done_copy
|
||||
|
||||
#define HAL_RX_LINK_DESC_MSDU0_PTR(link_desc) \
|
||||
((struct rx_msdu_details *) \
|
||||
_OFFSET_TO_BYTE_PTR((link_desc),\
|
||||
RX_MSDU_LINK_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET))
|
||||
|
||||
#if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK 0x00000006
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB 1
|
||||
#define PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_MSB 2
|
||||
|
||||
#define HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv) \
|
||||
((HAL_RX_GET((rx_tlv), \
|
||||
PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS, \
|
||||
RTT_CFR_STATUS) & \
|
||||
PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_BMASK) >> \
|
||||
PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS_CHAN_CAPTURE_STATUS_LSB)
|
||||
#endif
|
||||
#endif
|
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595
hal/wifi3.0/qcn6432/hal_6432_tx.h
Fichier normal
595
hal/wifi3.0/qcn6432/hal_6432_tx.h
Fichier normal
@@ -0,0 +1,595 @@
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/*
|
||||
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
|
||||
* Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
|
||||
*/
|
||||
#ifndef _HAL_6432_TX_H_
|
||||
#define _HAL_6432_TX_H_
|
||||
|
||||
#include "tcl_data_cmd.h"
|
||||
#include "phyrx_rssi_legacy.h"
|
||||
#include "hal_internal.h"
|
||||
#include "qdf_trace.h"
|
||||
#include "hal_rx.h"
|
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#include "hal_tx.h"
|
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#include "hal_api_mon.h"
|
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#include <hal_be_tx.h>
|
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#define DSCP_TID_TABLE_SIZE 24
|
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#define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4)
|
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#define HAL_TX_NUM_DSCP_REGISTER_SIZE 32
|
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#define HAL_PPE_VP_ENTRIES_MAX 32
|
||||
|
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/**
|
||||
* hal_tx_set_dscp_tid_map_6432() - Configure default DSCP to TID map table
|
||||
* @hal_soc: HAL SoC context
|
||||
* @map: DSCP-TID mapping table
|
||||
* @id: mapping table ID - 0-31
|
||||
*
|
||||
* DSCP are mapped to 8 TID values using TID values programmed
|
||||
* in any of the 32 DSCP_TID_MAPS (id = 0-31).
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
static void hal_tx_set_dscp_tid_map_6432(struct hal_soc *hal_soc, uint8_t *map,
|
||||
uint8_t id)
|
||||
{
|
||||
int i;
|
||||
uint32_t addr, cmn_reg_addr;
|
||||
uint32_t value = 0, regval;
|
||||
uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0;
|
||||
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||
|
||||
if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS_6432)
|
||||
return;
|
||||
|
||||
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
|
||||
MAC_TCL_REG_REG_BASE);
|
||||
|
||||
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||
MAC_TCL_REG_REG_BASE,
|
||||
id * NUM_WORDS_PER_DSCP_TID_TABLE);
|
||||
|
||||
/* Enable read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval |=
|
||||
(1 <<
|
||||
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
|
||||
/* Write 8 (24 bits) DSCP-TID mappings in each iteration */
|
||||
for (i = 0; i < 64; i += 8) {
|
||||
value = (map[i] |
|
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(map[i + 1] << 0x3) |
|
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(map[i + 2] << 0x6) |
|
||||
(map[i + 3] << 0x9) |
|
||||
(map[i + 4] << 0xc) |
|
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(map[i + 5] << 0xf) |
|
||||
(map[i + 6] << 0x12) |
|
||||
(map[i + 7] << 0x15));
|
||||
|
||||
qdf_mem_copy(&val[cnt], (void *)&value, 3);
|
||||
cnt += 3;
|
||||
}
|
||||
|
||||
for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) {
|
||||
regval = *(uint32_t *)(val + i);
|
||||
HAL_REG_WRITE(soc, addr,
|
||||
(regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
addr += 4;
|
||||
}
|
||||
|
||||
/* Diasble read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval &=
|
||||
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_update_dscp_tid_6432() - Update the dscp tid map table as updated
|
||||
* by the user
|
||||
* @soc: HAL SoC context
|
||||
* @tid: DSCP-TID mapping table
|
||||
* @id : MAP ID
|
||||
* @dscp: DSCP_TID map index
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static void hal_tx_update_dscp_tid_6432(struct hal_soc *soc, uint8_t tid,
|
||||
uint8_t id, uint8_t dscp)
|
||||
{
|
||||
uint32_t addr, addr1, cmn_reg_addr;
|
||||
uint32_t start_value = 0, end_value = 0;
|
||||
uint32_t regval;
|
||||
uint8_t end_bits = 0;
|
||||
uint8_t start_bits = 0;
|
||||
uint32_t start_index, end_index;
|
||||
|
||||
cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(
|
||||
MAC_TCL_REG_REG_BASE);
|
||||
|
||||
addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
|
||||
MAC_TCL_REG_REG_BASE,
|
||||
id * NUM_WORDS_PER_DSCP_TID_TABLE);
|
||||
|
||||
start_index = dscp * HAL_TX_BITS_PER_TID;
|
||||
end_index = (start_index + (HAL_TX_BITS_PER_TID - 1))
|
||||
% HAL_TX_NUM_DSCP_REGISTER_SIZE;
|
||||
start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE;
|
||||
addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) /
|
||||
HAL_TX_NUM_DSCP_REGISTER_SIZE));
|
||||
|
||||
if (end_index < start_index) {
|
||||
end_bits = end_index + 1;
|
||||
start_bits = HAL_TX_BITS_PER_TID - end_bits;
|
||||
start_value = tid << start_index;
|
||||
end_value = tid >> start_bits;
|
||||
addr1 = addr + 4;
|
||||
} else {
|
||||
start_bits = HAL_TX_BITS_PER_TID - end_bits;
|
||||
start_value = tid << start_index;
|
||||
addr1 = 0;
|
||||
}
|
||||
|
||||
/* Enable read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval |=
|
||||
(1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
|
||||
regval = HAL_REG_READ(soc, addr);
|
||||
|
||||
if (end_index < start_index)
|
||||
regval &= (~0) >> start_bits;
|
||||
else
|
||||
regval &= ~(7 << start_index);
|
||||
|
||||
regval |= start_value;
|
||||
|
||||
HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
|
||||
if (addr1) {
|
||||
regval = HAL_REG_READ(soc, addr1);
|
||||
regval &= (~0) << end_bits;
|
||||
regval |= end_value;
|
||||
|
||||
HAL_REG_WRITE(soc, addr1, (regval &
|
||||
HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
|
||||
}
|
||||
|
||||
/* Diasble read/write access */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval &=
|
||||
~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK);
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
}
|
||||
|
||||
#ifdef DP_TX_IMPLICIT_RBM_MAPPING
|
||||
|
||||
#define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK
|
||||
#define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT
|
||||
|
||||
#define RBM_TCL_CMD_CREDIT_OFFSET \
|
||||
(HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2)
|
||||
|
||||
/**
|
||||
* hal_tx_config_rbm_mapping_be_6432() - Update return buffer manager ring id
|
||||
* @hal_soc_hdl: HAL SoC context
|
||||
* @hal_ring_hdl: Source ring pointer
|
||||
* @rbm_id: return buffer manager ring id
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline void
|
||||
hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
hal_ring_handle_t hal_ring_hdl,
|
||||
uint8_t rbm_id)
|
||||
{
|
||||
struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl;
|
||||
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr = 0;
|
||||
uint32_t reg_val = 0;
|
||||
uint32_t val = 0;
|
||||
uint8_t ring_num;
|
||||
enum hal_ring_type ring_type;
|
||||
|
||||
ring_type = srng->ring_type;
|
||||
ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id;
|
||||
ring_num = srng->ring_id - ring_num;
|
||||
|
||||
reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
|
||||
if (ring_type == TCL_CMD_CREDIT)
|
||||
ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET;
|
||||
|
||||
/* get current value stored in register address */
|
||||
val = HAL_REG_READ(hal_soc, reg_addr);
|
||||
|
||||
/* mask out other stored value */
|
||||
val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num)));
|
||||
|
||||
reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) <<
|
||||
(RBM_MAPPING_SHFT * ring_num));
|
||||
|
||||
/* write rbm mapped value to register address */
|
||||
HAL_REG_WRITE(hal_soc, reg_addr, reg_val);
|
||||
}
|
||||
#else
|
||||
static inline void
|
||||
hal_tx_config_rbm_mapping_be_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
hal_ring_handle_t hal_ring_hdl,
|
||||
uint8_t rbm_id)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
* hal_tx_init_cmd_credit_ring_6432() - Initialize command/credit SRNG
|
||||
* @hal_soc_hdl: Handle to HAL SoC structure
|
||||
* @hal_ring_hdl: Handle to HAL SRNG structure
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
static inline void
|
||||
hal_tx_init_cmd_credit_ring_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
hal_ring_handle_t hal_ring_hdl)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_set_ppe_cmn_config_6432() - Set the PPE common config register
|
||||
* @hal_soc_hdl: HAL SoC handle
|
||||
* @cmn_cfg: Common PPE config
|
||||
*
|
||||
* Based on the PPE2TCL descriptor below errors, if the below register
|
||||
* values are set then the packets are forward to Tx rule handler if 1'0b
|
||||
* or to TCL exit base if 1'1b.
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline
|
||||
void hal_tx_set_ppe_cmn_config_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
union hal_tx_cmn_config_ppe *cmn_cfg)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
union hal_tx_cmn_config_ppe *cfg =
|
||||
(union hal_tx_cmn_config_ppe *)cmn_cfg;
|
||||
uint32_t reg_addr, reg_val = 0;
|
||||
|
||||
reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
|
||||
reg_val = HAL_REG_READ(soc, reg_addr);
|
||||
|
||||
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK;
|
||||
reg_val |=
|
||||
(cfg->drop_prec_err &
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) <<
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT;
|
||||
|
||||
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK;
|
||||
reg_val |=
|
||||
(cfg->fake_mac_hdr &
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) <<
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT;
|
||||
|
||||
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK;
|
||||
reg_val |=
|
||||
(cfg->cpu_code_inv &
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) <<
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT;
|
||||
|
||||
reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK;
|
||||
reg_val |=
|
||||
(cfg->l3_l4_err &
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) <<
|
||||
HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT;
|
||||
|
||||
HAL_REG_WRITE(soc, reg_addr, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_set_ppe_vp_entry_6432() - Set the PPE VP entry
|
||||
* @hal_soc_hdl: HAL SoC handle
|
||||
* @cfg: PPE VP config
|
||||
* @ppe_vp_idx: PPE VP index to the table
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline
|
||||
void hal_tx_set_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
union hal_tx_ppe_vp_config *cfg,
|
||||
int ppe_vp_idx)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr;
|
||||
|
||||
reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
|
||||
ppe_vp_idx);
|
||||
|
||||
HAL_REG_WRITE(soc, reg_addr, cfg->val);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_ppeds_cfg_ast_override_map_reg_6432() - Set the PPE index mapping table
|
||||
* @hal_soc_hdl: HAL SoC context
|
||||
* @idx: index into the table
|
||||
* @idx_map: HAL PPE INDESX MAPPING config
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline void
|
||||
hal_ppeds_cfg_ast_override_map_reg_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
uint8_t idx,
|
||||
union hal_tx_ppe_idx_map_config *idx_map)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr;
|
||||
|
||||
reg_addr =
|
||||
HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
|
||||
idx);
|
||||
|
||||
HAL_REG_WRITE(soc, reg_addr, idx_map->val);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_set_ppe_pri2tid_map_6432()
|
||||
* @hal_soc_hdl: HAL SoC handle
|
||||
* @val : PRI to TID value
|
||||
* @map_no: Map number
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline
|
||||
void hal_tx_set_ppe_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
uint32_t val, uint8_t map_no)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr, reg_val = 0;
|
||||
|
||||
if (map_no == 0)
|
||||
reg_addr =
|
||||
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
else
|
||||
reg_addr =
|
||||
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
|
||||
reg_val |= val;
|
||||
HAL_REG_WRITE(soc, reg_addr, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_enable_pri2tid_map_6432()
|
||||
* @hal_soc_hdl: HAL SoC handle
|
||||
* @val : PRI to TID value
|
||||
* @ppe_vp_idx: Map number
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
|
||||
static inline
|
||||
void hal_tx_enable_pri2tid_map_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
bool val, uint8_t ppe_vp_idx)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr, reg_val = 0;
|
||||
|
||||
reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE,
|
||||
ppe_vp_idx);
|
||||
|
||||
/*
|
||||
* Drop precedence is enabled by default.
|
||||
*/
|
||||
reg_val = HAL_REG_READ(soc, reg_addr);
|
||||
|
||||
reg_val &=
|
||||
~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK;
|
||||
|
||||
reg_val |=
|
||||
(val &
|
||||
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) <<
|
||||
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT;
|
||||
|
||||
HAL_REG_WRITE(soc, reg_addr, reg_val);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_update_ppe_pri2tid_6432()
|
||||
* @hal_soc_hdl: HAL SoC handle
|
||||
* @pri: INT_PRI
|
||||
* @tid: Wi-Fi TID
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
|
||||
static inline
|
||||
void hal_tx_update_ppe_pri2tid_6432(hal_soc_handle_t hal_soc_hdl,
|
||||
uint8_t pri, uint8_t tid)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr, reg_val = 0, mask, shift;
|
||||
|
||||
/*
|
||||
* INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15
|
||||
* is in MAP1 register.
|
||||
*/
|
||||
switch (pri) {
|
||||
case 0 ... 9:
|
||||
reg_addr =
|
||||
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
mask =
|
||||
(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri));
|
||||
shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3);
|
||||
break;
|
||||
case 10 ... 15:
|
||||
pri = pri - 10;
|
||||
reg_addr =
|
||||
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
mask =
|
||||
(HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri));
|
||||
shift =
|
||||
HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3);
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
reg_val = HAL_REG_READ(soc, reg_addr);
|
||||
reg_val &= ~mask;
|
||||
reg_val |= (pri << shift) & mask;
|
||||
|
||||
HAL_REG_WRITE(soc, reg_addr, reg_val);
|
||||
}
|
||||
|
||||
/*
|
||||
* hal_tx_dump_ppe_vp_entry_6432()
|
||||
* @hal_soc_hdl: HAL SoC handle
|
||||
*
|
||||
* Return: void
|
||||
*/
|
||||
static inline
|
||||
void hal_tx_dump_ppe_vp_entry_6432(hal_soc_handle_t hal_soc_hdl)
|
||||
{
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
|
||||
uint32_t reg_addr, reg_val = 0, i;
|
||||
|
||||
for (i = 0; i < HAL_PPE_VP_ENTRIES_MAX; i++) {
|
||||
reg_addr =
|
||||
HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(
|
||||
MAC_TCL_REG_REG_BASE,
|
||||
i);
|
||||
reg_val = HAL_REG_READ(soc, reg_addr);
|
||||
hal_verbose_debug("%d: 0x%x\n", i, reg_val);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* hal_tx_get_num_ppe_vp_tbl_entries_6432()
|
||||
* @hal_soc_hdl: HAL SoC handle
|
||||
*
|
||||
* Return: Number of PPE VP entries
|
||||
*/
|
||||
static
|
||||
uint32_t hal_tx_get_num_ppe_vp_tbl_entries_6432(hal_soc_handle_t hal_soc_hdl)
|
||||
{
|
||||
return HAL_PPE_VP_ENTRIES_MAX;
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_ppe2tcl_ring_halt_set_6432() - Enable ring halt for the ppe2tcl ring
|
||||
* @hal_soc: HAL SoC context
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
static void hal_tx_ppe2tcl_ring_halt_set_6432(hal_soc_handle_t hal_soc)
|
||||
{
|
||||
uint32_t cmn_reg_addr;
|
||||
uint32_t regval;
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||
|
||||
cmn_reg_addr =
|
||||
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
|
||||
/* Enable RING_HALT */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval |=
|
||||
(1 <<
|
||||
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_ppe2tcl_ring_halt_reset_6432() - Disable ring halt for the ppe2tcl ring
|
||||
* @hal_soc: HAL SoC context
|
||||
*
|
||||
* Return: none
|
||||
*/
|
||||
static void hal_tx_ppe2tcl_ring_halt_reset_6432(hal_soc_handle_t hal_soc)
|
||||
{
|
||||
uint32_t cmn_reg_addr;
|
||||
uint32_t regval;
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||
|
||||
cmn_reg_addr =
|
||||
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
|
||||
/* Disable RING_HALT */
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval &= ~(1 <<
|
||||
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT);
|
||||
|
||||
HAL_REG_WRITE(soc, cmn_reg_addr, regval);
|
||||
}
|
||||
|
||||
/**
|
||||
* hal_tx_ppe2tcl_ring_halt_done_6432() - Check if ring halt is done for ppe2tcl ring
|
||||
* @hal_soc: HAL SoC context
|
||||
*
|
||||
* Return: true if halt done
|
||||
*/
|
||||
static bool hal_tx_ppe2tcl_ring_halt_done_6432(hal_soc_handle_t hal_soc)
|
||||
{
|
||||
uint32_t cmn_reg_addr;
|
||||
uint32_t regval;
|
||||
struct hal_soc *soc = (struct hal_soc *)hal_soc;
|
||||
|
||||
cmn_reg_addr =
|
||||
HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE);
|
||||
|
||||
regval = HAL_REG_READ(soc, cmn_reg_addr);
|
||||
regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT);
|
||||
|
||||
return(!!regval);
|
||||
}
|
||||
|
||||
/* TX MONITOR */
|
||||
#ifdef QCA_MONITOR_2_0_SUPPORT
|
||||
|
||||
#if defined(TX_MONITOR_WORD_MASK)
|
||||
typedef struct tx_fes_setup_compact_6432 hal_tx_fes_setup_t;
|
||||
struct tx_fes_setup_compact_6432 {
|
||||
/* DWORD - 0 */
|
||||
uint32_t schedule_id;
|
||||
/* DWORD - 1 */
|
||||
uint32_t reserved_1a : 7, // [0: 6]
|
||||
transmit_start_reason : 3, // [7: 9]
|
||||
reserved_1b : 13, // [10: 22]
|
||||
number_of_users : 6, // [28: 23]
|
||||
MU_type : 1, // [29]
|
||||
reserved_1c : 2; // [30]
|
||||
/* DWORD - 2 */
|
||||
uint32_t reserved_2a : 4, // [0: 3]
|
||||
ndp_frame : 2, // [4: 5]
|
||||
txbf : 1, // [6]
|
||||
reserved_2b : 3, // [7: 9]
|
||||
static_bandwidth : 3, // [12: 10]
|
||||
reserved_2c : 1, // [13]
|
||||
transmission_contains_MU_RTS : 1, // [14]
|
||||
reserved_2d : 17; // [15: 31]
|
||||
/* DWORD - 3 */
|
||||
uint32_t reserved_3a : 15, // [0: 14]
|
||||
mu_ndp : 1, // [15]
|
||||
reserved_3b : 11, // [16: 26]
|
||||
ndpa : 1, // [27]
|
||||
reserved_3c : 4; // [28: 31]
|
||||
};
|
||||
#endif
|
||||
#endif /* QCA_MONITOR_2_0_SUPPORT */
|
||||
#endif /* _HAL_6432_TX_H_ */
|
||||
236
hif/src/qcn6432def.c
Fichier normal
236
hif/src/qcn6432def.c
Fichier normal
@@ -0,0 +1,236 @@
|
||||
/*
|
||||
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "qdf_module.h"
|
||||
|
||||
#if defined(QCN6432_HEADERS_DEF)
|
||||
|
||||
#undef UMAC
|
||||
#define WLAN_HEADERS 1
|
||||
|
||||
#include "wcss_version.h"
|
||||
#include "wcss_seq_hwiobase.h"
|
||||
#include "wfss_ce_reg_seq_hwioreg.h"
|
||||
|
||||
#define MISSING 0
|
||||
|
||||
#define SOC_RESET_CONTROL_OFFSET MISSING
|
||||
#define GPIO_PIN0_OFFSET MISSING
|
||||
#define GPIO_PIN1_OFFSET MISSING
|
||||
#define GPIO_PIN0_CONFIG_MASK MISSING
|
||||
#define GPIO_PIN1_CONFIG_MASK MISSING
|
||||
#define LOCAL_SCRATCH_OFFSET 0x18
|
||||
#define GPIO_PIN10_OFFSET MISSING
|
||||
#define GPIO_PIN11_OFFSET MISSING
|
||||
#define GPIO_PIN12_OFFSET MISSING
|
||||
#define GPIO_PIN13_OFFSET MISSING
|
||||
#define MBOX_BASE_ADDRESS MISSING
|
||||
#define INT_STATUS_ENABLE_ERROR_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_ERROR_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_CPU_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_CPU_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_COUNTER_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_COUNTER_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_LSB MISSING
|
||||
#define INT_STATUS_ENABLE_MBOX_DATA_MASK MISSING
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB MISSING
|
||||
#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK MISSING
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB MISSING
|
||||
#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK MISSING
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_LSB MISSING
|
||||
#define COUNTER_INT_STATUS_ENABLE_BIT_MASK MISSING
|
||||
#define INT_STATUS_ENABLE_ADDRESS MISSING
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_LSB MISSING
|
||||
#define CPU_INT_STATUS_ENABLE_BIT_MASK MISSING
|
||||
#define HOST_INT_STATUS_ADDRESS MISSING
|
||||
#define CPU_INT_STATUS_ADDRESS MISSING
|
||||
#define ERROR_INT_STATUS_ADDRESS MISSING
|
||||
#define ERROR_INT_STATUS_WAKEUP_MASK MISSING
|
||||
#define ERROR_INT_STATUS_WAKEUP_LSB MISSING
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK MISSING
|
||||
#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB MISSING
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_MASK MISSING
|
||||
#define ERROR_INT_STATUS_TX_OVERFLOW_LSB MISSING
|
||||
#define COUNT_DEC_ADDRESS MISSING
|
||||
#define HOST_INT_STATUS_CPU_MASK MISSING
|
||||
#define HOST_INT_STATUS_CPU_LSB MISSING
|
||||
#define HOST_INT_STATUS_ERROR_MASK MISSING
|
||||
#define HOST_INT_STATUS_ERROR_LSB MISSING
|
||||
#define HOST_INT_STATUS_COUNTER_MASK MISSING
|
||||
#define HOST_INT_STATUS_COUNTER_LSB MISSING
|
||||
#define RX_LOOKAHEAD_VALID_ADDRESS MISSING
|
||||
#define WINDOW_DATA_ADDRESS MISSING
|
||||
#define WINDOW_READ_ADDR_ADDRESS MISSING
|
||||
#define WINDOW_WRITE_ADDR_ADDRESS MISSING
|
||||
/* GPIO Register */
|
||||
#define GPIO_ENABLE_W1TS_LOW_ADDRESS MISSING
|
||||
#define GPIO_PIN0_CONFIG_LSB MISSING
|
||||
#define GPIO_PIN0_PAD_PULL_LSB MISSING
|
||||
#define GPIO_PIN0_PAD_PULL_MASK MISSING
|
||||
/* SI reg */
|
||||
#define SI_CONFIG_ERR_INT_MASK MISSING
|
||||
#define SI_CONFIG_ERR_INT_LSB MISSING
|
||||
|
||||
#define RTC_SOC_BASE_ADDRESS MISSING
|
||||
#define RTC_WMAC_BASE_ADDRESS MISSING
|
||||
#define SOC_CORE_BASE_ADDRESS MISSING
|
||||
#define WLAN_MAC_BASE_ADDRESS MISSING
|
||||
#define GPIO_BASE_ADDRESS MISSING
|
||||
#define ANALOG_INTF_BASE_ADDRESS MISSING
|
||||
#define CE0_BASE_ADDRESS MISSING
|
||||
#define CE1_BASE_ADDRESS MISSING
|
||||
#define CE_COUNT 12
|
||||
#define CE_WRAPPER_BASE_ADDRESS MISSING
|
||||
#define SI_BASE_ADDRESS MISSING
|
||||
#define DRAM_BASE_ADDRESS MISSING
|
||||
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_LSB MISSING
|
||||
#define WLAN_SYSTEM_SLEEP_DISABLE_MASK MISSING
|
||||
#define CLOCK_CONTROL_OFFSET MISSING
|
||||
#define CLOCK_CONTROL_SI0_CLK_MASK MISSING
|
||||
#define RESET_CONTROL_SI0_RST_MASK MISSING
|
||||
#define WLAN_RESET_CONTROL_OFFSET MISSING
|
||||
#define WLAN_RESET_CONTROL_COLD_RST_MASK MISSING
|
||||
#define WLAN_RESET_CONTROL_WARM_RST_MASK MISSING
|
||||
#define CPU_CLOCK_OFFSET MISSING
|
||||
|
||||
#define CPU_CLOCK_STANDARD_LSB MISSING
|
||||
#define CPU_CLOCK_STANDARD_MASK MISSING
|
||||
#define LPO_CAL_ENABLE_LSB MISSING
|
||||
#define LPO_CAL_ENABLE_MASK MISSING
|
||||
#define WLAN_SYSTEM_SLEEP_OFFSET MISSING
|
||||
|
||||
#define SOC_CHIP_ID_ADDRESS MISSING
|
||||
#define SOC_CHIP_ID_REVISION_MASK MISSING
|
||||
#define SOC_CHIP_ID_REVISION_LSB MISSING
|
||||
#define SOC_CHIP_ID_REVISION_MSB MISSING
|
||||
|
||||
#define FW_IND_EVENT_PENDING MISSING
|
||||
#define FW_IND_INITIALIZED MISSING
|
||||
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK MISSING
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
|
||||
#define MSDU_LINK_EXT_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB MISSING
|
||||
#define MSDU_LINK_EXT_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB MISSING
|
||||
|
||||
#define SR_WR_INDEX_ADDRESS MISSING
|
||||
#define DST_WATERMARK_ADDRESS MISSING
|
||||
|
||||
#define DST_WR_INDEX_ADDRESS MISSING
|
||||
#define SRC_WATERMARK_ADDRESS MISSING
|
||||
#define SRC_WATERMARK_LOW_MASK MISSING
|
||||
#define SRC_WATERMARK_HIGH_MASK MISSING
|
||||
#define DST_WATERMARK_LOW_MASK MISSING
|
||||
#define DST_WATERMARK_HIGH_MASK MISSING
|
||||
#define CURRENT_SRRI_ADDRESS MISSING
|
||||
#define CURRENT_DRRI_ADDRESS MISSING
|
||||
#define HOST_IS_SRC_RING_HIGH_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_SRC_RING_LOW_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_DST_RING_HIGH_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_DST_RING_LOW_WATERMARK_MASK MISSING
|
||||
#define HOST_IS_ADDRESS MISSING
|
||||
#define MISC_IS_ADDRESS MISSING
|
||||
#define HOST_IS_COPY_COMPLETE_MASK MISSING
|
||||
#define CE_WRAPPER_BASE_ADDRESS MISSING
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_ADDRESS MISSING
|
||||
#define CE_DDR_ADDRESS_FOR_RRI_LOW MISSING
|
||||
#define CE_DDR_ADDRESS_FOR_RRI_HIGH MISSING
|
||||
|
||||
#define HOST_CMEM_ADDRESS 0xC100000
|
||||
#define HOST_CE_ADDRESS SOC_WFSS_CE_REG_BASE
|
||||
#define HOST_IE_ADDRESS \
|
||||
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
|
||||
WFSS_CE_COMMON_REG_REG_BASE_OFFS)
|
||||
#define HOST_IE_REG1_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT
|
||||
#define HOST_IE_ADDRESS_2 \
|
||||
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR(\
|
||||
WFSS_CE_COMMON_REG_REG_BASE_OFFS)
|
||||
#define HOST_IE_REG2_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT
|
||||
#define HOST_IE_ADDRESS_3 \
|
||||
HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR(\
|
||||
WFSS_CE_COMMON_REG_REG_BASE_OFFS)
|
||||
#define HOST_IE_REG3_CE_LSB HWIO_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT
|
||||
|
||||
#define HOST_IE_COPY_COMPLETE_MASK MISSING
|
||||
#define SR_BA_ADDRESS MISSING
|
||||
#define SR_BA_ADDRESS_HIGH MISSING
|
||||
#define SR_SIZE_ADDRESS MISSING
|
||||
#define CE_CTRL1_ADDRESS MISSING
|
||||
#define CE_CTRL1_DMAX_LENGTH_MASK MISSING
|
||||
#define DR_BA_ADDRESS MISSING
|
||||
#define DR_BA_ADDRESS_HIGH MISSING
|
||||
#define DR_SIZE_ADDRESS MISSING
|
||||
#define CE_CMD_REGISTER MISSING
|
||||
#define CE_MSI_ADDRESS MISSING
|
||||
#define CE_MSI_ADDRESS_HIGH MISSING
|
||||
#define CE_MSI_DATA MISSING
|
||||
#define CE_MSI_ENABLE_BIT MISSING
|
||||
#define MISC_IE_ADDRESS MISSING
|
||||
#define MISC_IS_AXI_ERR_MASK MISSING
|
||||
#define MISC_IS_DST_ADDR_ERR_MASK MISSING
|
||||
#define MISC_IS_SRC_LEN_ERR_MASK MISSING
|
||||
#define MISC_IS_DST_MAX_LEN_VIO_MASK MISSING
|
||||
#define MISC_IS_DST_RING_OVERFLOW_MASK MISSING
|
||||
#define MISC_IS_SRC_RING_OVERFLOW_MASK MISSING
|
||||
#define SRC_WATERMARK_LOW_LSB MISSING
|
||||
#define SRC_WATERMARK_HIGH_LSB MISSING
|
||||
#define DST_WATERMARK_LOW_LSB MISSING
|
||||
#define DST_WATERMARK_HIGH_LSB MISSING
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_MASK MISSING
|
||||
#define CE_WRAPPER_INTERRUPT_SUMMARY_HOST_MSI_LSB MISSING
|
||||
#define CE_CTRL1_DMAX_LENGTH_LSB MISSING
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_MASK MISSING
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_MASK MISSING
|
||||
#define CE_CTRL1_SRC_RING_BYTE_SWAP_EN_LSB MISSING
|
||||
#define CE_CTRL1_DST_RING_BYTE_SWAP_EN_LSB MISSING
|
||||
#define CE_CTRL1_IDX_UPD_EN_MASK MISSING
|
||||
#define CE_WRAPPER_DEBUG_OFFSET MISSING
|
||||
#define CE_WRAPPER_DEBUG_SEL_MSB MISSING
|
||||
#define CE_WRAPPER_DEBUG_SEL_LSB MISSING
|
||||
#define CE_WRAPPER_DEBUG_SEL_MASK MISSING
|
||||
#define CE_DEBUG_OFFSET MISSING
|
||||
#define CE_DEBUG_SEL_MSB MISSING
|
||||
#define CE_DEBUG_SEL_LSB MISSING
|
||||
#define CE_DEBUG_SEL_MASK MISSING
|
||||
#define CE0_BASE_ADDRESS MISSING
|
||||
#define CE1_BASE_ADDRESS MISSING
|
||||
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_ENABLES MISSING
|
||||
#define A_WIFI_APB_3_A_WCMN_APPS_CE_INTR_STATUS MISSING
|
||||
|
||||
#define QCN6432_BOARD_DATA_SZ MISSING
|
||||
#define QCN6432_BOARD_EXT_DATA_SZ MISSING
|
||||
|
||||
#define MY_TARGET_DEF QCN6432_TARGETDEF
|
||||
#define MY_HOST_DEF QCN6432_HOSTDEF
|
||||
#define MY_CEREG_DEF QCN6432_CE_TARGETDEF
|
||||
#define MY_TARGET_BOARD_DATA_SZ QCN6432_BOARD_DATA_SZ
|
||||
#define MY_TARGET_BOARD_EXT_DATA_SZ QCN6432_BOARD_EXT_DATA_SZ
|
||||
#include "targetdef.h"
|
||||
#include "hostdef.h"
|
||||
qdf_export_symbol(QCN6432_CE_TARGETDEF);
|
||||
#else
|
||||
#include "common_drv.h"
|
||||
#include "targetdef.h"
|
||||
#include "hostdef.h"
|
||||
struct targetdef_s *QCN6432_TARGETDEF;
|
||||
struct hostdef_s *QCN6432_HOSTDEF;
|
||||
#endif /*QCN6432_HEADERS_DEF */
|
||||
qdf_export_symbol(QCN6432_TARGETDEF);
|
||||
qdf_export_symbol(QCN6432_HOSTDEF);
|
||||
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