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disp: msm: dp: calculate mvid and nvid dividers with in DP driver

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Change removes the dependency of reading MVID and NVID settings
from dispcc registers and calculates the values locally in displayport
driver.

Change-Id: I9ad66aea44a3cbc0f739060c49e23d389022a48a
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This commit is contained in:
Vara Reddy
2022-02-25 14:32:12 -08:00
parent 280c93b729
commit 7230476c9c
4 changed files with 31 additions and 32 deletions
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59
msm/dp/dp_catalog_v420.c
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@@ -1,22 +1,15 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*/ */
#include "dp_catalog.h" #include "dp_catalog.h"
#include "dp_reg.h" #include "dp_reg.h"
#include "dp_debug.h" #include "dp_debug.h"
#include "dp_pll.h"
#define MMSS_DP_PIXEL_BASE_V130 (0x1A8) #include <linux/rational.h>
#define MMSS_DP_PIXEL1_BASE_V130 (0x1C0)
#define MMSS_DP_PIXEL_BASE_V140 (0x1BC)
#define MMSS_DP_PIXEL1_BASE_V140 (0x1D4)
#define MMSS_DP_M_OFF (0x8)
#define MMSS_DP_N_OFF (0xC)
#define dp_catalog_get_priv_v420(x) ({ \ #define dp_catalog_get_priv_v420(x) ({ \
struct dp_catalog *catalog; \ struct dp_catalog *catalog; \
@@ -169,15 +162,15 @@ static void dp_catalog_aux_clear_hw_int_v420(struct dp_catalog_aux *aux)
static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel, static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
u32 rate, u32 stream_rate_khz) u32 rate, u32 stream_rate_khz)
{ {
u32 pixel_m, pixel_n; u32 mvid, nvid, mvid_off = 0, nvid_off = 0;
u32 mvid, nvid, reg_off = 0, mvid_off = 0, nvid_off = 0; u32 div, pixel_div = 0, rate_vco_div = 0;
u32 const nvid_fixed = 0x8000; u32 const nvid_fixed = 0x8000;
u32 const link_rate_hbr2 = 540000; u32 const link_rate_hbr2 = 540000;
u32 const link_rate_hbr3 = 810000; u32 const link_rate_hbr3 = 810000;
struct dp_catalog *dp_catalog; struct dp_catalog *dp_catalog;
struct dp_catalog_private_v420 *catalog; struct dp_catalog_private_v420 *catalog;
struct dp_io_data *io_data; struct dp_io_data *io_data;
u32 version; unsigned long num, den;
if (!panel || !rate) { if (!panel || !rate) {
DP_ERR("invalid input\n"); DP_ERR("invalid input\n");
@@ -192,28 +185,34 @@ static void dp_catalog_panel_config_msa_v420(struct dp_catalog_panel *panel,
dp_catalog = container_of(panel, struct dp_catalog, panel); dp_catalog = container_of(panel, struct dp_catalog, panel);
catalog = container_of(dp_catalog->sub, struct dp_catalog_private_v420, sub); catalog = container_of(dp_catalog->sub, struct dp_catalog_private_v420, sub);
version = dp_catalog_get_dp_core_version(dp_catalog); io_data = catalog->io->dp_pll;
io_data = catalog->io->dp_mmss_cc; div = dp_read(DP_PHY_VCO_DIV);
if (version >= 0x10040000) { div &= 0x03;
if (panel->stream_id == DP_STREAM_1)
reg_off = MMSS_DP_PIXEL1_BASE_V140; if (div == 0)
else pixel_div = 6;
reg_off = MMSS_DP_PIXEL_BASE_V140; else if (div == 1)
} else { pixel_div = 2;
if (panel->stream_id == DP_STREAM_1) else if (div == 2)
reg_off = MMSS_DP_PIXEL1_BASE_V130; pixel_div = 4;
else
reg_off = MMSS_DP_PIXEL_BASE_V130; if (!pixel_div) {
DP_ERR("Invalid pixel mux divider, not setting software mvid and nvid\n");
return;
} }
rate_vco_div = (rate * 10) / pixel_div;
pixel_m = dp_read(reg_off + MMSS_DP_M_OFF); rational_best_approximation(rate_vco_div, (stream_rate_khz / 2),
pixel_n = dp_read(reg_off + MMSS_DP_N_OFF); (unsigned long)(1 << 16) - 1,
DP_DEBUG("pixel_m=0x%x, pixel_n=0x%x\n", pixel_m, pixel_n); (unsigned long)(1 << 16) - 1, &den, &num);
mvid = (pixel_m & 0xFFFF) * 5; den = ~(den - num);
nvid = (0xFFFF & (~pixel_n)) + (pixel_m & 0xFFFF); den = den & 0xFFFF;
mvid = (num & 0xFFFF) * 5;
nvid = (0xFFFF & (~den)) + (num & 0xFFFF);
if (nvid < nvid_fixed) { if (nvid < nvid_fixed) {
u32 temp; u32 temp;

2
msm/dp/dp_pll.h
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@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved. * Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/ */
@@ -16,6 +17,7 @@
#define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL #define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
#define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL #define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL
#define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL #define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL
#define DP_PHY_VCO_DIV 0x0070
#define dp_pll_get_base(x) pll->io.x->io.base #define dp_pll_get_base(x) pll->io.x->io.base

1
msm/dp/dp_pll_4nm.c
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@@ -36,7 +36,6 @@
#define DP_PHY_AUX_CFG1 0x0024 #define DP_PHY_AUX_CFG1 0x0024
#define DP_PHY_AUX_CFG2 0x0028 #define DP_PHY_AUX_CFG2 0x0028
#define DP_PHY_VCO_DIV 0x0070
#define DP_PHY_TX0_TX1_LANE_CTL 0x0078 #define DP_PHY_TX0_TX1_LANE_CTL 0x0078
#define DP_PHY_TX2_TX3_LANE_CTL 0x009C #define DP_PHY_TX2_TX3_LANE_CTL 0x009C

1
msm/dp/dp_pll_5nm.c
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@@ -37,7 +37,6 @@
#define DP_PHY_AUX_CFG1 0x0024 #define DP_PHY_AUX_CFG1 0x0024
#define DP_PHY_AUX_CFG2 0x0028 #define DP_PHY_AUX_CFG2 0x0028
#define DP_PHY_VCO_DIV 0x0070
#define DP_PHY_TX0_TX1_LANE_CTL 0x0078 #define DP_PHY_TX0_TX1_LANE_CTL 0x0078
#define DP_PHY_TX2_TX3_LANE_CTL 0x009C #define DP_PHY_TX2_TX3_LANE_CTL 0x009C