From 71d305df0bf24a6c95fb79636cb18ec74679adff Mon Sep 17 00:00:00 2001 From: Jigar Agrawal Date: Fri, 11 Sep 2020 11:22:14 -0700 Subject: [PATCH] msm: camera: cpas: Add cpas support for camera v680 platform Add register info, initial QoS settings info to program camera static settings for chipsets having camera v680. CRs-fixed: 2792910 Change-Id: I8f054a8466035b8388ea84f3a50f562838611990 Signed-off-by: Mukund Madhusudan Atre Signed-off-by: Jigar Agrawal --- drivers/cam_cpas/cpas_top/cam_cpastop_hw.c | 17 + drivers/cam_cpas/cpas_top/cam_cpastop_hw.h | 120 +- drivers/cam_cpas/cpas_top/cpastop_v680_100.h | 1213 ++++++++++++++++++ drivers/cam_cpas/include/cam_cpas_api.h | 18 + 4 files changed, 1330 insertions(+), 38 deletions(-) create mode 100644 drivers/cam_cpas/cpas_top/cpastop_v680_100.h diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c index b0e07e0adb..ed1a951fa5 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.c @@ -29,6 +29,7 @@ #include "cpastop_v520_100.h" #include "cpastop_v545_100.h" #include "cpastop_v570_200.h" +#include "cpastop_v680_100.h" struct cam_camnoc_info *camnoc_info; @@ -175,6 +176,10 @@ static int cam_cpas_translate_camera_cpas_version_id( *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_570; break; + case CAM_CPAS_CAMERA_VERSION_680: + *cam_version_id = CAM_CPAS_CAMERA_VERSION_ID_680; + break; + default: CAM_ERR(CAM_CPAS, "Invalid cam version %u", cam_version); @@ -810,6 +815,9 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw, case CAM_CPAS_TITAN_570_V200: camnoc_info = &cam570_cpas200_camnoc_info; break; + case CAM_CPAS_TITAN_680_V100: + camnoc_info = &cam680_cpas100_camnoc_info; + break; default: CAM_ERR(CAM_CPAS, "Camera Version not supported %d.%d.%d", hw_caps->camera_version.major, @@ -853,6 +861,15 @@ static int cam_cpastop_setup_qos_settings(struct cam_hw_info *cpas_hw, "Invalid selection mask 0x%x for hw 0x%x", selection_mask, soc_info->hw_version); break; + case CAM_CPAS_TITAN_680_V100: + if ((selection_mask & CAM_CPAS_QOS_CUSTOM_SETTINGS_MASK) || + (selection_mask & CAM_CPAS_QOS_DEFAULT_SETTINGS_MASK)) + camnoc_info = &cam680_cpas100_camnoc_info; + else + CAM_ERR(CAM_CPAS, + "Invalid selection mask 0x%x for hw 0x%x", + selection_mask, soc_info->hw_version); + break; default: CAM_WARN(CAM_CPAS, "QoS selection not supported for 0x%x", soc_info->hw_version); diff --git a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h index c3ec408c5f..dd1e1f5273 100644 --- a/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h +++ b/drivers/cam_cpas/cpas_top/cam_cpastop_hw.h @@ -12,49 +12,65 @@ /** * enum cam_camnoc_hw_irq_type - Enum for camnoc error types * - * @CAM_CAMNOC_HW_IRQ_SLAVE_ERROR: Each slave port in CAMNOC (3 QSB ports and - * 1 QHB port) has an error logger. The error - * observed at any slave port is logged into - * the error logger register and an IRQ is - * triggered - * @CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR: Triggered if any error - * detected in the IFE UBWC- - * Stats encoder instance + * @CAM_CAMNOC_HW_IRQ_SLAVE_ERROR : Each slave port in CAMNOC + * (3 QSB ports and 1 QHB port) + * has an error logger. The + * error observed at any slave + * port is logged into the + * error logger register and + * an IRQ is triggered + * @CAM_CAMNOC_HW_IRQ_IFE_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the IFE UBWC + * encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR : Triggered if any error + * detected in the IFE UBWC- + * Stats encoder instance * @CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_1_ENCODE_ERROR: Triggered if any error - * detected in the IFE UBWC- - * Stats 1 encoder instance - * @CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR : Triggered if any error - * detected in the IFE0 UBWC - * encoder instance - * @CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR : Triggered if any error - * detected in the IFE1 or IFE3 - * UBWC encoder instance - * @CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR: Triggered if any error - * detected in the IPE1/BPS read - * path decoder instance - * @CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR : Triggered if any error detected - * in the IPE0 read path decoder - * instance - * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR: Triggered if any error - * detected in the IPE/BPS - * UBWC decoder instance - * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR: Triggered if any error - * detected in the IPE/BPS UBWC - * encoder instance - * @CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR: Triggered if any UBWC error - * is detected in IFE0 write path - * @CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR: Triggered if any UBWC error - * is detected in IFE1 write path - * @CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT : Triggered when the QHS_ICP - * slave times out after 4000 - * AHB cycles - * @CAM_CAMNOC_HW_IRQ_RESERVED1 : Reserved - * @CAM_CAMNOC_HW_IRQ_RESERVED2 : Reserved - * @CAM_CAMNOC_HW_IRQ_CAMNOC_TEST : To test the IRQ logic + * detected in the IFE UBWC- + * Stats 1 encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE02_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the IFE0 UBWC + * encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE13_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the IFE1 or + * IFE3 UBWC encoder instance + * @CAM_CAMNOC_HW_IRQ_IFE0_UBWC_ENCODE_ERROR : Triggered if any UBWC error + * is detected in IFE0 write + * path + * @CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR : Triggered if any UBWC error + * is detected in IFE1 write + * path slave times out after + * 4000 AHB cycles + * @CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the IPE + * UBWC encoder instance + * @CAM_CAMNOC_HW_IRQ_BPS_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the BPS + * UBWC encoder instance + * @CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR : Triggered if any error + * detected in the IPE1/BPS + * read path decoder instance + * @CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR : Triggered if any error + * detected in the IPE0 read + * path decoder instance + * @CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR : Triggered if any error + * detected in the IPE1 read + * path decoder instance + * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR : Triggered if any error + * detected in the IPE/BPS + * UBWC decoder instance + * @CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR : Triggered if any error + * detected in the IPE/BPS + * UBWC encoder instance + * @CAM_CAMNOC_HW_IRQ_RESERVED1 : Reserved + * @CAM_CAMNOC_HW_IRQ_RESERVED2 : Reserved + * @CAM_CAMNOC_HW_IRQ_CAMNOC_TEST : To test the IRQ logic */ enum cam_camnoc_hw_irq_type { CAM_CAMNOC_HW_IRQ_SLAVE_ERROR = CAM_CAMNOC_IRQ_SLAVE_ERROR, + CAM_CAMNOC_HW_IRQ_IFE_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IFE_UBWC_ENCODE_ERROR, CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_ENCODE_ERROR = CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR, CAM_CAMNOC_HW_IRQ_IFE_UBWC_STATS_1_ENCODE_ERROR = @@ -67,10 +83,16 @@ enum cam_camnoc_hw_irq_type { CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR, CAM_CAMNOC_HW_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR = CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_IPE_UBWC_ENCODE_ERROR, + CAM_CAMNOC_HW_IRQ_BPS_UBWC_ENCODE_ERROR = + CAM_CAMNOC_IRQ_BPS_UBWC_ENCODE_ERROR, CAM_CAMNOC_HW_IRQ_IPE1_BPS_UBWC_DECODE_ERROR = CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR, CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR = CAM_CAMNOC_IRQ_IPE0_UBWC_DECODE_ERROR, + CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR = + CAM_CAMNOC_IRQ_IPE1_UBWC_DECODE_ERROR, CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_DECODE_ERROR = CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR, CAM_CAMNOC_HW_IRQ_IPE_BPS_UBWC_ENCODE_ERROR = @@ -88,9 +110,17 @@ enum cam_camnoc_hw_irq_type { * each of these ports. * * @CAM_CAMNOC_CDM: Indicates CDM HW connection to camnoc + * @CAM_CAMNOC_SFE_RD: Indicates read data from all SFEs to cammnoc * @CAM_CAMNOC_IFE02: Indicates IFE0, IFE2 HW connection to camnoc * @CAM_CAMNOC_IFE13: Indicates IFE1, IFE3 HW connection to camnoc + * @CAM_CAMNOC_IFE_LITE: Indicates all IFE lites connection to camnoc * @CAM_CAMNOC_IFE_LINEAR: Indicates linear data from all IFEs to cammnoc + * @CAM_CAMNOC_IFE_LINEAR_STATS: Indicates linear and stats data from certan + * IFEs to cammnoc + * @CAM_CAMNOC_IFE_LINEAR_STATS_1: Indicates linear and stats data from certan + * IFEs to cammnoc + * @CAM_CAMNOC_IFE_PDAF: Indicates pdaf data from all IFEs to cammnoc + * @CAM_CAMNOC_IFE_UBWC: Indicates ubwc from all IFEs to cammnoc * @CAM_CAMNOC_IFE_UBWC_STATS: Indicates ubwc+stats from certain IFEs to cammnoc * @CAM_CAMNOC_IFE_UBWC_STATS_1: Indicates ubwc+stats from certain * IFEs to cammnoc @@ -108,10 +138,14 @@ enum cam_camnoc_hw_irq_type { * connection to camnoc * @CAM_CAMNOC_IPE_VID_DISP_WRITE: Indicates IPE's VID/DISP Wrire HW * connection to camnoc + * @CAM_CAMNOC_IPE_WR: Indicates IPE HW's write connection to camnoc * @CAM_CAMNOC_IPE0_RD: Indicates IPE's Read0 HW connection to camnoc + * @CAM_CAMNOC_IPE1_RD: Indicates IPE's Read1 HW connection to camnoc * @CAM_CAMNOC_IPE1_BPS_RD: Indicates IPE's Read1 + BPS Read HW connection * to camnoc * @CAM_CAMNOC_IPE_BPS_WR: Indicates IPE+BPS Write HW connection to camnoc + * @CAM_CAMNOC_BPS_WR: Indicates BPS HW's write connection to camnoc + * @CAM_CAMNOC_BPS_RD: Indicates BPS HW's read connection to camnoc * @CAM_CAMNOC_JPEG: Indicates JPEG HW connection to camnoc * @CAM_CAMNOC_FD: Indicates FD HW connection to camnoc * @CAM_CAMNOC_ICP: Indicates ICP HW connection to camnoc @@ -122,9 +156,15 @@ enum cam_camnoc_hw_irq_type { */ enum cam_camnoc_port_type { CAM_CAMNOC_CDM, + CAM_CAMNOC_SFE_RD, CAM_CAMNOC_IFE02, CAM_CAMNOC_IFE13, + CAM_CAMNOC_IFE_LITE, CAM_CAMNOC_IFE_LINEAR, + CAM_CAMNOC_IFE_LINEAR_STATS, + CAM_CAMNOC_IFE_LINEAR_STATS_1, + CAM_CAMNOC_IFE_PDAF, + CAM_CAMNOC_IFE_UBWC, CAM_CAMNOC_IFE_UBWC_STATS, CAM_CAMNOC_IFE_UBWC_STATS_1, CAM_CAMNOC_IFE_RDI_WR, @@ -137,9 +177,13 @@ enum cam_camnoc_port_type { CAM_CAMNOC_IPE_BPS_LRME_READ, CAM_CAMNOC_IPE_BPS_LRME_WRITE, CAM_CAMNOC_IPE_VID_DISP_WRITE, + CAM_CAMNOC_IPE_WR, CAM_CAMNOC_IPE0_RD, + CAM_CAMNOC_IPE1_RD, CAM_CAMNOC_IPE1_BPS_RD, CAM_CAMNOC_IPE_BPS_WR, + CAM_CAMNOC_BPS_WR, + CAM_CAMNOC_BPS_RD, CAM_CAMNOC_JPEG, CAM_CAMNOC_FD, CAM_CAMNOC_ICP, diff --git a/drivers/cam_cpas/cpas_top/cpastop_v680_100.h b/drivers/cam_cpas/cpas_top/cpastop_v680_100.h new file mode 100644 index 0000000000..fd1b1e8e56 --- /dev/null +++ b/drivers/cam_cpas/cpas_top/cpastop_v680_100.h @@ -0,0 +1,1213 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _CPASTOP_V680_100_H_ +#define _CPASTOP_V680_100_H_ + +#define TEST_IRQ_ENABLE 0 + +static struct cam_camnoc_irq_sbm cam_cpas_v680_100_irq_sbm = { + .sbm_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2240, /* CAM_NOC_SBM_FAULTINEN0_LOW */ + .value = 0x2 | /* SBM_FAULTINEN0_LOW_PORT1_MASK */ + 0x04 | /* SBM_FAULTINEN0_LOW_PORT2_MASK */ + 0x08 | /* SBM_FAULTINEN0_LOW_PORT3_MASK */ + 0x10 | /* SBM_FAULTINEN0_LOW_PORT4_MASK */ + 0x20 | /* SBM_FAULTINEN0_LOW_PORT5_MASK */ + (TEST_IRQ_ENABLE ? + 0x80 : /* SBM_FAULTINEN0_LOW_PORT7_MASK */ + 0x0), + }, + .sbm_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2248, /* CAM_NOC_SBM_FAULTINSTATUS0_LOW */ + }, + .sbm_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2280, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + .value = TEST_IRQ_ENABLE ? 0x5 : 0x1, + } +}; + +static struct cam_camnoc_irq_err + cam_cpas_v680_100_irq_err[] = { + { + .irq_type = CAM_CAMNOC_HW_IRQ_SLAVE_ERROR, + .enable = false, + .sbm_port = 0x1, /* SBM_FAULTINSTATUS0_LOW_PORT0_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2008, /* CAM_NOC_ERL_MAINCTL_LOW */ + .value = 1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2010, /* CAM_NOC_ERL_ERRVLD_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x2018, /* CAM_NOC_ERL_ERRCLR_LOW */ + .value = 1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IFE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x20, /* SBM_FAULTINSTATUS0_LOW_PORT5_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x59A0, /* IFE_UBWC_NIU_ENCERREN_LOW */ + .value = 0xF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5990, /* IFE_UBWC_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5998, /* IFE_UBWC_NIU_ENCERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_BPS_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x2, /* SBM_FAULTINSTATUS0_LOW_PORT1_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x7A0, /* CAM_NOC_BPS_WR_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x790, /* CAM_NOC_BPS_WR_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x798, /* CAM_NOC_BPS_WR_NIU_ENCERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE0_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x4, /* SBM_FAULTINSTATUS0_LOW_PORT2_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x5F20, /* CAM_NOC_IPE_0_RD_NIU_DECERREN_LOW */ + .value = 0xFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x5F10, /* CAM_NOC_IPE_0_RD_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x5F18, /* CAM_NOC_IPE_0_RD_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE1_UBWC_DECODE_ERROR, + .enable = true, + .sbm_port = 0x8, /* SBM_FAULTINSTATUS0_LOW_PORT3_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6520, /* CAM_NOC_IPE_1_RD_NIU_DECERREN_LOW */ + .value = 0XFF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6510, /* CAM_NOC_IPE_1_RD_NIU_DECERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x6518, /* CAM_NOC_IPE_1_RD_NIU_DECERRCLR_LOW */ + .value = 0X1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_IPE_UBWC_ENCODE_ERROR, + .enable = true, + .sbm_port = 0x10, /* SBM_FAULTINSTATUS0_LOW_PORT4_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x6BA0, /* CAM_NOC_IPE_WR_NIU_ENCERREN_LOW */ + .value = 0XF, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x6B90, /* CAM_NOC_IPE_WR_NIU_ENCERRSTATUS_LOW */ + }, + .err_clear = { + .access_type = CAM_REG_TYPE_WRITE, + .enable = true, + .offset = 0x6B98, /* CAM_NOC_IPE_WR_NIU_ENCERRCLR_LOW */ + .value = 0x1, + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_AHB_TIMEOUT, + .enable = false, + .sbm_port = 0x40, /* SBM_FAULTINSTATUS0_LOW_PORT6_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x1, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED1, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_RESERVED2, + .enable = false, + }, + { + .irq_type = CAM_CAMNOC_HW_IRQ_CAMNOC_TEST, + .enable = TEST_IRQ_ENABLE ? true : false, + .sbm_port = 0x80, /* SBM_FAULTINSTATUS0_LOW_PORT7_MASK */ + .err_enable = { + .access_type = CAM_REG_TYPE_READ_WRITE, + .enable = true, + .offset = 0x2288, /* CAM_NOC_SBM_FLAGOUTSET0_LOW */ + .value = 0x5, + }, + .err_status = { + .access_type = CAM_REG_TYPE_READ, + .enable = true, + .offset = 0x2290, /* CAM_NOC_SBM_FLAGOUTSTATUS0_LOW */ + }, + .err_clear = { + .enable = false, /* CAM_NOC_SBM_FLAGOUTCLR0_LOW */ + }, + }, +}; + +static struct cam_camnoc_specific + cam_cpas_v680_100_camnoc_specific[] = { + { + .port_type = CAM_CAMNOC_IFE_UBWC, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5830, /* IFE_UBWC_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5834, /* IFE_UBWC_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5838, /* IFE_UBWC_URGENCY_LOW */ + .value = 0x1B30, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5840, /* IFE_UBWC_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5848, /* IFE_UBWC_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A08, /* IFE_UBWC_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A20, /* IFE_UBWC_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5A24, /* IFE_UBWC_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_RDI_WR, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5230, /* IFE_RDI_WR_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5234, /* IFE_RDI_WR_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5238, /* IFE_RDI_WR_URGENCY_LOW */ + .value = 0x1B30, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5240, /* IFE_RDI_WR_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5248, /* IFE_RDI_WR_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5408, /* IFE_RDI_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5420, /* IFE_RDI_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5424, /* IFE_RDI_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_PDAF, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4c30, /* IFE_PDAF_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4c34, /* IFE_PDAF_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4c38, /* IFE_PDAF_URGENCY_LOW */ + .value = 0x1B30, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4c40, /* IFE_PDAF_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4c48, /* IFE_PDAF_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4e08, /* IFE_PDAF_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4e20, /* IFE_PDAF_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4e24, /* IFE_PDAF_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_LINEAR_STATS, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4030, /* IFE_LINEAR_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4034, /* IFE_LINEAR_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4038, /* IFE_LINEAR_URGENCY_LOW */ + .value = 0x1B30, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4040, /* IFE_LINEAR_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4048, /* IFE_LINEAR_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4208, /* IFE_LINEAR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4220, /* IFE_LINEAR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4224, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_LINEAR_STATS_1, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8230, /* IFE_LINEAR_1_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8234, /* IFE_LINEAR_1_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8238, /* IFE_LINEAR_1_URGENCY_LOW */ + .value = 0x1B30, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8240, /* IFE_LINEAR_1_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8248, /* IFE_LINEAR_1_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8408, /* IFE_LINEAR_1_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8420, /* IFE_LINEAR_1_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x8424, /* IFE_LINEAR_1_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IFE_LITE, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4630, /* IFE_LITE_PRIORITYLUT_LOW */ + .value = 0x66665433, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4634, /* IFE_LITE_PRIORITYLUT_HIGH */ + .value = 0x66666666, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4638, /* IFE_LITE_URGENCY_LOW */ + .value = 0x1B30, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4640, /* IFE_LITE_DANGERLUT_LOW */ + .value = 0xffffff00, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4648, /* IFE_LITE_SAFELUT_LOW */ + .value = 0x000f, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4808, /* IFE_LITE_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4820, /* IFE_LITE_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x4824, /* IFE_LITE_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_SFE_RD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7030, /* SFE_RD_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7034, /* SFE_RD_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7038, /* SFE_RD_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7040, /* SFE_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7048, /* SFE_RD_SAFELUT_LOW */ + .value = 0x0, + }, + .ubwc_ctl = { + /* + * Do not explicitly set ubwc config register. + * Power on default values are taking care of required + * register settings. + */ + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7208, /* SFE_RD_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7220, /* SFE_RD_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7224, /* SFE_RD_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IPE_WR, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6a30, /* IPE_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6a34, /* IPE_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6a38, /* IPE_WR_URGENCY_LOW */ + .value = 0x30, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6a40, /* IPE_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6a48, /* IPE_WR_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6c08, /* IPE_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6c20, /* IPE_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6c24, /* IPE_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_BPS_WR, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x630, /* BPS_WR_PRIORITYLUT_LOW */ + .value = 0x33333333, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x634, /* BPS_WR_PRIORITYLUT_HIGH */ + .value = 0x33333333, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x638, /* BPS_WR_URGENCY_LOW */ + .value = 0x30, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x640, /* BPS_WR_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x648, /* BPS_WR_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x808, /* BPS_WR_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x820, /* BPS_WR_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x824, /* BPS_WR_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_BPS_RD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x30, /* BPS_RD_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x34, /* BPS_RD_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x38, /* BPS_RD_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x40, /* BPS_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x48, /* BPS_RD_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x208, /* BPS_RD_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x220, /* BPS_RD_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x224, /* BPS_RD_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_JPEG, + .enable = true, + .priority_lut_low = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7c30, /* JPEG_PRIORITYLUT_LOW */ + .value = 0x22222222, + }, + .priority_lut_high = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7c34, /* JPEG_PRIORITYLUT_HIGH */ + .value = 0x22222222, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7c38, /* JPEG_URGENCY_LOW */ + .value = 0x22, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7c40, /* JPEG_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7c48, /* JPEG_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7e08, /* JPEG_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7e20, /* JPEG_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7e24, /* JPEG_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IPE0_RD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E30, /* IPE0_RD_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E34, /* IPE0_RD_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E38, /* IPE0_RD_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E40, /* IPE0_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5E48, /* IPE0_RD_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x5F08, /* IPE0_RD_DECCTL_LOW */ + .value = 1, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6008, /* IPE0_RD_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6020, /* IPE0_RD_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6024, /* IPE0_RD_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_IPE1_RD, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6430, /* IPE1_RD_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6434, /* IPE1_RD_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6438, /* IPE1_RD_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6440, /* IPE1_RD_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6448, /* IPE1_RD_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6608, /* IPE1_RD_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6620, /* IPE1_RD_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x6624, /* IPE1_RD_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_CDM, + .enable = true, + .priority_lut_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3830, /* CDM_PRIORITYLUT_LOW */ + .value = 0x0, + }, + .priority_lut_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3834, /* CDM_PRIORITYLUT_HIGH */ + .value = 0x0, + }, + .urgency = { + .enable = true, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3838, /* CDM_URGENCY_LOW */ + .value = 0x3, + }, + .danger_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3840, /* CDM_DANGERLUT_LOW */ + .value = 0x0, + }, + .safe_lut = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3848, /* CDM_SAFELUT_LOW */ + .value = 0xffff, + }, + .ubwc_ctl = { + .enable = false, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3a08, /* CDM_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3a20, /* CDM_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x3a24, /* CDM_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, + { + .port_type = CAM_CAMNOC_ICP, + .enable = true, + .flag_out_set0_low = { + .enable = true, + .access_type = CAM_REG_TYPE_WRITE, + .masked_value = 0, + .offset = 0x2288, + .value = 0x100000, + }, + .qosgen_mainctl = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x7688, /* ICP_QOSGEN_MAINCTL */ + .value = 0x0, + }, + .qosgen_shaping_low = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x76A0, /* ICP_QOSGEN_SHAPING_LOW */ + .value = 0x0, + }, + .qosgen_shaping_high = { + .enable = false, + .access_type = CAM_REG_TYPE_READ_WRITE, + .masked_value = 0, + .offset = 0x76A4, /* ICP_QOSGEN_SHAPING_HIGH */ + .value = 0x0, + }, + }, +}; + +static struct cam_camnoc_err_logger_info cam680_cpas100_err_logger_offsets = { + .mainctrl = 0x2008, /* ERRLOGGER_MAINCTL_LOW */ + .errvld = 0x2010, /* ERRLOGGER_ERRVLD_LOW */ + .errlog0_low = 0x2020, /* ERRLOGGER_ERRLOG0_LOW */ + .errlog0_high = 0x2024, /* ERRLOGGER_ERRLOG0_HIGH */ + .errlog1_low = 0x2028, /* ERRLOGGER_ERRLOG1_LOW */ + .errlog1_high = 0x202c, /* ERRLOGGER_ERRLOG1_HIGH */ + .errlog2_low = 0x2030, /* ERRLOGGER_ERRLOG2_LOW */ + .errlog2_high = 0x2034, /* ERRLOGGER_ERRLOG2_HIGH */ + .errlog3_low = 0x2038, /* ERRLOGGER_ERRLOG3_LOW */ + .errlog3_high = 0x203c, /* ERRLOGGER_ERRLOG3_HIGH */ +}; + +static struct cam_cpas_hw_errata_wa_list cam680_cpas100_errata_wa_list = { + .camnoc_flush_slave_pending_trans = { + .enable = false, + .data.reg_info = { + .access_type = CAM_REG_TYPE_READ, + .offset = 0x2300, /* sbm_SenseIn0_Low */ + .mask = 0xE0000, /* Bits 17, 18, 19 */ + .value = 0, /* expected to be 0 */ + }, + }, +}; + +static struct cam_camnoc_info cam680_cpas100_camnoc_info = { + .specific = &cam_cpas_v680_100_camnoc_specific[0], + .specific_size = ARRAY_SIZE(cam_cpas_v680_100_camnoc_specific), + .irq_sbm = &cam_cpas_v680_100_irq_sbm, + .irq_err = &cam_cpas_v680_100_irq_err[0], + .irq_err_size = ARRAY_SIZE(cam_cpas_v680_100_irq_err), + .err_logger = &cam680_cpas100_err_logger_offsets, + .errata_wa_list = &cam680_cpas100_errata_wa_list, +}; + +#endif /* _CPASTOP_V680_100_H_ */ + diff --git a/drivers/cam_cpas/include/cam_cpas_api.h b/drivers/cam_cpas/include/cam_cpas_api.h index 2380c5527a..5d288f54f6 100644 --- a/drivers/cam_cpas/include/cam_cpas_api.h +++ b/drivers/cam_cpas/include/cam_cpas_api.h @@ -67,6 +67,7 @@ enum cam_cpas_camera_version { CAM_CPAS_CAMERA_VERSION_580 = 0x00050800, CAM_CPAS_CAMERA_VERSION_545 = 0x00050405, CAM_CPAS_CAMERA_VERSION_570 = 0x00050700, + CAM_CPAS_CAMERA_VERSION_680 = 0x00060800, CAM_CPAS_CAMERA_VERSION_MAX }; @@ -98,6 +99,7 @@ enum cam_cpas_camera_version_map_id { CAM_CPAS_CAMERA_VERSION_ID_540 = 0x6, CAM_CPAS_CAMERA_VERSION_ID_545 = 0x7, CAM_CPAS_CAMERA_VERSION_ID_570 = 0x8, + CAM_CPAS_CAMERA_VERSION_ID_680 = 0x9, CAM_CPAS_CAMERA_VERSION_ID_MAX }; @@ -135,6 +137,7 @@ enum cam_cpas_hw_version { CAM_CPAS_TITAN_520_V100 = 0x520100, CAM_CPAS_TITAN_545_V100 = 0x545100, CAM_CPAS_TITAN_570_V200 = 0x570200, + CAM_CPAS_TITAN_680_V100 = 0x680100, CAM_CPAS_TITAN_MAX }; @@ -146,6 +149,8 @@ enum cam_cpas_hw_version { * observed at any slave port is logged into * the error logger register and an IRQ is * triggered + * @CAM_CAMNOC_IRQ_IFE_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IFE UBWC encoder instance * @CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR: Triggered if any error detected * in the IFE UBWC-Stats encoder * instance @@ -159,12 +164,21 @@ enum cam_cpas_hw_version { * @CAM_CAMNOC_IRQ_IFE1_WR_UBWC_ENCODE_ERROR : Triggered if any error detected * in the IFE1 UBWC encoder * instance + * @CAM_CAMNOC_IRQ_IPE_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the IPE write path encoder + * instance + * @CAM_CAMNOC_IRQ_BPS_UBWC_ENCODE_ERROR : Triggered if any error detected + * in the BPS write path encoder + * instance * @CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR: Triggered if any error detected * in the IPE1/BPS read path decoder * instance * @CAM_CAMNOC_IRQ_IPE0_UBWC_DECODE_ERROR : Triggered if any error detected * in the IPE0 read path decoder * instance + * @CAM_CAMNOC_IRQ_IPE1_UBWC_DECODE_ERROR : Triggered if any error detected + * in the IPE1 read path decoder + * instance * @CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR: Triggered if any error detected * in the IPE/BPS UBWC decoder * instance @@ -176,14 +190,18 @@ enum cam_cpas_hw_version { */ enum cam_camnoc_irq_type { CAM_CAMNOC_IRQ_SLAVE_ERROR, + CAM_CAMNOC_IRQ_IFE_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_IFE_UBWC_STATS_ENCODE_ERROR, CAM_CAMNOC_IRQ_IFE_UBWC_STATS_1_ENCODE_ERROR, CAM_CAMNOC_IRQ_IFE02_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_IFE13_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_IFE0_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_IFE1_WRITE_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_IPE_UBWC_ENCODE_ERROR, + CAM_CAMNOC_IRQ_BPS_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_IPE1_BPS_UBWC_DECODE_ERROR, CAM_CAMNOC_IRQ_IPE0_UBWC_DECODE_ERROR, + CAM_CAMNOC_IRQ_IPE1_UBWC_DECODE_ERROR, CAM_CAMNOC_IRQ_IPE_BPS_UBWC_DECODE_ERROR, CAM_CAMNOC_IRQ_IPE_BPS_UBWC_ENCODE_ERROR, CAM_CAMNOC_IRQ_AHB_TIMEOUT,