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@@ -44,6 +44,8 @@
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(DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
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(DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
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#define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
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#define DP_INTR_MASK5 (DP_INTERRUPT_STATUS5 << 2)
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+#define DP_TPG_PATTERN_MAX 9
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+#define DP_TPG_PATTERN_DEFAULT 8
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#define dp_catalog_fill_io(x) { \
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#define dp_catalog_fill_io(x) { \
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catalog->io.x = parser->get_io(parser, #x); \
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catalog->io.x = parser->get_io(parser, #x); \
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@@ -1417,8 +1419,7 @@ static void dp_catalog_ctrl_usb_reset(struct dp_catalog_ctrl *ctrl, bool flip)
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wmb();
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wmb();
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}
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}
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-static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
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- bool enable)
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+static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel, u32 pattern)
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{
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{
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struct dp_catalog_private *catalog;
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struct dp_catalog_private *catalog;
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struct dp_io_data *io_data;
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struct dp_io_data *io_data;
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@@ -1441,7 +1442,7 @@ static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
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else if (panel->stream_id == DP_STREAM_1)
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else if (panel->stream_id == DP_STREAM_1)
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io_data = catalog->io.dp_p1;
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io_data = catalog->io.dp_p1;
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- if (!enable) {
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+ if (!pattern) {
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dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x0);
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dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x0);
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dp_write(MMSS_DP_BIST_ENABLE, 0x0);
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dp_write(MMSS_DP_BIST_ENABLE, 0x0);
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reg = dp_read(MMSS_DP_TIMING_ENGINE_EN);
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reg = dp_read(MMSS_DP_TIMING_ENGINE_EN);
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@@ -1451,6 +1452,9 @@ static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
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return;
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return;
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}
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}
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+ if (pattern > DP_TPG_PATTERN_MAX)
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+ pattern = DP_TPG_PATTERN_DEFAULT;
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+
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dp_write(MMSS_DP_INTF_HSYNC_CTL,
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dp_write(MMSS_DP_INTF_HSYNC_CTL,
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panel->hsync_ctl);
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panel->hsync_ctl);
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dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F0,
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dp_write(MMSS_DP_INTF_VSYNC_PERIOD_F0,
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@@ -1472,7 +1476,7 @@ static void dp_catalog_panel_tpg_cfg(struct dp_catalog_panel *panel,
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dp_write(MMSS_DP_INTF_POLARITY_CTL, 0);
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dp_write(MMSS_DP_INTF_POLARITY_CTL, 0);
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wmb(); /* ensure TPG registers are programmed */
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wmb(); /* ensure TPG registers are programmed */
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- dp_write(MMSS_DP_TPG_MAIN_CONTROL, 0x100);
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+ dp_write(MMSS_DP_TPG_MAIN_CONTROL, (1 << pattern));
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dp_write(MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
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dp_write(MMSS_DP_TPG_VIDEO_CONFIG, 0x5);
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wmb(); /* ensure TPG config is programmed */
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wmb(); /* ensure TPG config is programmed */
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dp_write(MMSS_DP_BIST_ENABLE, 0x1);
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dp_write(MMSS_DP_BIST_ENABLE, 0x1);
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