msm: camera: isp: Add support for MMU prefetch for IFE/SFE WMs
Add support to enable MMU prefetch for IFE/SFE write clients. Also added debugfs to disable this feature. CRs-Fixed: 2841729 Change-Id: I8581fdb182f2578e1730c426028f1628d24c8124 Signed-off-by: Karthik Anantha Ram <kartanan@codeaurora.org>
This commit is contained in:
@@ -6280,6 +6280,20 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args)
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}
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}
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/* set IFE bus WR MMU config */
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for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) {
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if (g_ife_hw_mgr.ife_devices[i]) {
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rc = g_ife_hw_mgr.ife_devices[i]->hw_intf->hw_ops.process_cmd(
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g_ife_hw_mgr.ife_devices[i]->hw_intf->hw_priv,
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CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG,
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&g_ife_hw_mgr.debug_cfg.disable_ife_mmu_prefetch,
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sizeof(g_ife_hw_mgr.debug_cfg.disable_ife_mmu_prefetch));
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if (rc)
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CAM_DBG(CAM_ISP,
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"Failed to set IFE_%d bus wr debug cfg", i);
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}
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}
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if (ctx->flags.need_csid_top_cfg) {
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list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid,
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list) {
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@@ -11235,6 +11249,9 @@ static int cam_ife_hw_mgr_debug_register(void)
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g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_sfe_debug);
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dbgfileptr = debugfs_create_file("sfe_sensor_diag_sel", 0644,
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g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_sfe_sensor_diag_debug);
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dbgfileptr = debugfs_create_bool("disable_ife_mmu_prefetch", 0644,
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g_ife_hw_mgr.debug_cfg.dentry,
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&g_ife_hw_mgr.debug_cfg.disable_ife_mmu_prefetch);
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if (IS_ERR(dbgfileptr)) {
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if (PTR_ERR(dbgfileptr) == -ENODEV)
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@@ -50,6 +50,7 @@ enum cam_ife_ctx_master_type {
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* @enable_req_dump: Enable request dump on HW errors
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* @per_req_reg_dump: Enable per request reg dump
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* @disable_ubwc_comp: Disable UBWC compression
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* @disable_ife_mmu_prefetch: Disable MMU prefetch for IFE bus WR
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*
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*/
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struct cam_ife_hw_mgr_debug {
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@@ -63,6 +64,7 @@ struct cam_ife_hw_mgr_debug {
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bool enable_req_dump;
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bool per_req_reg_dump;
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bool disable_ubwc_comp;
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bool disable_ife_mmu_prefetch;
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};
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/**
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@@ -156,6 +156,7 @@ enum cam_isp_hw_cmd_type {
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CAM_ISP_HW_NOTIFY_OVERFLOW,
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CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN,
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CAM_ISP_HW_CMD_GET_PATH_PORT_MAP,
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CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG,
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CAM_ISP_HW_CMD_MAX,
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};
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@@ -420,6 +420,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00000A80,
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.debug_status_0 = 0x00000A84,
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.debug_status_1 = 0x00000A88,
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.mmu_prefetch_cfg = 0x00000A60,
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.mmu_prefetch_max_offset = 0x00000A64,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_0,
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},
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/* BUS Client 1 LCR */
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@@ -447,6 +449,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00000B80,
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.debug_status_0 = 0x00000B84,
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.debug_status_1 = 0x00000B88,
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.mmu_prefetch_cfg = 0x00000B60,
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.mmu_prefetch_max_offset = 0x00000B64,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_1,
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},
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/* BUS Client 2 STATS_BE_0 */
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@@ -474,6 +478,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00000C80,
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.debug_status_0 = 0x00000C84,
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.debug_status_1 = 0x00000C88,
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.mmu_prefetch_cfg = 0x00000C60,
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.mmu_prefetch_max_offset = 0x00000C64,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_2,
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},
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/* BUS Client 3 STATS_BHIST_0 */
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@@ -501,6 +507,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00000D80,
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.debug_status_0 = 0x00000D84,
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.debug_status_1 = 0x00000D88,
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.mmu_prefetch_cfg = 0x00000D60,
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.mmu_prefetch_max_offset = 0x00000D64,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_2,
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},
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/* BUS Client 4 STATS_BE_1 */
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@@ -528,6 +536,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00000E80,
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.debug_status_0 = 0x00000E84,
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.debug_status_1 = 0x00000E88,
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.mmu_prefetch_cfg = 0x00000E60,
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.mmu_prefetch_max_offset = 0x00000E64,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_3,
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},
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/* BUS Client 5 STATS_BHIST_1 */
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@@ -555,6 +565,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00000F80,
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.debug_status_0 = 0x00000F84,
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.debug_status_1 = 0x00000F88,
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.mmu_prefetch_cfg = 0x00000F60,
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.mmu_prefetch_max_offset = 0x00000F64,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_3,
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},
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/* BUS Client 6 STATS_BE_2 */
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@@ -582,6 +594,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00001080,
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.debug_status_0 = 0x00001084,
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.debug_status_1 = 0x00001088,
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.mmu_prefetch_cfg = 0x00001060,
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.mmu_prefetch_max_offset = 0x00001064,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_4,
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},
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/* BUS Client 7 STATS_BHIST_2 */
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@@ -609,6 +623,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00001180,
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.debug_status_0 = 0x00001184,
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.debug_status_1 = 0x00001188,
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.mmu_prefetch_cfg = 0x00001160,
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.mmu_prefetch_max_offset = 0x00001164,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_4,
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},
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/* BUS Client 8 RDI0 */
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@@ -636,6 +652,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00001280,
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.debug_status_0 = 0x00001284,
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.debug_status_1 = 0x00001288,
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.mmu_prefetch_cfg = 0x00001260,
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.mmu_prefetch_max_offset = 0x00001264,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_5,
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},
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/* BUS Client 9 RDI1 */
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@@ -663,6 +681,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00001380,
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.debug_status_0 = 0x00001384,
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.debug_status_1 = 0x00001388,
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.mmu_prefetch_cfg = 0x00001360,
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.mmu_prefetch_max_offset = 0x00001364,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_6,
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},
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/* BUS Client 10 RDI2 */
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@@ -690,6 +710,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00001480,
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.debug_status_0 = 0x00001484,
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.debug_status_1 = 0x00001488,
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.mmu_prefetch_cfg = 0x00001460,
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.mmu_prefetch_max_offset = 0x00001464,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_7,
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},
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/* BUS Client 11 RDI3 */
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@@ -717,6 +739,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00001580,
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.debug_status_0 = 0x00001584,
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.debug_status_1 = 0x00001588,
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.mmu_prefetch_cfg = 0x00001560,
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.mmu_prefetch_max_offset = 0x00001564,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_8,
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},
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/* BUS Client 12 RDI4 */
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@@ -744,6 +768,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
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.debug_status_cfg = 0x00001680,
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.debug_status_0 = 0x00001684,
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.debug_status_1 = 0x00001688,
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.mmu_prefetch_cfg = 0x00001660,
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.mmu_prefetch_max_offset = 0x00001664,
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.comp_group = CAM_SFE_BUS_WR_COMP_GRP_9,
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},
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},
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@@ -44,6 +44,7 @@ struct cam_sfe_hw_core_info {
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#define SFE_DEBUG_ENABLE_SENSOR_DIAG_INFO BIT(1)
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#define SFE_DEBUG_ENABLE_FRAME_COUNTER BIT(2)
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#define SFE_DEBUG_ENABLE_RD_DONE_IRQ BIT(3)
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#define SFE_DEBUG_DISABLE_MMU_PREFETCH BIT(4)
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int cam_sfe_get_hw_caps(void *device_priv,
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void *get_hw_cap_args, uint32_t arg_size);
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@@ -677,6 +677,16 @@ static int cam_sfe_bus_start_wm(struct cam_isp_resource_node *wm_res)
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rsrc_data->hw_regs->line_done_cfg);
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}
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if (!(common_data->sfe_debug_cfg & SFE_DEBUG_DISABLE_MMU_PREFETCH)) {
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cam_io_w_mb(1, common_data->mem_base +
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rsrc_data->hw_regs->mmu_prefetch_cfg);
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cam_io_w_mb(0xFFFFFFFF, common_data->mem_base +
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rsrc_data->hw_regs->mmu_prefetch_max_offset);
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CAM_DBG(CAM_SFE, "SFE: %u WM: %u MMU prefetch enabled",
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rsrc_data->common_data->core_index,
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rsrc_data->index);
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}
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/* Enable WM */
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cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base +
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rsrc_data->hw_regs->cfg);
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@@ -103,6 +103,8 @@ struct cam_sfe_bus_reg_offset_bus_client {
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uint32_t debug_status_cfg;
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uint32_t debug_status_0;
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uint32_t debug_status_1;
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uint32_t mmu_prefetch_cfg;
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uint32_t mmu_prefetch_max_offset;
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uint32_t comp_group;
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};
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@@ -531,6 +531,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
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case CAM_ISP_HW_CMD_DUMP_BUS_INFO:
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case CAM_ISP_HW_CMD_GET_RES_FOR_MID:
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case CAM_ISP_HW_CMD_QUERY_BUS_CAP:
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case CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG:
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rc = core_info->vfe_bus->hw_ops.process_cmd(
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core_info->vfe_bus->bus_priv, cmd_type, cmd_args,
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arg_size);
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@@ -106,6 +106,7 @@ struct cam_vfe_bus_ver3_common_data {
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bool support_consumed_addr;
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bool disable_ubwc_comp;
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bool init_irq_subscribed;
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bool disable_mmu_prefetch;
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cam_hw_mgr_event_cb_func event_cb;
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int rup_irq_handle[CAM_VFE_BUS_VER3_SRC_GRP_MAX];
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uint32_t pack_align_shift;
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@@ -1343,6 +1344,18 @@ static int cam_vfe_bus_ver3_start_wm(struct cam_isp_resource_node *wm_res)
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cam_io_w_mb(val, common_data->mem_base + ubwc_regs->mode_cfg);
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}
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/* Validate for debugfs and mmu reg info for targets that don't list it */
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if (!(common_data->disable_mmu_prefetch) &&
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(rsrc_data->hw_regs->mmu_prefetch_cfg)) {
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cam_io_w_mb(1, common_data->mem_base +
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rsrc_data->hw_regs->mmu_prefetch_cfg);
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cam_io_w_mb(0xFFFFFFFF, common_data->mem_base +
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rsrc_data->hw_regs->mmu_prefetch_max_offset);
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CAM_DBG(CAM_SFE, "VFE: %d WM: %d MMU prefetch enabled",
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rsrc_data->common_data->core_index,
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rsrc_data->index);
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}
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/* Enable WM */
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cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base +
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rsrc_data->hw_regs->cfg);
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@@ -3678,6 +3691,14 @@ static int cam_vfe_bus_ver3_process_cmd(
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vfe_bus_cap->support_consumed_addr =
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bus_priv->common_data.support_consumed_addr;
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break;
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case CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG:
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bus_priv = (struct cam_vfe_bus_ver3_priv *) priv;
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bus_priv->common_data.disable_mmu_prefetch =
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(*((bool *)cmd_args));
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CAM_DBG(CAM_ISP, "IFE bus WR prefetch %s",
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bus_priv->common_data.disable_mmu_prefetch ?
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"disabled" : "enabled");
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break;
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default:
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CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d",
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cmd_type);
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@@ -3759,6 +3780,7 @@ int cam_vfe_bus_ver3_init(
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bus_priv->common_data.comp_config_needed =
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ver3_hw_info->comp_cfg_needed;
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bus_priv->common_data.init_irq_subscribed = false;
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bus_priv->common_data.disable_mmu_prefetch = false;
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bus_priv->common_data.pack_align_shift =
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ver3_hw_info->pack_align_shift;
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