qcacmn: Force wake PCIe for hsp register write
make sure both PCIe and device are force woken for the register writes for hsp, or write may fail. Earlier WAR is not required as we have root caused it. Change-Id: I350b810a6cef8eec46428e57f5b779f888552c1b CRs-Fixed: 2677342
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@@ -1787,29 +1787,6 @@ void hal_get_hw_hptp_generic(struct hal_soc *hal_soc,
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}
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}
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#if defined(WBM_IDLE_LSB_WRITE_CONFIRM_WAR)
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/**
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* hal_wbm_idle_lsb_write_confirm() - Check and update WBM_IDLE_LINK ring LSB
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* @srng: srng handle
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*
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* Return: None
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*/
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static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng)
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{
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if (srng->ring_id == HAL_SRNG_WBM_IDLE_LINK) {
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while (SRNG_SRC_REG_READ(srng, BASE_LSB) !=
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((unsigned int)srng->ring_base_paddr & 0xffffffff))
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SRNG_SRC_REG_WRITE(srng, BASE_LSB,
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srng->ring_base_paddr &
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0xffffffff);
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}
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}
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#else
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static void hal_wbm_idle_lsb_write_confirm(struct hal_srng *srng)
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{
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}
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#endif
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/**
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* hal_srng_src_hw_init - Private function to initialize SRNG
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* source ring HW
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@@ -1837,8 +1814,6 @@ void hal_srng_src_hw_init_generic(struct hal_soc *hal,
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}
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SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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hal_wbm_idle_lsb_write_confirm(srng);
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reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_SIZE),
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