Merge "msm: camera: cpas: Move camnoc register offsets to header" into camera-kernel.lnx.5.0

drivers/cam_cpas/cam_cpas_hw.c

@@ -16,6 +16,9 @@
 #include "cam_req_mgr_dev.h"
 #include "cam_smmu_api.h"
 #include "cam_compat.h"
+#include "cam_cpastop_hw.h"
+
+#define CAM_CPAS_LOG_BUF_LEN 512
 
 static uint cam_min_camnoc_ib_bw;
 module_param(cam_min_camnoc_ib_bw, uint, 0644);
@@ -484,6 +487,46 @@ static int cam_cpas_hw_reg_read(struct cam_hw_info *cpas_hw,
 	return rc;
 }
 
+static int cam_cpas_hw_dump_camnoc_buff_fill_info(
+	struct cam_hw_info *cpas_hw,
+	uint32_t client_handle)
+{
+	int rc = 0, i;
+	uint32_t val = 0;
+	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
+	struct cam_camnoc_info *camnoc_info =
+		(struct cam_camnoc_info *) cpas_core->camnoc_info;
+	char log_buf[CAM_CPAS_LOG_BUF_LEN] = {0};
+	size_t len = 0;
+
+	if (!camnoc_info) {
+		CAM_ERR(CAM_CPAS, "Invalid camnoc info for hw_version: 0x%x",
+			cpas_hw->soc_info.hw_version);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < camnoc_info->specific_size; i++) {
+		if ((!camnoc_info->specific[i].enable) ||
+			(!camnoc_info->specific[i].maxwr_low.enable))
+			continue;
+
+		rc = cam_cpas_hw_reg_read(cpas_hw, client_handle,
+			CAM_CPAS_REG_CAMNOC,
+			camnoc_info->specific[i].maxwr_low.offset, true, &val);
+		if (rc)
+			break;
+
+		len += scnprintf((log_buf + len), (CAM_CPAS_LOG_BUF_LEN - len),
+			" %s:[%d %d]", camnoc_info->specific[i].port_name,
+			(val & 0x7FF), (val & 0x7F0000) >> 16);
+	}
+
+	CAM_INFO(CAM_CPAS, "CAMNOC Fill level [Queued Pending] %s", log_buf);
+
+	return rc;
+
+}
+
 static int cam_cpas_util_set_camnoc_axi_clk_rate(
 	struct cam_hw_info *cpas_hw)
 {
@@ -1977,13 +2020,22 @@ static void cam_cpas_update_monitor_array(struct cam_hw_info *cpas_hw,
 	const char *identifier_string, int32_t identifier_value)
 {
 	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
+	struct cam_camnoc_info *camnoc_info =
+		(struct cam_camnoc_info *) cpas_core->camnoc_info;
 	struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
 	struct cam_cpas_private_soc *soc_private =
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
 	struct cam_cpas_monitor *entry;
 	int iterator;
-	int i;
+	int i, j = 0;
 	int reg_camnoc = cpas_core->regbase_index[CAM_CPAS_REG_CAMNOC];
+	uint32_t val = 0;
+
+	if (!camnoc_info) {
+		CAM_ERR(CAM_CPAS, "Invalid camnoc info for hw_version: 0x%x",
+			cpas_hw->soc_info.hw_version);
+		return;
+	}
 
 	CAM_CPAS_INC_MONITOR_HEAD(&cpas_core->monitor_head, &iterator);
 
@@ -2049,19 +2101,25 @@ static void cam_cpas_update_monitor_array(struct cam_hw_info *cpas_hw,
 			entry->be_mnoc);
 	}
 
-	entry->camnoc_fill_level[0] = cam_io_r_mb(
-		soc_info->reg_map[reg_camnoc].mem_base + 0xA20);
-	entry->camnoc_fill_level[1] = cam_io_r_mb(
-		soc_info->reg_map[reg_camnoc].mem_base + 0x1420);
-	entry->camnoc_fill_level[2] = cam_io_r_mb(
-		soc_info->reg_map[reg_camnoc].mem_base + 0x1A20);
+	for (i = 0; i < camnoc_info->specific_size; i++) {
+		if ((!camnoc_info->specific[i].enable) ||
+			(!camnoc_info->specific[i].maxwr_low.enable))
+			continue;
 
-	if (cpas_hw->soc_info.hw_version == CAM_CPAS_TITAN_580_V100) {
-		entry->camnoc_fill_level[3] = cam_io_r_mb(
-			soc_info->reg_map[reg_camnoc].mem_base + 0x7620);
-		entry->camnoc_fill_level[4] = cam_io_r_mb(
-			soc_info->reg_map[reg_camnoc].mem_base + 0x7420);
+		if (j >= CAM_CAMNOC_FILL_LVL_REG_INFO_MAX) {
+			CAM_WARN(CAM_CPAS,
+				"CPAS monitor reg info buffer full, max : %d", j);
+			break;
+		}
+
+		entry->camnoc_port_name[j] = camnoc_info->specific[i].port_name;
+		val = cam_io_r_mb(soc_info->reg_map[reg_camnoc].mem_base +
+			camnoc_info->specific[i].maxwr_low.offset);
+		entry->camnoc_fill_level[j] = val;
+		j++;
 	}
+
+	entry->num_camnoc_lvl_regs = j;
 }
 
 static void cam_cpas_dump_monitor_array(
@@ -2073,6 +2131,8 @@ static void cam_cpas_dump_monitor_array(
 	uint64_t ms, tmp, hrs, min, sec;
 	struct cam_cpas_monitor *entry;
 	struct timespec64 curr_timestamp;
+	char log_buf[CAM_CPAS_LOG_BUF_LEN];
+	size_t len;
 
 	if (!cpas_core->full_state_dump)
 		return;
@@ -2112,6 +2172,8 @@ static void cam_cpas_dump_monitor_array(
 		sec = do_div(tmp, 60);
 		min = do_div(tmp, 60);
 		hrs = do_div(tmp, 24);
+		memset(log_buf, 0, sizeof(log_buf));
+		len = 0;
 
 		CAM_INFO(CAM_CPAS,
 			"**** %llu:%llu:%llu.%llu : Index[%d] Identifier[%s][%d] camnoc=%lld, ahb=%d",
@@ -2136,18 +2198,15 @@ static void cam_cpas_dump_monitor_array(
 				entry->be_ddr, entry->be_mnoc, entry->be_shub);
 		}
 
-		CAM_INFO(CAM_CPAS,
-			"CAMNOC REG[Queued Pending] linear[%d %d] rdi0_wr[%d %d] ubwc_stats0[%d %d] ubwc_stats1[%d %d] rdi1_wr[%d %d]",
-			(entry->camnoc_fill_level[0] & 0x7FF),
-			(entry->camnoc_fill_level[0] & 0x7F0000) >> 16,
-			(entry->camnoc_fill_level[1] & 0x7FF),
-			(entry->camnoc_fill_level[1] & 0x7F0000) >> 16,
-			(entry->camnoc_fill_level[2] & 0x7FF),
-			(entry->camnoc_fill_level[2] & 0x7F0000) >> 16,
-			(entry->camnoc_fill_level[3] & 0x7FF),
-			(entry->camnoc_fill_level[3] & 0x7F0000) >> 16,
-			(entry->camnoc_fill_level[4] & 0x7FF),
-			(entry->camnoc_fill_level[4] & 0x7F0000) >> 16);
+		for (j = 0; j < entry->num_camnoc_lvl_regs; j++) {
+			len += scnprintf((log_buf + len),
+				(CAM_CPAS_LOG_BUF_LEN - len), " %s:[%d %d]",
+				entry->camnoc_port_name[j],
+				(entry->camnoc_fill_level[j] & 0x7FF),
+				(entry->camnoc_fill_level[j] & 0x7F0000) >> 16);
+		}
+
+		CAM_INFO(CAM_CPAS, "CAMNOC REG[Queued Pending] %s", log_buf);
 
 		index = (index + 1) % CAM_CPAS_MONITOR_MAX_ENTRIES;
 	}
@@ -2506,6 +2565,20 @@ static int cam_cpas_hw_process_cmd(void *hw_priv,
 		rc = cam_cpas_deactivate_cache_slice(hw_priv, type);
 	}
 		break;
+	case CAM_CPAS_HW_CMD_DUMP_BUFF_FILL_INFO: {
+		uint32_t *client_handle;
+
+		if (sizeof(uint32_t) != arg_size) {
+			CAM_ERR(CAM_CPAS, "cmd_type %d, size mismatch %d",
+				cmd_type, arg_size);
+			break;
+		}
+
+		client_handle = (uint32_t *)cmd_args;
+		rc = cam_cpas_hw_dump_camnoc_buff_fill_info(hw_priv,
+			*client_handle);
+		break;
+	}
 	default:
 		CAM_ERR(CAM_CPAS, "CPAS HW command not valid =%d", cmd_type);
 		break;

drivers/cam_cpas/cam_cpas_hw.h

@@ -20,6 +20,7 @@
 #define CAM_CPAS_MAX_GRAN_PATHS_PER_CLIENT   32
 #define CAM_CPAS_PATH_DATA_MAX               40
 #define CAM_CPAS_TRANSACTION_MAX             2
+#define CAM_CAMNOC_FILL_LVL_REG_INFO_MAX     6
 
 #define CAM_CPAS_AXI_MIN_MNOC_AB_BW   (2048 * 1024)
 #define CAM_CPAS_AXI_MIN_MNOC_IB_BW   (2048 * 1024)
@@ -220,6 +221,9 @@ struct cam_cpas_axi_port_debug_info {
  *           This indicates actual current clock plan
  * @be_shub: RPMH SHUB BCM BE (back-end) status register value.
  *           This indicates actual current clock plan
+ * @num_camnoc_lvl_regs: Number of enabled camnoc fill level
+ *           monitoring registers
+ * @camnoc_port_name: Camnoc port names
  * @camnoc_fill_level: Camnoc fill level register info
  */
 struct cam_cpas_monitor {
@@ -234,7 +238,9 @@ struct cam_cpas_monitor {
 	uint32_t                            fe_mnoc;
 	uint32_t                            be_mnoc;
 	uint32_t                            be_shub;
-	uint32_t                            camnoc_fill_level[5];
+	uint32_t                            num_camnoc_lvl_regs;
+	const char                         *camnoc_port_name[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
+	uint32_t                            camnoc_fill_level[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
 };
 
 /**
@@ -288,6 +294,7 @@ struct cam_cpas {
 	atomic64_t  monitor_head;
 	struct cam_cpas_monitor monitor_entries[CAM_CPAS_MONITOR_MAX_ENTRIES];
 	bool full_state_dump;
+	void *camnoc_info;
 };
 
 int cam_camsstop_get_internal_ops(struct cam_cpas_internal_ops *internal_ops);

drivers/cam_cpas/cam_cpas_hw_intf.h

@@ -46,6 +46,7 @@ enum cam_cpas_hw_cmd_process {
 	CAM_CPAS_HW_CMD_GET_SCID,
 	CAM_CPAS_HW_CMD_ACTIVATE_LLC,
 	CAM_CPAS_HW_CMD_DEACTIVATE_LLC,
+	CAM_CPAS_HW_CMD_DUMP_BUFF_FILL_INFO,
 	CAM_CPAS_HW_CMD_INVALID,
 };
 

drivers/cam_cpas/cam_cpas_intf.c

@@ -137,6 +137,31 @@ const char *cam_cpas_axi_util_trans_type_to_string(
 }
 EXPORT_SYMBOL(cam_cpas_axi_util_trans_type_to_string);
 
+int cam_cpas_dump_camnoc_buff_fill_info(uint32_t client_handle)
+{
+	int rc;
+
+	if (!CAM_CPAS_INTF_INITIALIZED()) {
+		CAM_ERR(CAM_CPAS, "cpas intf not initialized");
+		return -ENODEV;
+	}
+
+	if (g_cpas_intf->hw_intf->hw_ops.process_cmd) {
+		rc = g_cpas_intf->hw_intf->hw_ops.process_cmd(
+			g_cpas_intf->hw_intf->hw_priv,
+			CAM_CPAS_HW_CMD_DUMP_BUFF_FILL_INFO, &client_handle,
+			sizeof(uint32_t));
+		if (rc)
+			CAM_ERR(CAM_CPAS, "Failed in process_cmd, rc=%d", rc);
+	} else {
+		CAM_ERR(CAM_CPAS, "Invalid process_cmd ops");
+		rc = -EINVAL;
+	}
+
+	return rc;
+}
+EXPORT_SYMBOL(cam_cpas_dump_camnoc_buff_fill_info);
+
 bool cam_cpas_is_feature_supported(uint32_t flag, uint32_t hw_map,
 	uint32_t *fuse_val)
 {

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -878,6 +878,7 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw,
 {
 	int rc = 0;
 	struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
+	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
 	qchannel_info = NULL;
 
 	CAM_DBG(CAM_CPAS,
@@ -953,6 +954,7 @@ static int cam_cpastop_init_hw_version(struct cam_hw_info *cpas_hw,
 		break;
 	}
 
+	cpas_core->camnoc_info = camnoc_info;
 	return 0;
 }
 

drivers/cam_cpas/cpas_top/cam_cpastop_hw.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CPASTOP_HW_H_
@@ -200,6 +200,7 @@ enum cam_camnoc_port_type {
  * struct cam_camnoc_specific : CPAS camnoc specific settings
  *
  * @port_type: Port type
+ * @port_name: Port name
  * @enable: Whether to enable settings for this connection
  * @priority_lut_low: Priority Low LUT mapping for this connection
  * @priority_lut_high: Priority High LUT mapping for this connection
@@ -210,10 +211,12 @@ enum cam_camnoc_port_type {
  * @qosgen_mainctl: qosgen shaping control configuration for this connection
  * @qosgen_shaping_low: qosgen shaping low configuration for this connection
  * @qosgen_shaping_high: qosgen shaping high configuration for this connection
+ * @maxwr_low: maxwr low configuration for this connection
  *
  */
 struct cam_camnoc_specific {
 	enum cam_camnoc_port_type port_type;
+	const char *port_name;
 	bool enable;
 	struct cam_cpas_reg priority_lut_low;
 	struct cam_cpas_reg priority_lut_high;
@@ -225,6 +228,7 @@ struct cam_camnoc_specific {
 	struct cam_cpas_reg qosgen_mainctl;
 	struct cam_cpas_reg qosgen_shaping_low;
 	struct cam_cpas_reg qosgen_shaping_high;
+	struct cam_cpas_reg maxwr_low;
 };
 
 /**

drivers/cam_cpas/cpas_top/cpastop_v165_100.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
  #ifndef _CPASTOP_V165_100_H_
@@ -201,6 +201,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v165_100_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -245,6 +246,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE01234_RDI_WRITE,
+		.port_name = "IFE01234_RDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -289,9 +291,17 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x3620, /* IFE01234_RDI_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE01_NRDI_WRITE,
+		.port_name = "IFE01_NRDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -343,9 +353,17 @@ static struct cam_camnoc_specific
 			.offset = 0x3B88, /* IFE01_NRDI_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x3A20, /* IFE01_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE2_NRDI_WRITE,
+		.port_name = "IFE2_NRDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -397,9 +415,17 @@ static struct cam_camnoc_specific
 			.offset = 0x5588, /* IFE2_NRDI_ENCCTL_LOW */
 			.value = 0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5420, /* IFE2_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
+		.port_name = "IPE_BPS_LRME_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -455,6 +481,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
+		.port_name = "IPE_BPS_LRME_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -507,9 +534,17 @@ static struct cam_camnoc_specific
 			.offset = 0x2B88, /* IPE_BPS_LRME_WR_ENCCTL_LOW */
 			.value = 0,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2A20, /* IBL_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -551,10 +586,18 @@ static struct cam_camnoc_specific
 		.ubwc_ctl = {
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2620, /* JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		/*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/
 		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
 		.enable = true,
 		.flag_out_set0_low = {
 			.enable = true,

drivers/cam_cpas/cpas_top/cpastop_v170_200.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CPASTOP_V170_200_H_
@@ -203,6 +203,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v170_200_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -247,6 +248,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE02,
+		.port_name = "IFE02",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -292,9 +294,17 @@ static struct cam_camnoc_specific
 			.offset = 0x588, /* SPECIFIC_IFE02_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2420, /* IFE02_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE13,
+		.port_name = "IFE13",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -340,9 +350,17 @@ static struct cam_camnoc_specific
 			.offset = 0x988, /* SPECIFIC_IFE13_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2620, /* IFE13_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
+		.port_name = "IPE_BPS_LRME_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -393,6 +411,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
+		.port_name = "IPE_BPS_LRME_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -440,9 +459,17 @@ static struct cam_camnoc_specific
 			.offset = 0x1188, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2A20, /* IPE_BPS_LRME_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -482,13 +509,22 @@ static struct cam_camnoc_specific
 		.ubwc_ctl = {
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2C20, /* IPE_BPS_LRME_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_FD,
+		.port_name = "FD",
 		.enable = false,
 	},
 	{
 		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
 		.enable = true,
 		.flag_out_set0_low = {
 			.enable = true,

drivers/cam_cpas/cpas_top/cpastop_v175_130.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019, 2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CPASTOP_V175_130_H_
@@ -203,6 +203,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v175_130_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -248,6 +249,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE0123_RDI_WRITE,
+		.port_name = "IFE0123_RDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -296,9 +298,17 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x3620, /* IFE0123_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE0_NRDI_WRITE,
+		.port_name = "IFE0_NRDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -349,10 +359,18 @@ static struct cam_camnoc_specific
 			.offset = 0x3B88, /* SPECIFIC_IFE0_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x3A20, /* IFE0_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		/* IFE0/1 RDI READ PATH */
 		.port_type = CAM_CAMNOC_IFE01_RDI_READ,
+		.port_name = "IFE01_RDI_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -402,6 +420,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE1_NRDI_WRITE,
+		.port_name = "IFE1_NRDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -453,9 +472,17 @@ static struct cam_camnoc_specific
 			.offset = 0x5588, /* SPECIFIC_IFE1_WR_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5420, /* IFE1_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_LRME_READ,
+		.port_name = "IPE_BPS_LRME_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -511,6 +538,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_LRME_WRITE,
+		.port_name = "IPE_BPS_LRME_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -563,9 +591,17 @@ static struct cam_camnoc_specific
 			.offset = 0x2B88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
 			.value = 0,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2A20, /* IBL_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_VID_DISP_WRITE,
+		.port_name = "IPE_VID_DISP_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -623,10 +659,18 @@ static struct cam_camnoc_specific
 			.offset = 0x5F88, /* SPECIFIC_IBL_WR_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5E20, /* IPE_VID_DISP_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 
 	{
 		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -666,9 +710,17 @@ static struct cam_camnoc_specific
 		.ubwc_ctl = {
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2620, /* JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_FD,
+		.port_name = "FD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -708,11 +760,18 @@ static struct cam_camnoc_specific
 		.ubwc_ctl = {
 			.enable = false,
 		},
-
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x3E20, /* FD_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		/*SidebandManager_main_SidebandManager_FlagOutSet0_Low*/
 		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
 		.enable = true,
 		.flag_out_set0_low = {
 			.enable = true,

drivers/cam_cpas/cpas_top/cpastop_v480_100.h

@@ -199,6 +199,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v480_100_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -241,6 +242,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_FD,
+		.port_name = "FD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -280,9 +282,17 @@ static struct cam_camnoc_specific
 		.ubwc_ctl = {
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x620, /* FD_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_LINEAR,
+		.port_name = "IFE_LINEAR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -325,9 +335,17 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0xA20, /* IFE_LINEAR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_RD,
+		.port_name = "IFE_RDI_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -373,6 +391,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_WR,
+		.port_name = "IFE_RDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -415,9 +434,17 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x1420, /* IFE_RDI_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
+		.port_name = "IFE_UBWC_STATS",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -464,9 +491,17 @@ static struct cam_camnoc_specific
 			.offset = 0x1B88, /* IFE_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x1A20, /* IFE_UBWC_STATS_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE0_RD,
+		.port_name = "IPE0_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -518,6 +553,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE1_BPS_RD,
+		.port_name = "IPE1_BPS_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -569,6 +605,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_WR,
+		.port_name = "IPE_BPS_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -617,9 +654,17 @@ static struct cam_camnoc_specific
 			.offset = 0x2988, /* IPE_BPS_WR_ENCCTL_LOW */
 			.value = 1,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2820, /* IPE_BPS_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -659,9 +704,17 @@ static struct cam_camnoc_specific
 		.ubwc_ctl = {
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2E20, /* JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
 		.enable = true,
 		.flag_out_set0_low = {
 			.enable = false,

drivers/cam_cpas/cpas_top/cpastop_v520_100.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CPASTOP_V520_100_H_
@@ -81,6 +81,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v520_100_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -123,6 +124,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_TFE,
+		.port_name = "TFE",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -167,9 +169,17 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x20, /* TFE_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_OPE,
+		.port_name = "OPE",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -211,6 +221,13 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x420, /* OPE_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 };
 

drivers/cam_cpas/cpas_top/cpastop_v540_100.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CPASTOP_V540_100_H_
@@ -82,6 +82,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v540_100_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -124,6 +125,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_TFE,
+		.port_name = "TFE",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -168,9 +170,17 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x20, /* TFE_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_OPE,
+		.port_name = "OPE",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -212,6 +222,13 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x420, /* OPE_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 };
 

drivers/cam_cpas/cpas_top/cpastop_v545_100.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CPASTOP_V545_100_H_
@@ -81,6 +81,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v545_100_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -123,6 +124,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_TFE,
+		.port_name = "TFE",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -167,9 +169,17 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x20, /* TFE_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_TFE_1,
+		.port_name = "TFE_1",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -206,9 +216,17 @@ static struct cam_camnoc_specific
 			.offset = 0x4048, /* TFE_SAFELUT_LOW */
 			.value = 0x00000003,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x4020, /* TFE_1_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_TFE_2,
+		.port_name = "TFE_2",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -245,9 +263,17 @@ static struct cam_camnoc_specific
 			.offset = 0x5048, /* TFE_SAFELUT_LOW */
 			.value = 0x00000003,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5020, /* TFE_2_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_OPE,
+		.port_name = "OPE",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -289,6 +315,13 @@ static struct cam_camnoc_specific
 			 */
 			.enable = false,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x420, /* OPE_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 };
 

drivers/cam_cpas/cpas_top/cpastop_v570_200.h

@@ -201,6 +201,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v570_200_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -264,6 +265,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_LINEAR,
+		.port_name = "IFE_LINEAR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -327,9 +329,17 @@ static struct cam_camnoc_specific
 			.offset = 0xE24, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0xA20, /* IFE_LINEAR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_RD,
+		.port_name = "IFE_RDI_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -396,6 +406,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_WR,
+		.port_name = "IFE_RDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -459,9 +470,17 @@ static struct cam_camnoc_specific
 			.offset = 0x1824, /* IFE_RDI_WR_0_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x1420, /* IFE_RDI_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
+		.port_name = "IFE_UBWC_STATS",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -532,9 +551,17 @@ static struct cam_camnoc_specific
 			/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x1A20, /* IFE_UBWC_STATS_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE0_RD,
+		.port_name = "IPE0_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -607,6 +634,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE1_BPS_RD,
+		.port_name = "IPE1_BPS_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -679,6 +707,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_WR,
+		.port_name = "IPE_BPS_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -748,9 +777,17 @@ static struct cam_camnoc_specific
 			.offset = 0x2C24, /* IPE_BPS_WR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2820, /* IFE_IPE_BPS_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -811,9 +848,17 @@ static struct cam_camnoc_specific
 			.offset = 0x2D24, /* JPEG_QOSGEN_SHAPING_HIGH */
 			.value = 0xA0A0A0A,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2E20, /* IFE_JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
 		.enable = true,
 		.flag_out_set0_low = {
 			.enable = false,

drivers/cam_cpas/cpas_top/cpastop_v580_100.h

@@ -224,6 +224,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v580_100_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -287,6 +288,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_LINEAR,
+		.port_name = "IFE_LINEAR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -350,9 +352,17 @@ static struct cam_camnoc_specific
 			.offset = 0xE24, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0xA20, /* IFE_LINEAR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_RD,
+		.port_name = "IFE_RDI_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -419,6 +429,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_WR,
+		.port_name = "IFE_RDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -482,9 +493,17 @@ static struct cam_camnoc_specific
 			.offset = 0x1824, /* IFE_RDI_WR_0_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x1420, /* IFE_RDI_WR_0_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_WR_1,
+		.port_name = "IFE_RDI_WR_1",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -548,9 +567,17 @@ static struct cam_camnoc_specific
 			.offset = 0x7C24, /* IFE_RDI_WR_1_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x7420, /* IFE_RDI_WR_1_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_UBWC_STATS,
+		.port_name = "IFE_UBWC_STATS",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -621,9 +648,17 @@ static struct cam_camnoc_specific
 			/* IFE_UBWC_STATS_0_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x1A20, /* IFE_UBWC_STATS_0_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_UBWC_STATS_1,
+		.port_name = "IFE_UBWC_STATS_1",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -694,9 +729,17 @@ static struct cam_camnoc_specific
 			/* IFE_UBWC_STATS_1_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x7620, /* IFE_UBWC_STATS_1_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE0_RD,
+		.port_name = "IPE0_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -769,6 +812,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE1_BPS_RD,
+		.port_name = "IPE1_BPS_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -841,6 +885,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_BPS_WR,
+		.port_name = "IPE_BPS_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -910,9 +955,17 @@ static struct cam_camnoc_specific
 			.offset = 0x2C24, /* IPE_BPS_WR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2820, /* IFE_IPE_BPS_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -973,9 +1026,17 @@ static struct cam_camnoc_specific
 			.offset = 0x2D24, /* JPEG_QOSGEN_SHAPING_HIGH */
 			.value = 0x10101010,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x2E20, /* IFE_JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
 		.enable = true,
 		.flag_out_set0_low = {
 			.enable = false,

drivers/cam_cpas/cpas_top/cpastop_v680_100.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CPASTOP_V680_100_H_
@@ -221,6 +221,7 @@ static struct cam_camnoc_specific
 	cam_cpas_v680_100_camnoc_specific[] = {
 	{
 		.port_type = CAM_CAMNOC_IFE_UBWC,
+		.port_name = "IFE_UBWC",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -286,9 +287,17 @@ static struct cam_camnoc_specific
 			.offset = 0x5A24, /* IFE_UBWC_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5820, /* IFE_UBWC_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_RDI_WR,
+		.port_name = "IFE_RDI_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -354,9 +363,17 @@ static struct cam_camnoc_specific
 			.offset = 0x5424, /* IFE_RDI_WR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x5220, /* IFE_RDI_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_PDAF,
+		.port_name = "IFE_PDAF",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -422,9 +439,17 @@ static struct cam_camnoc_specific
 			.offset = 0x4e24, /* IFE_PDAF_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x4C20, /* IFE_PDAF_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_LINEAR_STATS,
+		.port_name = "IFE_LINEAR_STATS",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -490,9 +515,17 @@ static struct cam_camnoc_specific
 			.offset = 0x4224, /* IFE_LINEAR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x4020, /* IFE_LINEAR_STATS_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_LINEAR_STATS_1,
+		.port_name = "IFE_LINEAR_STATS_1",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -558,9 +591,17 @@ static struct cam_camnoc_specific
 			.offset = 0x8424, /* IFE_LINEAR_1_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x8220, /* IFE_LINEAR_STATS_1_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IFE_LITE,
+		.port_name = "IFE_LITE",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -626,9 +667,17 @@ static struct cam_camnoc_specific
 			.offset = 0x4824, /* IFE_LITE_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = true,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x4620, /* IFE_LITE_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_SFE_RD,
+		.port_name = "SFE_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -697,6 +746,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE_WR,
+		.port_name = "IPE_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -757,9 +807,17 @@ static struct cam_camnoc_specific
 			.offset = 0x6c24, /* IPE_WR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x6A20, /* IPE_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_BPS_WR,
+		.port_name = "BPS_WR",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -820,9 +878,17 @@ static struct cam_camnoc_specific
 			.offset = 0x824, /* BPS_WR_QOSGEN_SHAPING_HIGH */
 			.value = 0x0,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x620, /* BPS_WR_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_BPS_RD,
+		.port_name = "BPS_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -886,6 +952,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_JPEG,
+		.port_name = "JPEG",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = true,
@@ -946,9 +1013,17 @@ static struct cam_camnoc_specific
 			.offset = 0x7e24, /* JPEG_QOSGEN_SHAPING_HIGH */
 			.value = 0x10101010,
 		},
+		.maxwr_low = {
+			.enable = false,
+			.access_type = CAM_REG_TYPE_READ,
+			.masked_value = 0,
+			.offset = 0x7C20, /* JPEG_MAXWR_LOW */
+			.value = 0x0,
+		},
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE0_RD,
+		.port_name = "IPE0_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -1016,6 +1091,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_IPE1_RD,
+		.port_name = "IPE1_RD",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -1079,6 +1155,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_CDM,
+		.port_name = "CDM",
 		.enable = true,
 		.priority_lut_low = {
 			.enable = false,
@@ -1142,6 +1219,7 @@ static struct cam_camnoc_specific
 	},
 	{
 		.port_type = CAM_CAMNOC_ICP,
+		.port_name = "ICP",
 		.enable = true,
 		.flag_out_set0_low = {
 			.enable = false,

drivers/cam_cpas/include/cam_cpas_api.h

@@ -767,4 +767,16 @@ int cam_cpas_activate_llcc(enum cam_sys_cache_config_types type);
  */
 int cam_cpas_deactivate_llcc(enum cam_sys_cache_config_types type);
 
+/**
+ * cam_cpas_dump_camnoc_buff_fill_info()
+ *
+ * @brief: API to dump camnoc buffer fill level info
+ *
+ * @client_handle : Client cpas handle
+ *
+ * @return 0 on success
+ *
+ */
+int cam_cpas_dump_camnoc_buff_fill_info(uint32_t client_handle);
+
 #endif /* _CAM_CPAS_API_H_ */

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe680.h

@@ -384,41 +384,6 @@ static struct cam_vfe_top_ver4_wr_client_desc vfe680_wr_client_desc[] = {
 	},
 };
 
-static struct cam_vfe_top_camnoc_reg_data vfe680_camnoc_reg_data[] = {
-	{
-		.desc = "linear_stats",
-		.offset = 0x4020,
-	},
-	{
-		.desc = "lite",
-		.offset = 0x4620,
-	},
-	{
-		.desc = "pdaf",
-		.offset = 0x4c20,
-	},
-	{
-		.desc = "rdi",
-		.offset = 0x5220,
-	},
-	{
-		.desc = "ubwc",
-		.offset = 0x5820,
-	},
-	{
-		.desc = "linear_stats_1",
-		.offset = 0x8220,
-	},
-};
-
-struct cam_vfe_top_camnoc_debug_data vfe680_camnoc_debug_data = {
-	.pending_mask      = 0x7f0000,
-	.pending_shift     = 16,
-	.queued_mask       = 0x7ff,
-	.num_reg           = 6,
-	.camnoc_reg        = vfe680_camnoc_reg_data,
-};
-
 static struct cam_irq_register_set vfe680_top_irq_reg_set[3] = {
 	{
 		.mask_reg_offset   = 0x00000034,
@@ -571,7 +536,6 @@ static struct cam_vfe_top_ver4_hw_info vfe680_top_hw_info = {
 	.rdi_hw_info[2] = &vfe680_rdi_hw_info_arr[2],
 	.wr_client_desc         = vfe680_wr_client_desc,
 	.module_desc            = vfe680_pp_mod_desc,
-	.camnoc_debug_data      = &vfe680_camnoc_debug_data,
 	.num_mux = 5,
 	.mux_type = {
 		CAM_VFE_CAMIF_VER_4_0,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe17x/cam_vfe_lite68x.h

@@ -54,41 +54,6 @@ static struct cam_vfe_top_ver4_wr_client_desc vfe680x_wr_client_desc[] = {
 	},
 };
 
-static struct cam_vfe_top_camnoc_reg_data vfe680x_camnoc_reg_data[] = {
-	{
-		.desc = "linear_stats",
-		.offset = 0x4020,
-	},
-	{
-		.desc = "lite",
-		.offset = 0x4620,
-	},
-	{
-		.desc = "pdaf",
-		.offset = 0x4c20,
-	},
-	{
-		.desc = "rdi",
-		.offset = 0x5220,
-	},
-	{
-		.desc = "ubwc",
-		.offset = 0x5820,
-	},
-	{
-		.desc = "linear_stats_1",
-		.offset = 0x8220,
-	},
-};
-
-struct cam_vfe_top_camnoc_debug_data vfe680x_camnoc_debug_data = {
-	.pending_mask      = 0x7f0000,
-	.pending_shift     = 16,
-	.queued_mask       = 0x7ff,
-	.num_reg           = 6,
-	.camnoc_reg        = vfe680x_camnoc_reg_data,
-};
-
 static struct cam_irq_register_set vfe68x_top_irq_reg_set[3] = {
 	{
 		.mask_reg_offset   = 0x00001024,
@@ -207,7 +172,6 @@ static struct cam_vfe_top_ver4_hw_info vfe68x_top_hw_info = {
 	},
 	.module_desc            = vfe68x_pp_mod_desc,
 	.wr_client_desc         = vfe680x_wr_client_desc,
-	.camnoc_debug_data      = &vfe680x_camnoc_debug_data,
 	.num_mux = 5,
 	.mux_type = {
 		CAM_VFE_CAMIF_VER_4_0,

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver3.c

@@ -945,23 +945,12 @@ static void cam_vfe_camif_ver3_print_status(uint32_t *status,
 	uint32_t violation_mask = 0x3F, module_id = 0;
 	uint32_t bus_overflow_status = 0, status_0 = 0, status_2 = 0;
 	struct cam_vfe_soc_private *soc_private;
-	uint32_t val0, val1, val2, val3, val4;
-	uint32_t camera_hw_version;
-	int rc = 0;
-
-	val3 = val4 = 0;
 
 	if (!status) {
 		CAM_ERR(CAM_ISP, "Invalid params");
 		return;
 	}
 
-	rc = cam_cpas_get_cpas_hw_version(&camera_hw_version);
-	if (rc) {
-		CAM_ERR(CAM_ISP, "Failed to get HW version rc:%d", rc);
-		return;
-	}
-
 	bus_overflow_status = status[CAM_IFE_IRQ_BUS_OVERFLOW_STATUS];
 	status_0 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS0];
 	status_2 = status[CAM_IFE_IRQ_CAMIF_REG_STATUS2];
@@ -1275,27 +1264,7 @@ static void cam_vfe_camif_ver3_print_status(uint32_t *status,
 print_state:
 	soc_private = camif_priv->soc_info->soc_private;
 
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0xA20, true, &val0);
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x1420, true, &val1);
-	cam_cpas_reg_read(soc_private->cpas_handle,
-		CAM_CPAS_REG_CAMNOC, 0x1A20, true, &val2);
-
-	if (camera_hw_version == CAM_CPAS_TITAN_580_V100) {
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC, 0x7620, true, &val3);
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC, 0x7420, true, &val4);
-	}
-
-	CAM_INFO(CAM_ISP,
-		"CAMNOC REG[Queued Pending] linear[%d %d] rdi0_wr[%d %d] ubwc_stats0[%d %d] ubwc_stats1[%d %d] rdi1_wr[%d %d]",
-		(val0 & 0x7FF), (val0 & 0x7F0000) >> 16,
-		(val1 & 0x7FF), (val1 & 0x7F0000) >> 16,
-		(val2 & 0x7FF), (val2 & 0x7F0000) >> 16,
-		(val3 & 0x7FF), (val3 & 0x7F0000) >> 16,
-		(val4 & 0x7FF), (val4 & 0x7F0000) >> 16);
+	cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
 
 	CAM_INFO(CAM_ISP, "ife_clk_src:%lld", soc_private->ife_clk_src);
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_common.h

@@ -31,20 +31,6 @@ struct cam_vfe_top_priv_common {
 	enum cam_vfe_bw_control_action  axi_vote_control[CAM_VFE_TOP_MUX_MAX];
 };
 
-
-struct cam_vfe_top_camnoc_reg_data {
-	uint8_t                              *desc;
-	uint32_t                              offset;
-};
-
-struct cam_vfe_top_camnoc_debug_data {
-	uint32_t                               pending_mask;
-	uint32_t                               pending_shift;
-	uint32_t                               queued_mask;
-	uint32_t                               num_reg;
-	struct cam_vfe_top_camnoc_reg_data    *camnoc_reg;
-};
-
 struct cam_vfe_top_reg_dump_entry {
 	uint32_t reg_dump_start;
 	uint32_t reg_dump_end;

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.c

@@ -995,51 +995,23 @@ int cam_vfe_top_ver4_dump_timestamps(
 	return 0;
 }
 
-static void cam_vfe_top_ver4_print_camnoc_debug_info(
-	struct cam_vfe_top_ver4_priv *top_priv)
-{
-	struct cam_vfe_top_camnoc_debug_data *camnoc_debug = NULL;
-	struct cam_vfe_soc_private           *soc_private = NULL;
-	uint32_t                              i;
-	uint32_t                              val = 0;
-
-	camnoc_debug = top_priv->common_data.hw_info->camnoc_debug_data;
-
-	if (!camnoc_debug || !camnoc_debug->camnoc_reg) {
-		CAM_DBG(CAM_ISP, "No CAMNOC Info");
-		return;
-	}
-
-	soc_private = top_priv->common_data.soc_info->soc_private;
-
-	for (i = 0; i < camnoc_debug->num_reg; i++) {
-		cam_cpas_reg_read(soc_private->cpas_handle,
-			CAM_CPAS_REG_CAMNOC,
-			camnoc_debug->camnoc_reg[i].offset,
-			true, &val);
-		CAM_ERR(CAM_ISP, "CAMNOC Fill level: %s  pending %u queued %u",
-			camnoc_debug->camnoc_reg[i].desc,
-			((val & camnoc_debug->pending_mask) >>
-				camnoc_debug->pending_shift),
-			val & camnoc_debug->queued_mask);
-	}
-}
-
 static int cam_vfe_top_ver4_print_overflow_debug_info(
 	struct cam_vfe_top_ver4_priv *top_priv, void *cmd_args)
 {
 	struct cam_vfe_top_ver4_common_data *common_data;
 	struct cam_hw_soc_info              *soc_info;
-	uint32_t                             status = 0;
+	struct cam_vfe_soc_private *soc_private = NULL;
+	uint32_t                             status = 0, bus_overflow_status = 0;
 	uint32_t                             i = 0;
 	int                                  res_id;
 
 	common_data = &top_priv->common_data;
 	soc_info = common_data->soc_info;
+	soc_private = soc_info->soc_private;
 
 	status  = cam_io_r(soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base +
 		    common_data->common_reg->bus_overflow_status);
-
+	bus_overflow_status = status;
 	res_id = *((int *)(cmd_args));
 	CAM_ERR_RATE_LIMIT(CAM_ISP, "VFE[%d] src_clk_rate:%luHz res: %u overflow_status 0x%x",
 		soc_info->index, soc_info->applied_src_clk_rate,
@@ -1054,7 +1026,9 @@ static int cam_vfe_top_ver4_print_overflow_debug_info(
 	}
 
 	cam_vfe_top_ver4_dump_timestamps(top_priv, res_id);
-	cam_vfe_top_ver4_print_camnoc_debug_info(top_priv);
+	cam_cpas_dump_camnoc_buff_fill_info(soc_private->cpas_handle);
+	if (bus_overflow_status)
+		cam_cpas_log_votes();
 
 	status  = cam_io_r(soc_info->reg_map[VFE_CORE_BASE_IDX].mem_base +
 		    common_data->common_reg->bus_violation_status);
@@ -1711,6 +1685,8 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 				payload->ts.mono_time.tv_nsec;
 		}
 
+		cam_cpas_notify_event("IFE SOF", evt_info.hw_idx);
+
 		if (vfe_priv->event_cb)
 			vfe_priv->event_cb(vfe_priv->priv,
 				CAM_ISP_HW_EVENT_SOF, (void *)&evt_info);
@@ -1726,6 +1702,8 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 		vfe_priv->epoch_ts.tv_nsec =
 			payload->ts.mono_time.tv_nsec;
 
+		cam_cpas_notify_event("IFE EPOCH", evt_info.hw_idx);
+
 		if (vfe_priv->event_cb)
 			vfe_priv->event_cb(vfe_priv->priv,
 				CAM_ISP_HW_EVENT_EPOCH, (void *)&evt_info);
@@ -1740,6 +1718,8 @@ static int cam_vfe_handle_irq_bottom_half(void *handler_priv,
 		vfe_priv->eof_ts.tv_nsec =
 			payload->ts.mono_time.tv_nsec;
 
+		cam_cpas_notify_event("IFE EOF", evt_info.hw_idx);
+
 		if (vfe_priv->event_cb)
 			vfe_priv->event_cb(vfe_priv->priv,
 				CAM_ISP_HW_EVENT_EOF, (void *)&evt_info);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver4.h

@@ -96,7 +96,6 @@ struct cam_vfe_top_ver4_hw_info {
 	struct cam_vfe_ver4_path_reg_data          *reg_data;
 	struct cam_vfe_top_ver4_wr_client_desc     *wr_client_desc;
 	struct cam_vfe_top_ver4_module_desc        *module_desc;
-	struct cam_vfe_top_camnoc_debug_data       *camnoc_debug_data;
 	uint32_t                                    num_reg;
 	uint32_t                                    num_mux;
 	uint32_t                                    num_path_port_map;