Revert "qcacmn: limit tx completion process count to napi quota"

This reverts Change-Id:	Ic24f131c90b90b0e118edffcab559ddf31779dcf

Change-Id: Ia683184f346ee13ad970679bef8bab211a84503d
CRs-Fixed: 3421368
This commit is contained in:
Kai Liu
2023-04-25 02:55:17 -07:00
committed by Madan Koyyalamudi
parent 2467d81f7b
commit 6f3d208ec8
2 changed files with 5 additions and 11 deletions

View File

@@ -5785,7 +5785,6 @@ uint32_t dp_tx_comp_handler(struct dp_intr *int_ctx, struct dp_soc *soc,
struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id]; struct dp_srng *tx_comp_ring = &soc->tx_comp_ring[ring_id];
int max_reap_limit, ring_near_full; int max_reap_limit, ring_near_full;
uint32_t num_entries; uint32_t num_entries;
uint32_t rquota = quota;
DP_HIST_INIT(); DP_HIST_INIT();
@@ -5812,8 +5811,8 @@ more_data:
num_avail_for_reap = hal_srng_dst_num_valid(hal_soc, num_avail_for_reap = hal_srng_dst_num_valid(hal_soc,
hal_ring_hdl, 0); hal_ring_hdl, 0);
if (num_avail_for_reap >= rquota) if (num_avail_for_reap >= quota)
num_avail_for_reap = rquota; num_avail_for_reap = quota;
dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap); dp_srng_dst_inv_cached_descs(soc, hal_ring_hdl, num_avail_for_reap);
last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc, last_prefetched_hw_desc = dp_srng_dst_prefetch_32_byte_desc(hal_soc,
@@ -6001,10 +6000,8 @@ next_desc:
* *
* One more loop will move the state to normal processing and yield * One more loop will move the state to normal processing and yield
*/ */
if (ring_near_full && rquota) { if (ring_near_full)
rquota -= num_processed;
goto more_data; goto more_data;
}
if (dp_tx_comp_enable_eol_data_check(soc)) { if (dp_tx_comp_enable_eol_data_check(soc)) {
@@ -6016,10 +6013,8 @@ next_desc:
hal_ring_hdl)) { hal_ring_hdl)) {
DP_STATS_INC(soc, tx.hp_oos2, 1); DP_STATS_INC(soc, tx.hp_oos2, 1);
if (!hif_exec_should_yield(soc->hif_handle, if (!hif_exec_should_yield(soc->hif_handle,
int_ctx->dp_intr_id)) { int_ctx->dp_intr_id))
rquota -= num_processed;
goto more_data; goto more_data;
}
num_avail_for_reap = num_avail_for_reap =
hal_srng_dst_num_valid_locked(soc->hal_soc, hal_srng_dst_num_valid_locked(soc->hal_soc,
@@ -6029,7 +6024,6 @@ next_desc:
(num_avail_for_reap >= (num_avail_for_reap >=
num_entries >> 1))) { num_entries >> 1))) {
DP_STATS_INC(soc, tx.near_full, 1); DP_STATS_INC(soc, tx.near_full, 1);
rquota -= num_processed;
goto more_data; goto more_data;
} }
} }

View File

@@ -41,7 +41,7 @@
* This mask defines how many transmit frames account for 1 NAPI work unit * This mask defines how many transmit frames account for 1 NAPI work unit
* 0 means each tx completion is 1 unit * 0 means each tx completion is 1 unit
*/ */
#define DP_TX_NAPI_BUDGET_DIV_MASK 0xffff #define DP_TX_NAPI_BUDGET_DIV_MASK 0
/* PPDU Stats Configuration - Configure bitmask for enabling tx ppdu tlv's */ /* PPDU Stats Configuration - Configure bitmask for enabling tx ppdu tlv's */
#define DP_PPDU_TXLITE_STATS_BITMASK_CFG 0x3FFF #define DP_PPDU_TXLITE_STATS_BITMASK_CFG 0x3FFF