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disp: msm: dp: update mode validation logic for widebus

Update the mode validation logic by halving the mode clock
when widebus is enabled.

Change-Id: I8f060d8b60403aa5020496983bec0b3e2878b08b
Signed-off-by: Tatenda Chipeperekwa <[email protected]>
Tatenda Chipeperekwa 5 years ago
parent
commit
6f0828d9a7
1 changed files with 7 additions and 2 deletions
  1. 7 2
      msm/dp/dp_display.c

+ 7 - 2
msm/dp/dp_display.c

@@ -2059,6 +2059,7 @@ static enum drm_mode_status dp_display_validate_mode(
 	bool dsc_en;
 	bool dsc_en;
 	u32 num_lm = 0;
 	u32 num_lm = 0;
 	int rc = 0;
 	int rc = 0;
+	u32 pclk_khz = 0;
 
 
 	if (!dp_display || !mode || !panel ||
 	if (!dp_display || !mode || !panel ||
 			!avail_res || !avail_res->max_mixer_width) {
 			!avail_res || !avail_res->max_mixer_width) {
@@ -2099,8 +2100,12 @@ static enum drm_mode_status dp_display_validate_mode(
 		goto end;
 		goto end;
 	}
 	}
 
 
-	if (mode->clock > dp_display->max_pclk_khz) {
-		DP_MST_DEBUG("clk:%d, max:%d\n", mode->clock,
+	pclk_khz = dp_mode.timing.widebus_en ?
+		(dp_mode.timing.pixel_clk_khz >> 1) :
+		(dp_mode.timing.pixel_clk_khz);
+
+	if (pclk_khz > dp_display->max_pclk_khz) {
+		DP_MST_DEBUG("clk:%d, max:%d\n", pclk_khz,
 				dp_display->max_pclk_khz);
 				dp_display->max_pclk_khz);
 		goto end;
 		goto end;
 	}
 	}