cam: tfe: Correct master select and halt mode

Correct master select and halt mode for single TFE in
IPP and PPP path.

CRs-Fixed: 3478317
Change-Id: I4697bb54b106b2459049d884303234315fd48fa7
Signed-off-by: Alok Chauhan <quic_alokc@quicinc.com>

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid770.h

@@ -51,7 +51,7 @@ static struct cam_tfe_csid_pxl_reg_offset  cam_tfe_csid_770_ipp_reg_offset = {
 	.early_eof_en_shift_val              = 29,
 	.halt_master_sel_shift               = 4,
 	.halt_mode_shift                     = 2,
-	.halt_master_sel_master_val          = 3,
+	.halt_master_sel_master_val          = 1,
 	.halt_master_sel_slave_val           = 0,
 	.binning_supported                   = 3,
 	.bin_qcfa_en_shift_val               = 30,
@@ -104,7 +104,7 @@ static struct cam_tfe_csid_pxl_reg_offset  cam_tfe_csid_770_ppp_reg_offset = {
 	.halt_master_sel_shift               = 4,
 	.halt_mode_shift                     = 2,
 	.halt_master_sel_master_val          = 3,
-	.halt_master_sel_slave_val           = 0,
+	.halt_master_sel_slave_val           = 2,
 	.binning_supported                   = 0,
 	.bin_qcfa_en_shift_val               = 30,
 	.bin_en_shift_val                    = 2,
@@ -273,7 +273,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset
 	.csid_csi2_rx_stats_ecc_addr                  = 0x164,
 	.csid_csi2_rx_total_crc_err_addr              = 0x168,
 
-	.phy_tpg_base_id                              = 0,
+	.phy_tpg_base_id                              = 3,
 	.csi2_rst_srb_all                             = 0x3FFF,
 	.csi2_rst_done_shift_val                      = 27,
 	.csi2_irq_mask_all                            = 0xFFFFFFF,
@@ -290,6 +290,7 @@ static struct cam_tfe_csid_csi2_rx_reg_offset
 	.csi2_rx_long_pkt_hdr_rst_stb_shift           = 0x1,
 	.csi2_rx_short_pkt_hdr_rst_stb_shift          = 0x2,
 	.csi2_rx_cphy_pkt_hdr_rst_stb_shift           = 0x3,
+	.need_to_sel_tpg_mux                          = true,
 };
 
 static struct cam_tfe_csid_common_reg_offset

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c

@@ -1652,7 +1652,7 @@ static int cam_tfe_csid_enable_pxl_path(
 		val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift);
 	else
 		/* Default is internal halt mode */
-		val = 0;
+		val = 1 << pxl_reg->halt_master_sel_shift;
 
 	/*
 	 * Resume at frame boundary if Master or No Sync.
@@ -1866,7 +1866,17 @@ static int cam_tfe_csid_enable_ppp_path(
 			ppp_reg->halt_master_sel_shift);
 	else
 		/* Default is internal halt mode */
-		val = 0;
+		val = (TFE_CSID_HALT_MODE_SLAVE  << ppp_reg->halt_mode_shift) |
+			(ppp_reg->halt_master_sel_master_val <<
+			ppp_reg->halt_master_sel_shift);
+
+	/*
+	 * Resume at frame boundary if Master or No Sync.
+	 * Slave will get resume command from Master.
+	 */
+	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER ||
+		path_data->sync_mode == CAM_ISP_HW_SYNC_NONE)
+		val |= CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY;
 
 	cam_io_w_mb(val, soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr);