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@@ -78,6 +78,7 @@ do { \
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#define HAL_TX_TID_BITS_MASK ((1 << HAL_TX_BITS_PER_TID) - 1)
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#define HAL_TX_NUM_DSCP_PER_REGISTER 10
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#define HAL_MAX_HW_DSCP_TID_MAPS 2
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+#define HAL_MAX_HW_DSCP_TID_MAPS_11AX 32
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#define HTT_META_HEADER_LEN_BYTES 64
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#define HAL_TX_EXT_DESC_WITH_META_DATA \
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@@ -459,6 +460,7 @@ static inline void hal_tx_desc_set_to_fw(void *desc, uint8_t to_fw)
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*
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* Return: void
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*/
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+#if !defined(QCA_WIFI_QCA6290_11AX)
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static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc,
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uint8_t id)
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{
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@@ -467,6 +469,16 @@ static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc,
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HAL_TX_SM(TCL_DATA_CMD_3,
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DSCP_TO_TID_PRIORITY_TABLE_ID, id);
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}
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+#else
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+static inline void hal_tx_desc_set_dscp_tid_table_id(void *desc,
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+ uint8_t id)
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+{
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+ HAL_SET_FLD(desc, TCL_DATA_CMD_5,
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+ DSCP_TID_TABLE_NUM) |=
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+ HAL_TX_SM(TCL_DATA_CMD_5,
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+ DSCP_TID_TABLE_NUM, id);
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+}
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+#endif
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/**
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* hal_tx_desc_set_mesh_en - Set mesh_enable flag in Tx descriptor
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@@ -968,6 +980,7 @@ static inline void hal_tx_comp_get_htt_desc(void *hw_desc, uint8_t *htt_desc)
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qdf_mem_copy(htt_desc, desc, HAL_TX_COMP_HTT_STATUS_LEN);
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}
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+#if !defined(QCA_WIFI_QCA6290_11AX)
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/**
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* hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
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* @soc: HAL SoC context
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@@ -1061,6 +1074,76 @@ static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid,
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HAL_REG_WRITE(soc, addr,
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(regval & HWIO_TCL_R0_DSCP_TID1_MAP_1_RMSK));
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}
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+#else
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+/**
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+ * hal_tx_set_dscp_tid_map_default() - Configure default DSCP to TID map table
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+ * @soc: HAL SoC context
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+ * @map: DSCP-TID mapping table
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+ * @id: mapping table ID - 0-31
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+ *
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+ * DSCP are mapped to 8 TID values using TID values programmed
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+ * in any of the 32 DSCP_TID_MAPS (id = 0-31).
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+ *
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+ * Return: none
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+ */
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+static inline void hal_tx_set_dscp_tid_map(void *hal_soc, uint8_t *map,
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+ uint8_t id)
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+{
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+ int i;
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+ uint32_t addr;
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+ uint32_t value;
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+
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+ struct hal_soc *soc = (struct hal_soc *)hal_soc;
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+
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+ if (id >= HAL_MAX_HW_DSCP_TID_MAPS_11AX) {
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+ return;
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+ }
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+
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+ addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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+ SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id);
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+
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+ for (i = 0; i < 64; i += 10) {
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+ value = (map[i] |
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+ (map[i+1] << 0x3) |
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+ (map[i+2] << 0x6) |
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+ (map[i+3] << 0x9) |
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+ (map[i+4] << 0xc) |
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+ (map[i+5] << 0xf) |
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+ (map[i+6] << 0x12) |
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+ (map[i+7] << 0x15) |
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+ (map[i+8] << 0x18) |
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+ (map[i+9] << 0x1b));
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+
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+ HAL_REG_WRITE(soc, addr,
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+ (value & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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+
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+ addr += 4;
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+ }
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+}
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+static inline void hal_tx_update_dscp_tid(void *hal_soc, uint8_t tid,
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+ uint8_t id, uint8_t dscp)
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+{
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+ int index;
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+ uint32_t addr;
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+ uint32_t value;
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+ uint32_t regval;
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+
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+ struct hal_soc *soc = (struct hal_soc *)hal_soc;
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+ addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(
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+ SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET, id);
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+
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+ index = dscp % HAL_TX_NUM_DSCP_PER_REGISTER;
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+ addr += 4 * (dscp/HAL_TX_NUM_DSCP_PER_REGISTER);
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+ value = tid << (HAL_TX_BITS_PER_TID * index);
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+
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+ regval = HAL_REG_READ(soc, addr);
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+ regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * index));
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+ regval |= value;
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+
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+ HAL_REG_WRITE(soc, addr,
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+ (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK));
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+}
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+#endif
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/**
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* hal_tx_init_data_ring() - Initialize all the TCL Descriptors in SRNG
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