msm: camera: cdm: Fix cdm driver for bufffer excursion

Update the cdm submit bl function to use allocated
genirq memory for genirq command instead of appending
the command to the last BL entry to prevent possibly
using the memory not mapped. Also, add some more logs
to make the debugging easier.

CRs-fixed: 3029732
Change-Id: I2fc679bef4c0f72031798a03b26f840b6b4ef746
Signed-off-by: Jigar Agrawal <[email protected]>

drivers/cam_cdm/cam_cdm_core_common.c

@@ -285,27 +285,18 @@ static int cam_cdm_stream_handle_init(void *hw_priv, bool init)
 			return rc;
 		}
 
-		if (core->arbitration !=
-			CAM_CDM_ARBITRATION_PRIORITY_BASED) {
-			rc = cam_hw_cdm_alloc_genirq_mem(
-				hw_priv);
-			if (rc) {
-				CAM_ERR(CAM_CDM,
-					"Genirqalloc failed");
-				cam_hw_cdm_deinit(hw_priv,
-					NULL, 0);
-			}
+		rc = cam_hw_cdm_alloc_genirq_mem(hw_priv);
+		if (rc) {
+			CAM_ERR(CAM_CDM, "Genirqalloc failed");
+			cam_hw_cdm_deinit(hw_priv, NULL, 0);
 		}
 	} else {
 		rc = cam_hw_cdm_deinit(hw_priv, NULL, 0);
 		if (rc)
 			CAM_ERR(CAM_CDM, "Deinit failed in streamoff");
 
-		if (core->arbitration !=
-			CAM_CDM_ARBITRATION_PRIORITY_BASED) {
-			if (cam_hw_cdm_release_genirq_mem(hw_priv))
-				CAM_ERR(CAM_CDM, "Genirq release fail");
-		}
+		if (cam_hw_cdm_release_genirq_mem(hw_priv))
+			CAM_ERR(CAM_CDM, "Genirq release fail");
 	}
 
 	return rc;
@@ -509,7 +500,7 @@ int cam_cdm_process_cmd(void *hw_priv,
 			break;
 		}
 		cam_cdm_get_client_refcount(client);
-		if ((req->data->flag == true) &&
+		if (req->data->flag &&
 			(!client->data.cam_cdm_callback)) {
 			CAM_ERR(CAM_CDM,
 				"CDM request cb without registering cb");

drivers/cam_cdm/cam_cdm_hw_core.c

@@ -28,8 +28,13 @@
 #include "cam_req_mgr_workq.h"
 #include "cam_common_util.h"
 
-#define CAM_CDM_BL_FIFO_WAIT_TIMEOUT 2000
-#define CAM_CDM_DBG_GEN_IRQ_USR_DATA 0xff
+#define CAM_CDM_BL_FIFO_WAIT_TIMEOUT         2000
+#define CAM_CDM_DBG_GEN_IRQ_USR_DATA         0xff
+#define CAM_CDM_MAX_BL_LENGTH                0x100000
+#define CAM_CDM_FIFO_LEN_REG_LEN_MASK        0xFFFFF
+#define CAM_CDM_FIFO_LEN_REG_TAG_MASK        0xFF
+#define CAM_CDM_FIFO_LEN_REG_TAG_SHIFT       24
+#define CAM_CDM_FIFO_LEN_REG_ARB_SHIFT       20
 
 static void cam_hw_cdm_work(struct work_struct *work);
 
@@ -675,8 +680,7 @@ int cam_hw_cdm_wait_for_bl_fifo(
 	bl_fifo = &core->bl_fifo[fifo_idx];
 
 	do {
-		if (cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(
-				cdm_hw, fifo_idx, &pending_bl)) {
+		if (cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw, fifo_idx, &pending_bl)) {
 			CAM_ERR(CAM_CDM, "Failed to read CDM pending BL's");
 			rc = -EIO;
 			break;
@@ -745,8 +749,9 @@ bool cam_hw_cdm_bl_write(
 	}
 	if (cam_cdm_write_hw_reg(cdm_hw,
 		cdm_core->offsets->bl_fifo_reg[fifo_idx]->bl_fifo_len,
-		((len & 0xFFFFF) | ((tag & 0xFF) << 24)) |
-		((set_arb) ? (1 << 20) : (0)))) {
+		((len & CAM_CDM_FIFO_LEN_REG_LEN_MASK) |
+			((tag & CAM_CDM_FIFO_LEN_REG_TAG_MASK) << CAM_CDM_FIFO_LEN_REG_TAG_SHIFT)) |
+			((set_arb) ? (1 << CAM_CDM_FIFO_LEN_REG_ARB_SHIFT) : (0)))) {
 		CAM_ERR(CAM_CDM, "Failed to write CDM BL len");
 		return true;
 	}
@@ -906,103 +911,16 @@ end:
 	return rc;
 }
 
-static int cam_hw_cdm_arb_submit_bl(struct cam_hw_info *cdm_hw,
-	struct cam_cdm_hw_intf_cmd_submit_bl *req, int i,
-	uint32_t fifo_idx, dma_addr_t hw_vaddr_ptr)
-{
-	struct cam_cdm_bl_request *cdm_cmd = req->data;
-	struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info;
-	uintptr_t cpu_addr;
-	struct cam_cdm_bl_cb_request_entry *node;
-	int rc = 0;
-	size_t len = 0;
-
-	node = kzalloc(sizeof(
-		struct cam_cdm_bl_cb_request_entry),
-		GFP_KERNEL);
-	if (!node)
-		return -ENOMEM;
-
-	node->request_type = CAM_HW_CDM_BL_CB_CLIENT;
-	node->client_hdl = req->handle;
-	node->cookie = req->data->cookie;
-	node->bl_tag = core->bl_fifo[fifo_idx].bl_tag -
-		1;
-	node->userdata = req->data->userdata;
-	list_add_tail(&node->entry,
-		&core->bl_fifo[fifo_idx]
-		.bl_request_list);
-	cdm_cmd->cmd[i].arbitrate = true;
-	rc = cam_mem_get_cpu_buf(
-		cdm_cmd->cmd[i].bl_addr.mem_handle,
-		&cpu_addr, &len);
-	if (rc || !cpu_addr) {
-		CAM_ERR(CAM_OPE, "get cmd buffailed %x",
-			cdm_cmd->cmd[i].bl_addr
-			.mem_handle);
-		return rc;
-	}
-	core->ops->cdm_write_genirq(
-		((uint32_t *)cpu_addr +
-		cdm_cmd->cmd[i].offset / 4 +
-		cdm_cmd->cmd[i].len / 4),
-		core->bl_fifo[fifo_idx].bl_tag - 1,
-		1, fifo_idx);
-	rc = cam_hw_cdm_bl_write(cdm_hw,
-		(uint32_t)hw_vaddr_ptr +
-		cdm_cmd->cmd[i].offset,
-		cdm_cmd->cmd[i].len + 7,
-		core->bl_fifo[fifo_idx].bl_tag - 1,
-		1, fifo_idx);
-	if (rc) {
-		CAM_ERR(CAM_CDM,
-			"CDM hw bl write failed tag=%d",
-			core->bl_fifo[fifo_idx].bl_tag -
-			1);
-			list_del_init(&node->entry);
-			kfree(node);
-			return -EIO;
-	}
-
-	if (cam_presil_mode_enabled()) {
-		CAM_DBG(CAM_PRESIL,
-			"Sending CDM arb cmd buffer:%d with iommu_hdl:%d",
-			cdm_cmd->cmd[i].bl_addr.mem_handle, core->iommu_hdl.non_secure);
-
-		rc = cam_mem_mgr_send_buffer_to_presil(core->iommu_hdl.non_secure,
-			cdm_cmd->cmd[i].bl_addr.mem_handle);
-		if (rc) {
-			CAM_ERR(CAM_PRESIL,
-				"Failed to send CDM arb cmd buffer i:%d mem_handle:%d rc:%d",
-				i, cdm_cmd->cmd[i].bl_addr.mem_handle, rc);
-			return rc;
-		}
-	}
-
-	rc = cam_hw_cdm_commit_bl_write(cdm_hw,
-		fifo_idx);
-	if (rc) {
-		CAM_ERR(CAM_CDM,
-			"CDM hw commit failed tag=%d",
-			core->bl_fifo[fifo_idx].bl_tag -
-			1);
-			list_del_init(&node->entry);
-			kfree(node);
-			return -EIO;
-	}
-
-	return 0;
-}
-
 int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 	struct cam_cdm_hw_intf_cmd_submit_bl *req,
 	struct cam_cdm_client *client)
 {
-	int i, rc;
+	unsigned int i;
+	int rc;
 	struct cam_cdm_bl_request *cdm_cmd = req->data;
 	struct cam_cdm *core = (struct cam_cdm *)cdm_hw->core_info;
 	struct cam_cdm_bl_fifo *bl_fifo = NULL;
-	uint32_t pending_bl = 0, fifo_idx = 0;
+	uint32_t fifo_idx = 0;
 	int write_count = 0;
 
 	fifo_idx = CAM_CDM_GET_BLFIFO_IDX(client->handle);
@@ -1025,7 +943,6 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 			bl_fifo->bl_depth);
 	}
 
-
 	mutex_lock(&core->bl_fifo[fifo_idx].fifo_lock);
 	mutex_lock(&client->lock);
 
@@ -1036,24 +953,13 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 		return -EAGAIN;
 	}
 
-	rc = cam_hw_cdm_bl_fifo_pending_bl_rb_in_fifo(cdm_hw,
-		fifo_idx, &pending_bl);
-
-	if (rc) {
-		CAM_ERR(CAM_CDM, "Cannot read the current BL depth");
-		mutex_unlock(&client->lock);
-		mutex_unlock(&core->bl_fifo[fifo_idx].fifo_lock);
-		return rc;
-	}
-
 	for (i = 0; i < req->data->cmd_arrary_count ; i++) {
 		dma_addr_t hw_vaddr_ptr = 0;
 		size_t len = 0;
 
-		if ((!cdm_cmd->cmd[i].len) &&
-			(cdm_cmd->cmd[i].len > 0x100000)) {
+		if ((!cdm_cmd->cmd[i].len) && (cdm_cmd->cmd[i].len > CAM_CDM_MAX_BL_LENGTH)) {
 			CAM_ERR(CAM_CDM,
-				"cmd len(%d) is invalid cnt=%d total cnt=%d",
+				"cmd len=: %d is invalid_ent: %d, num_cmd_ent: %d",
 				cdm_cmd->cmd[i].len, i,
 				req->data->cmd_arrary_count);
 			rc = -EINVAL;
@@ -1074,29 +980,32 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 				(req->data->cmd_arrary_count - i), fifo_idx);
 			if (write_count < 0) {
 				CAM_ERR(CAM_CDM,
-					"wait for bl fifo failed %d:%d",
-					i, req->data->cmd_arrary_count);
+					"wait for bl fifo failed for ent: %u", i);
 				rc = -EIO;
 				break;
 			}
 		}
 
 		if (req->data->type == CAM_CDM_BL_CMD_TYPE_MEM_HANDLE) {
-			rc = cam_mem_get_io_buf(
-				cdm_cmd->cmd[i].bl_addr.mem_handle,
+			rc = cam_mem_get_io_buf(cdm_cmd->cmd[i].bl_addr.mem_handle,
 				core->iommu_hdl.non_secure, &hw_vaddr_ptr,
 				&len, NULL);
+			if (rc) {
+				CAM_ERR(CAM_CDM,
+					"Getting a hwva from mem_hdl failed. rc: %d, cmd_ent: %u",
+					rc, i);
+				rc = -EINVAL;
+				break;
+			}
 		} else if (req->data->type == CAM_CDM_BL_CMD_TYPE_HW_IOVA) {
 			if (!cdm_cmd->cmd[i].bl_addr.hw_iova) {
-				CAM_ERR(CAM_CDM,
-					"Hw bl hw_iova is invalid %d:%d",
-					i, req->data->cmd_arrary_count);
+				CAM_ERR(CAM_CDM, "hw_iova is null for ent: %d", i);
 				rc = -EINVAL;
 				break;
 			}
+
 			rc = 0;
-			hw_vaddr_ptr =
-				(dma_addr_t)cdm_cmd->cmd[i].bl_addr.hw_iova;
+			hw_vaddr_ptr = (dma_addr_t)cdm_cmd->cmd[i].bl_addr.hw_iova;
 			len = cdm_cmd->cmd[i].len + cdm_cmd->cmd[i].offset;
 		} else {
 			CAM_ERR(CAM_CDM,
@@ -1106,11 +1015,8 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 			break;
 		}
 
-		if ((!rc) && (hw_vaddr_ptr) && (len) &&
-			(len >= cdm_cmd->cmd[i].offset)) {
-
-			if ((len - cdm_cmd->cmd[i].offset) <
-				cdm_cmd->cmd[i].len) {
+		if ((hw_vaddr_ptr) && (len) && (len >= cdm_cmd->cmd[i].offset)) {
+			if ((len - cdm_cmd->cmd[i].offset) < cdm_cmd->cmd[i].len) {
 				CAM_ERR(CAM_CDM,
 					"Not enough buffer cmd offset: %u cmd length: %u",
 					cdm_cmd->cmd[i].offset,
@@ -1119,134 +1025,99 @@ int cam_hw_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 				break;
 			}
 
-			CAM_DBG(CAM_CDM, "Got the HW VA");
-			if (core->bl_fifo[fifo_idx].bl_tag >=
-				(bl_fifo->bl_depth - 1))
-				core->bl_fifo[fifo_idx].bl_tag = 0;
-			if (core->arbitration ==
-				CAM_CDM_ARBITRATION_PRIORITY_BASED &&
-				(req->data->flag == true) &&
-				(i == (req->data->cmd_arrary_count -
-				1))) {
-				CAM_DBG(CAM_CDM,
-					"GenIRQ in same bl, will sumbit later");
-			} else {
-				rc = cam_hw_cdm_bl_write(cdm_hw,
-					((uint32_t)hw_vaddr_ptr +
-						cdm_cmd->cmd[i].offset),
-					(cdm_cmd->cmd[i].len - 1),
-					core->bl_fifo[fifo_idx].bl_tag,
-					cdm_cmd->cmd[i].arbitrate,
-					fifo_idx);
-				if (rc) {
-					CAM_ERR(CAM_CDM,
-						"Hw bl write failed %d:%d",
-						i, req->data->cmd_arrary_count);
-					rc = -EIO;
-					break;
-				}
-			}
-		} else {
-			CAM_ERR(CAM_CDM,
-				"Sanity check failed for hdl=%x len=%zu:%d",
-				cdm_cmd->cmd[i].bl_addr.mem_handle, len,
-				cdm_cmd->cmd[i].offset);
-			CAM_ERR(CAM_CDM, "Sanity check failed for %d:%d",
-				i, req->data->cmd_arrary_count);
-			rc = -EINVAL;
-			break;
-		}
+			CAM_DBG(CAM_CDM, "Got the hwva: %pK, type: %u",
+				hw_vaddr_ptr, req->data->type);
 
-		if (!rc) {
-			CAM_DBG(CAM_CDM,
-				"write BL done cnt=%d with tag=%d total_cnt=%d",
-				i, core->bl_fifo[fifo_idx].bl_tag,
-				req->data->cmd_arrary_count);
+			rc = cam_hw_cdm_bl_write(cdm_hw,
+				((uint32_t)hw_vaddr_ptr + cdm_cmd->cmd[i].offset),
+				(cdm_cmd->cmd[i].len - 1),
+				core->bl_fifo[fifo_idx].bl_tag,
+				cdm_cmd->cmd[i].arbitrate,
+				fifo_idx);
+			if (rc) {
+				CAM_ERR(CAM_CDM, "Hw bl write failed %d:%d",
+					i, req->data->cmd_arrary_count);
+				rc = -EIO;
+				break;
+			}
 
-			if (core->arbitration ==
-				CAM_CDM_ARBITRATION_PRIORITY_BASED &&
-				(req->data->flag == true) &&
-				(i == (req->data->cmd_arrary_count -
-				1))) {
-				CAM_DBG(CAM_CDM,
-					"GenIRQ in same blcommit later");
-			} else {
-				CAM_DBG(CAM_CDM, "Now commit the BL");
-				if (cam_hw_cdm_commit_bl_write(cdm_hw,
-					fifo_idx)) {
-					CAM_ERR(CAM_CDM,
-						"commit failed BL %d tag=%d",
-						i, core->bl_fifo[fifo_idx]
-						.bl_tag);
-					rc = -EIO;
-					break;
-				}
-				write_count--;
-				CAM_DBG(CAM_CDM, "commit success BL %d tag=%d",
+			if (cam_hw_cdm_commit_bl_write(cdm_hw, fifo_idx)) {
+				CAM_ERR(CAM_CDM, "Commit failed for BL: %d Tag: %u",
 					i, core->bl_fifo[fifo_idx].bl_tag);
+				rc = -EIO;
+				break;
 			}
+
+			CAM_DBG(CAM_CDM, "Commit success for BL: %d of %d, Tag: %u", (i + 1),
+				req->data->cmd_arrary_count,
+				core->bl_fifo[fifo_idx].bl_tag);
+
+			write_count--;
 			core->bl_fifo[fifo_idx].bl_tag++;
+			core->bl_fifo[fifo_idx].bl_tag %= (bl_fifo->bl_depth - 1);
 
 			if (cdm_cmd->cmd[i].enable_debug_gen_irq) {
 				if (write_count == 0) {
 					write_count =
-						cam_hw_cdm_wait_for_bl_fifo(
-						cdm_hw, 1, fifo_idx);
+						cam_hw_cdm_wait_for_bl_fifo(cdm_hw, 1, fifo_idx);
 					if (write_count < 0) {
-						CAM_ERR(CAM_CDM,
-						"wait for bl fifo failed %d:%d",
-						i, req->data->cmd_arrary_count);
+						CAM_ERR(CAM_CDM, "wait for bl fifo failed %d:%d",
+							i, req->data->cmd_arrary_count);
 						rc = -EIO;
 						break;
 					}
 				}
 
-				rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw,
-					fifo_idx);
-				if (rc == 0) {
+				rc = cam_hw_cdm_submit_debug_gen_irq(cdm_hw, fifo_idx);
+				if (!rc) {
+					CAM_DBG(CAM_CDM,
+						"Commit success for Dbg_GenIRQ_BL, Tag: %d",
+						core->bl_fifo[fifo_idx].bl_tag);
 					write_count--;
 					core->bl_fifo[fifo_idx].bl_tag++;
+					core->bl_fifo[fifo_idx].bl_tag %= (bl_fifo->bl_depth - 1);
+				} else {
+					CAM_WARN(CAM_CDM,
+						"Failed in submitting the debug gen entry. rc: %d",
+						rc);
+					continue;
 				}
-				if (core->bl_fifo[fifo_idx].bl_tag >=
-						(bl_fifo->bl_depth -
-						1))
-					core->bl_fifo[fifo_idx].bl_tag = 0;
 			}
 
-			if ((!rc) && (req->data->flag == true) &&
-				(i == (req->data->cmd_arrary_count -
-				1))) {
+			if (req->data->flag && (i == (req->data->cmd_arrary_count - 1))) {
 
 				if (write_count == 0) {
 					write_count =
-						cam_hw_cdm_wait_for_bl_fifo(
-						cdm_hw, 1, fifo_idx);
+						cam_hw_cdm_wait_for_bl_fifo(cdm_hw, 1, fifo_idx);
 					if (write_count < 0) {
-						CAM_ERR(CAM_CDM,
-						"wait for bl fifo failed %d:%d",
-						i, req->data->cmd_arrary_count);
+						CAM_ERR(CAM_CDM, "wait for bl fifo failed %d:%d",
+							i, req->data->cmd_arrary_count);
 						rc = -EIO;
 						break;
 					}
 				}
 
-				if (core->arbitration !=
-					CAM_CDM_ARBITRATION_PRIORITY_BASED) {
+				if (core->arbitration == CAM_CDM_ARBITRATION_PRIORITY_BASED)
+					cdm_cmd->gen_irq_arb = true;
+				else
+					cdm_cmd->gen_irq_arb = false;
 
-					rc = cam_hw_cdm_submit_gen_irq(
-						cdm_hw, req, fifo_idx,
-						cdm_cmd->gen_irq_arb);
-					if (rc == 0)
-						core->bl_fifo[fifo_idx]
-						.bl_tag++;
-					break;
+				rc = cam_hw_cdm_submit_gen_irq(cdm_hw, req, fifo_idx,
+					cdm_cmd->gen_irq_arb);
+				if (!rc) {
+					CAM_DBG(CAM_CDM, "Commit success for GenIRQ_BL, Tag: %d",
+						core->bl_fifo[fifo_idx].bl_tag);
+					core->bl_fifo[fifo_idx].bl_tag++;
+					core->bl_fifo[fifo_idx].bl_tag %= (bl_fifo->bl_depth - 1);
 				}
-
-				rc = cam_hw_cdm_arb_submit_bl(cdm_hw, req, i,
-					fifo_idx, hw_vaddr_ptr);
-				if (rc)
-					break;
 			}
+		} else {
+			CAM_ERR(CAM_CDM,
+				"Sanity check failed for cdm_cmd: %d, Hdl: 0x%x, len: %zu, offset: 0x%x, num_cmds: %d",
+				i, cdm_cmd->cmd[i].bl_addr.mem_handle, len, cdm_cmd->cmd[i].offset,
+				req->data->cmd_arrary_count);
+			rc = -EINVAL;
+			break;
 		}
 	}
 	mutex_unlock(&client->lock);

drivers/cam_cdm/cam_cdm_intf_api.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
 #ifndef _CAM_CDM_API_H_
@@ -133,23 +133,23 @@ struct cam_cdm_bl_cmd {
  *
  * @flag : 1 for callback needed and 0 for no callback when this BL
  *            request is done
+ * @gen_irq_arb : enum for setting arbitration in gen_irq
  * @userdata :Input private data which will be returned as part
  *             of callback if request for this bl request in flags.
- * @cookie : Cookie if the callback is gen irq status
  * @type : type of the submitted bl cmd address.
  * @cmd_arrary_count : Input number of BL commands to be submitted to CDM
- * @gen_irq_arb : enum for setting arbitration in gen_irq
+ * @cookie : Cookie if the callback is gen irq status
  * @bl_cmd_array     : Input payload holding the BL cmd's arrary
  *                     to be sumbitted.
  *
  */
 struct cam_cdm_bl_request {
-	int flag;
+	bool flag;
+	bool gen_irq_arb;
 	void *userdata;
-	uint64_t cookie;
 	enum cam_cdm_bl_cmd_addr_type type;
 	uint32_t cmd_arrary_count;
-	bool gen_irq_arb;
+	uint64_t cookie;
 	struct cam_cdm_bl_cmd cmd[1];
 };
 

drivers/cam_cdm/cam_cdm_util.c

@@ -186,78 +186,78 @@ struct cdm_prefetch_disable_event_cmd {
 	unsigned int mask2;
 } __attribute__((__packed__));
 
-uint32_t cdm_get_cmd_header_size(unsigned int command)
+uint32_t cam_cdm_get_cmd_header_size(unsigned int command)
 {
 	return CDMCmdHeaderSizes[command];
 }
 
-uint32_t cdm_required_size_dmi(void)
+uint32_t cam_cdm_required_size_dmi(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
 }
 
-uint32_t cdm_required_size_reg_continuous(uint32_t numVals)
+uint32_t cam_cdm_required_size_reg_continuous(uint32_t numVals)
 {
 	if (!numVals) {
 		CAM_WARN(CAM_CDM, "numVals cant be 0");
 		return 0;
 	}
 
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT) + numVals;
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT) + numVals;
 }
 
-uint32_t cdm_required_size_reg_random(uint32_t numRegVals)
+uint32_t cam_cdm_required_size_reg_random(uint32_t numRegVals)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM) +
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM) +
 		(2 * numRegVals);
 }
 
-uint32_t cdm_required_size_indirect(void)
+uint32_t cam_cdm_required_size_indirect(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
 }
 
-uint32_t cdm_required_size_genirq(void)
+uint32_t cam_cdm_required_size_genirq(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_GEN_IRQ);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_GEN_IRQ);
 }
 
-uint32_t cdm_required_size_wait_event(void)
+uint32_t cam_cdm_required_size_wait_event(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
 }
 
-uint32_t cdm_required_size_changebase(void)
+uint32_t cam_cdm_required_size_changebase(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
 }
 
-uint32_t cdm_required_size_comp_wait(void)
+uint32_t cam_cdm_required_size_comp_wait(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
 }
 
-uint32_t cdm_required_size_clear_comp_event(void)
+uint32_t cam_cdm_required_size_clear_comp_event(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
 }
 
-uint32_t cdm_required_size_prefetch_disable(void)
+uint32_t cam_cdm_required_size_prefetch_disable(void)
 {
-	return cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
+	return cam_cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
 }
 
-uint32_t cdm_offsetof_dmi_addr(void)
+uint32_t cam_cdm_offsetof_dmi_addr(void)
 {
 	return offsetof(struct cdm_dmi_cmd, addr);
 }
 
-uint32_t cdm_offsetof_indirect_addr(void)
+uint32_t cam_cdm_offsetof_indirect_addr(void)
 {
 	return offsetof(struct cdm_indirect_cmd, addr);
 }
 
-uint32_t *cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd,
+uint32_t *cam_cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd,
 	uint32_t DMIAddr, uint8_t DMISel, uint32_t dmiBufferAddr,
 	uint32_t length)
 {
@@ -269,12 +269,12 @@ uint32_t *cdm_write_dmi(uint32_t *pCmdBuffer, uint8_t dmiCmd,
 	pHeader->DMIAddr = DMIAddr;
 	pHeader->DMISel = DMISel;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
+uint32_t *cam_cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
 	uint32_t numVals, uint32_t *pVals)
 {
 	uint32_t i;
@@ -287,7 +287,7 @@ uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
 	pHeader->reserved1 = 0;
 	pHeader->offset = reg;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
 
 	for (i = 0; i < numVals; i++)
 		(((uint32_t *)pCmdBuffer)[i]) = (((uint32_t *)pVals)[i]);
@@ -297,7 +297,7 @@ uint32_t *cdm_write_regcontinuous(uint32_t *pCmdBuffer, uint32_t reg,
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
+uint32_t *cam_cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
 	uint32_t *pRegVals)
 {
 	uint32_t i;
@@ -314,7 +314,7 @@ uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
 	pHeader->cmd = CAM_CDM_CMD_REG_RANDOM;
 	pHeader->reserved = 0;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
 	dst = pCmdBuffer;
 	src = pRegVals;
 	for (i = 0; i < numRegVals; i++) {
@@ -325,7 +325,7 @@ uint32_t *cdm_write_regrandom(uint32_t *pCmdBuffer, uint32_t numRegVals,
 	return dst;
 }
 
-uint32_t *cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr,
+uint32_t *cam_cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr,
 	uint32_t length)
 {
 	struct cdm_indirect_cmd *pHeader =
@@ -335,12 +335,12 @@ uint32_t *cdm_write_indirect(uint32_t *pCmdBuffer, uint32_t indirectBufAddr,
 	pHeader->addr = indirectBufAddr;
 	pHeader->length = length - 1;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_BUFF_INDIRECT);
 
 	return pCmdBuffer;
 }
 
-void cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata,
+void cam_cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata,
 		bool bit_wr_enable, uint32_t fifo_idx)
 {
 	struct cdm_genirq_cmd *pHeader = (struct cdm_genirq_cmd *)pCmdBuffer;
@@ -356,7 +356,7 @@ void cdm_write_genirq(uint32_t *pCmdBuffer, uint32_t userdata,
 	pHeader->userdata = (userdata << (8 * fifo_idx));
 }
 
-uint32_t *cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw,
+uint32_t *cam_cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw,
 	uint32_t id, uint32_t mask,
 	uint32_t offset, uint32_t data)
 {
@@ -372,12 +372,12 @@ uint32_t *cdm_write_wait_event(uint32_t *pcmdbuffer, uint32_t iw,
 	pheader->iw_reserved = 0;
 	pheader->offset_reserved = 0;
 
-	pcmdbuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
+	pcmdbuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_WAIT_EVENT);
 
 	return pcmdbuffer;
 }
 
-uint32_t *cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base)
+uint32_t *cam_cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base)
 {
 	struct cdm_changebase_cmd *pHeader =
 		(struct cdm_changebase_cmd *)pCmdBuffer;
@@ -386,12 +386,12 @@ uint32_t *cdm_write_changebase(uint32_t *pCmdBuffer, uint32_t base)
 
 	pHeader->cmd = CAM_CDM_CMD_CHANGE_BASE;
 	pHeader->base = base;
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_CHANGE_BASE);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_wait_comp_event(
+uint32_t *cam_cdm_write_wait_comp_event(
 	uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2)
 {
 	struct cdm_wait_comp_event_cmd *pHeader =
@@ -401,12 +401,12 @@ uint32_t *cdm_write_wait_comp_event(
 	pHeader->mask1 = mask1;
 	pHeader->mask2 = mask2;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_COMP_WAIT);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_clear_comp_event(
+uint32_t *cam_cdm_write_clear_comp_event(
 	uint32_t *pCmdBuffer, uint32_t mask1, uint32_t mask2)
 {
 	struct cdm_clear_comp_event_cmd *pHeader =
@@ -416,12 +416,12 @@ uint32_t *cdm_write_clear_comp_event(
 	pHeader->mask1 = mask1;
 	pHeader->mask2 = mask2;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_CLEAR_COMP_WAIT);
 
 	return pCmdBuffer;
 }
 
-uint32_t *cdm_write_wait_prefetch_disable(
+uint32_t *cam_cdm_write_wait_prefetch_disable(
 	uint32_t                   *pCmdBuffer,
 	uint32_t                    id,
 	uint32_t                    mask1,
@@ -435,36 +435,36 @@ uint32_t *cdm_write_wait_prefetch_disable(
 	pHeader->mask1 = mask1;
 	pHeader->mask2 = mask2;
 
-	pCmdBuffer += cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
+	pCmdBuffer += cam_cdm_get_cmd_header_size(CAM_CDM_WAIT_PREFETCH_DISABLE);
 
 	return pCmdBuffer;
 }
 
 
 struct cam_cdm_utils_ops CDM170_ops = {
-	cdm_get_cmd_header_size,
-	cdm_required_size_dmi,
-	cdm_required_size_reg_continuous,
-	cdm_required_size_reg_random,
-	cdm_required_size_indirect,
-	cdm_required_size_genirq,
-	cdm_required_size_wait_event,
-	cdm_required_size_changebase,
-	cdm_required_size_comp_wait,
-	cdm_required_size_clear_comp_event,
-	cdm_required_size_prefetch_disable,
-	cdm_offsetof_dmi_addr,
-	cdm_offsetof_indirect_addr,
-	cdm_write_dmi,
-	cdm_write_regcontinuous,
-	cdm_write_regrandom,
-	cdm_write_indirect,
-	cdm_write_genirq,
-	cdm_write_wait_event,
-	cdm_write_changebase,
-	cdm_write_wait_comp_event,
-	cdm_write_clear_comp_event,
-	cdm_write_wait_prefetch_disable,
+	.cdm_get_cmd_header_size              = cam_cdm_get_cmd_header_size,
+	.cdm_required_size_dmi                = cam_cdm_required_size_dmi,
+	.cdm_required_size_reg_continuous     = cam_cdm_required_size_reg_continuous,
+	.cdm_required_size_reg_random         = cam_cdm_required_size_reg_random,
+	.cdm_required_size_indirect           = cam_cdm_required_size_indirect,
+	.cdm_required_size_genirq             = cam_cdm_required_size_genirq,
+	.cdm_required_size_wait_event         = cam_cdm_required_size_wait_event,
+	.cdm_required_size_changebase         = cam_cdm_required_size_changebase,
+	.cdm_required_size_comp_wait          = cam_cdm_required_size_comp_wait,
+	.cdm_required_size_clear_comp_event   = cam_cdm_required_size_clear_comp_event,
+	.cdm_required_size_prefetch_disable   = cam_cdm_required_size_prefetch_disable,
+	.cdm_offsetof_dmi_addr                = cam_cdm_offsetof_dmi_addr,
+	.cdm_offsetof_indirect_addr           = cam_cdm_offsetof_indirect_addr,
+	.cdm_write_dmi                        = cam_cdm_write_dmi,
+	.cdm_write_regcontinuous              = cam_cdm_write_regcontinuous,
+	.cdm_write_regrandom                  = cam_cdm_write_regrandom,
+	.cdm_write_indirect                   = cam_cdm_write_indirect,
+	.cdm_write_genirq                     = cam_cdm_write_genirq,
+	.cdm_write_wait_event                 = cam_cdm_write_wait_event,
+	.cdm_write_changebase                 = cam_cdm_write_changebase,
+	.cdm_write_wait_comp_event            = cam_cdm_write_wait_comp_event,
+	.cdm_write_clear_comp_event           = cam_cdm_write_clear_comp_event,
+	.cdm_write_wait_prefetch_disable      = cam_cdm_write_wait_prefetch_disable,
 };
 
 int cam_cdm_get_ioremap_from_base(uint32_t hw_base,
@@ -496,7 +496,7 @@ static int cam_cdm_util_reg_cont_write(void __iomem *base_addr,
 	uint32_t *data;
 	struct cdm_regcontinuous_cmd *reg_cont;
 
-	if ((cmd_buf_size < cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) ||
+	if ((cmd_buf_size < cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) ||
 		(!base_addr)) {
 		CAM_ERR(CAM_CDM, "invalid base addr and data length  %d %pK",
 			cmd_buf_size, base_addr);
@@ -506,18 +506,18 @@ static int cam_cdm_util_reg_cont_write(void __iomem *base_addr,
 	reg_cont = (struct cdm_regcontinuous_cmd *)cmd_buf;
 	if ((!reg_cont->count) || (reg_cont->count > 0x10000) ||
 		(((reg_cont->count * sizeof(uint32_t)) +
-			cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) >
+			cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT)) >
 			cmd_buf_size)) {
 		CAM_ERR(CAM_CDM, "buffer size %d is not sufficient for count%d",
 			cmd_buf_size, reg_cont->count);
 		return -EINVAL;
 	}
-	data = cmd_buf + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	data = cmd_buf + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
 	cam_io_memcpy(base_addr + reg_cont->offset,	data,
 		reg_cont->count * sizeof(uint32_t));
 
 	*used_bytes = (reg_cont->count * sizeof(uint32_t)) +
-		(4 * cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT));
+		(4 * cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT));
 
 	return ret;
 }
@@ -537,13 +537,13 @@ static int cam_cdm_util_reg_random_write(void __iomem *base_addr,
 	reg_random = (struct cdm_regrandom_cmd *) cmd_buf;
 	if ((!reg_random->count) || (reg_random->count > 0x10000) ||
 		(((reg_random->count * (sizeof(uint32_t) * 2)) +
-		cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)) >
+		cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)) >
 			cmd_buf_size)) {
 		CAM_ERR(CAM_CDM, "invalid reg_count  %d cmd_buf_size %d",
 			reg_random->count, cmd_buf_size);
 		return -EINVAL;
 	}
-	data = cmd_buf + cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	data = cmd_buf + cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
 
 	for (i = 0; i < reg_random->count; i++) {
 		CAM_DBG(CAM_CDM, "reg random: offset %pK, value 0x%x",
@@ -554,7 +554,7 @@ static int cam_cdm_util_reg_random_write(void __iomem *base_addr,
 	}
 
 	*used_bytes = ((reg_random->count * (sizeof(uint32_t) * 2)) +
-		(4 * cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)));
+		(4 * cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM)));
 
 	return 0;
 }
@@ -569,12 +569,12 @@ static int cam_cdm_util_swd_dmi_write(uint32_t cdm_cmd_type,
 
 	swd_dmi = (struct cdm_dmi_cmd *)cmd_buf;
 
-	if (cmd_buf_size < (cdm_required_size_dmi() + swd_dmi->length + 1)) {
+	if (cmd_buf_size < (cam_cdm_required_size_dmi() + swd_dmi->length + 1)) {
 		CAM_ERR(CAM_CDM, "invalid CDM_SWD_DMI length %d",
 			swd_dmi->length + 1);
 		return -EINVAL;
 	}
-	data = cmd_buf + cdm_required_size_dmi();
+	data = cmd_buf + cam_cdm_required_size_dmi();
 
 	if (cdm_cmd_type == CAM_CDM_CMD_SWD_DMI_64) {
 		for (i = 0; i < (swd_dmi->length + 1)/8; i++) {
@@ -597,7 +597,7 @@ static int cam_cdm_util_swd_dmi_write(uint32_t cdm_cmd_type,
 			data += 1;
 		}
 	}
-	*used_bytes = (4 * cdm_required_size_dmi()) + swd_dmi->length + 1;
+	*used_bytes = (4 * cam_cdm_required_size_dmi()) + swd_dmi->length + 1;
 
 	return 0;
 }
@@ -681,8 +681,8 @@ int cam_cdm_util_cmd_buf_write(void __iomem **current_device_base,
 				change_base_cmd->base,
 				current_device_base);
 			cmd_buf_size -= (4 *
-				cdm_required_size_changebase());
-			cmd_buf += cdm_required_size_changebase();
+				cam_cdm_required_size_changebase());
+			cmd_buf += cam_cdm_required_size_changebase();
 			}
 			break;
 		default:
@@ -949,8 +949,8 @@ static uint32_t cam_cdm_util_dump_reg_cont_cmd_v2(
 	struct cam_cdm_cmd_dump_header *hdr;
 
 	p_regcont_cmd = (struct cdm_regcontinuous_cmd *)temp_ptr;
-	temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
-	ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	temp_ptr += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
+	ret = cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_CONT);
 
 	min_len = (sizeof(uint32_t) * p_regcont_cmd->count) +
 		sizeof(struct cam_cdm_cmd_dump_header) +
@@ -1000,8 +1000,8 @@ static uint32_t cam_cdm_util_dump_reg_random_cmd_v2(
 	struct cam_cdm_cmd_dump_header *hdr;
 
 	p_regrand_cmd = (struct cdm_regrandom_cmd *)temp_ptr;
-	temp_ptr += cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
-	ret = cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	temp_ptr += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
+	ret = cam_cdm_get_cmd_header_size(CAM_CDM_CMD_REG_RANDOM);
 
 	min_len = (2 * sizeof(uint32_t) * p_regrand_cmd->count) +
 		sizeof(struct cam_cdm_cmd_dump_header) + sizeof(uint32_t);
@@ -1063,7 +1063,7 @@ int cam_cdm_util_dump_cmd_bufs_v2(
 		case CAM_CDM_CMD_DMI:
 		case CAM_CDM_CMD_DMI_32:
 		case CAM_CDM_CMD_DMI_64:
-			buf_now += cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
+			buf_now += cam_cdm_get_cmd_header_size(CAM_CDM_CMD_DMI);
 			break;
 		case CAM_CDM_CMD_REG_CONT:
 			buf_now += cam_cdm_util_dump_reg_cont_cmd_v2(buf_now,
@@ -1074,27 +1074,27 @@ int cam_cdm_util_dump_cmd_bufs_v2(
 				dump_info);
 			break;
 		case CAM_CDM_CMD_BUFF_INDIRECT:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_BUFF_INDIRECT);
 			break;
 		case CAM_CDM_CMD_GEN_IRQ:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_GEN_IRQ);
 			break;
 		case CAM_CDM_CMD_WAIT_EVENT:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_WAIT_EVENT);
 			break;
 		case CAM_CDM_CMD_CHANGE_BASE:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_CHANGE_BASE);
 			break;
 		case CAM_CDM_CMD_PERF_CTRL:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_PERF_CTRL);
 			break;
 		case CAM_CDM_CMD_COMP_WAIT:
-			buf_now += cdm_get_cmd_header_size(
+			buf_now += cam_cdm_get_cmd_header_size(
 				CAM_CDM_CMD_COMP_WAIT);
 			break;
 		default:

drivers/cam_cdm/cam_cdm_virtual_core.c

@@ -160,8 +160,7 @@ int cam_virtual_cdm_submit_bl(struct cam_hw_info *cdm_hw,
 			CAM_DBG(CAM_CDM,
 				"write BL success for cnt=%d with tag=%d",
 				i, core->bl_tag);
-			if ((true == req->data->flag) &&
-				(i == req->data->cmd_arrary_count)) {
+			if (req->data->flag && (i == req->data->cmd_arrary_count)) {
 				struct cam_cdm_bl_cb_request_entry *node;
 
 				node = kzalloc(sizeof(