samsung-sm8650/android_kernel_samsung_sm8650-modules
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disp: msm: dsi: adding prefix for logs

Переглянути джерело 
Adding debug, info and error prefix for log messages
in dsi files. To enable debug logs
run "echo 0x1 > /sys/module/drm/parameters/debug"

Change-Id: I438ac16954bd1d39450f8adeb7fb17f9ea6f8140
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Цей коміт міститься в:
Satya Rama Aditya Pinapala
2019-06-25 09:46:41 -07:00
джерело 3588284310
коміт 6c483e3b23
24 змінених файлів з 1444 додано та 1418 видалено
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97
msm/dsi/dsi_ctrl_hw_cmn.c
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@@ -3,7 +3,6 @@
* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "dsi-hw:" fmt
#include <linux/delay.h>
#include <linux/iopoll.h>
@@ -120,7 +119,7 @@ void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl,
if (ctrl->phy_isolation_enabled)
DSI_W32(ctrl, DSI_DEBUG_CTRL, BIT(28));
pr_debug("[DSI_%d]Host configuration complete\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "Host configuration complete\n");
}
/**
@@ -136,7 +135,7 @@ void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl)
wmb(); /* ensure reset is cleared before waiting */
udelay(100);
pr_debug("[DSI_%d] phy sw reset done\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "phy sw reset done\n");
}
/**
@@ -178,7 +177,7 @@ void dsi_ctrl_hw_cmn_soft_reset(struct dsi_ctrl_hw *ctrl)
/* Re-enable DSI controller */
DSI_W32(ctrl, DSI_CTRL, reg_ctrl);
wmb(); /* make sure DSI controller is enabled again */
pr_debug("[DSI_%d] ctrl soft reset done\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "ctrl soft reset done\n");
}
/**
@@ -209,8 +208,7 @@ void dsi_ctrl_hw_cmn_setup_misr(struct dsi_ctrl_hw *ctrl,
config |= frame_count << 8;
}
pr_debug("[DSI_%d] MISR ctrl: 0x%x\n", ctrl->index,
config);
DSI_CTRL_HW_DBG(ctrl, "MISR ctrl: 0x%x\n", config);
DSI_W32(ctrl, addr, config);
wmb(); /* make sure MISR is configured */
}
@@ -240,8 +238,7 @@ u32 dsi_ctrl_hw_cmn_collect_misr(struct dsi_ctrl_hw *ctrl,
if (enabled)
misr = DSI_R32(ctrl, addr);
pr_debug("[DSI_%d] MISR enabled %x value: 0x%x\n", ctrl->index,
enabled, misr);
DSI_CTRL_HW_DBG(ctrl, "MISR enabled %x value: 0x%x\n", enabled, misr);
return misr;
}
@@ -261,8 +258,7 @@ void dsi_ctrl_hw_cmn_set_timing_db(struct dsi_ctrl_hw *ctrl,
DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0);
wmb(); /* make sure timing db registers are set */
pr_debug("[DSI_%d] ctrl timing DB set:%d\n", ctrl->index,
enable);
DSI_CTRL_HW_DBG(ctrl, "ctrl timing DB set:%d\n", enable);
SDE_EVT32(ctrl->index, enable);
}
@@ -338,7 +334,7 @@ void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl,
DSI_W32(ctrl, DSI_HS_TIMER_CTRL, 0x3FD08);
DSI_W32(ctrl, DSI_MISR_VIDEO_CTRL, 0x10100);
DSI_W32(ctrl, DSI_DSI_TIMING_FLUSH, 0x1);
pr_debug("[DSI_%d] ctrl video parameters updated\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "ctrl video parameters updated\n");
SDE_EVT32(v_total, h_total);
}
@@ -405,7 +401,7 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
reg_ctrl2 &= ~(0xFFFF << offset);
reg_ctrl2 |= (dsc.bytes_in_slice << offset);
pr_debug("ctrl %d reg_ctrl 0x%x reg_ctrl2 0x%x\n", ctrl->index,
DSI_CTRL_HW_DBG(ctrl, "reg_ctrl 0x%x reg_ctrl2 0x%x\n",
reg_ctrl, reg_ctrl2);
} else if (roi) {
width_final = roi->w;
@@ -442,7 +438,7 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,
DSI_W32(ctrl, DSI_COMMAND_MODE_NULL_INSERTION_CTRL, data);
}
pr_debug("ctrl %d stream_ctrl 0x%x stream_total 0x%x\n", ctrl->index,
DSI_CTRL_HW_DBG(ctrl, "stream_ctrl 0x%x stream_total 0x%x\n",
stream_ctrl, stream_total);
}
@@ -463,8 +459,7 @@ void dsi_ctrl_hw_cmn_setup_avr(struct dsi_ctrl_hw *ctrl, bool enable)
reg &= ~BIT(29);
DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg);
pr_debug("ctrl %d AVR %s\n", ctrl->index,
enable ? "enabled" : "disabled");
DSI_CTRL_HW_DBG(ctrl, "AVR %s\n", enable ? "enabled" : "disabled");
}
/**
@@ -502,7 +497,7 @@ void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl,
/* Disable Timing double buffering */
DSI_W32(ctrl, DSI_DSI_TIMING_DB_MODE, 0x0);
pr_debug("[DSI_%d] Video engine setup done\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "Video engine setup done\n");
}
void dsi_ctrl_hw_cmn_debug_bus(struct dsi_ctrl_hw *ctrl, u32 *entries, u32 size)
@@ -514,8 +509,8 @@ void dsi_ctrl_hw_cmn_debug_bus(struct dsi_ctrl_hw *ctrl, u32 *entries, u32 size)
/* make sure that debug test point is enabled */
wmb();
reg = DSI_R32(ctrl, DSI_DEBUG_BUS_STATUS);
pr_err("[DSI_%d] debug bus ctrl: 0x%x status:0x%x\n",
ctrl->index, entries[i], reg);
DSI_CTRL_HW_ERR(ctrl, "debug bus ctrl: 0x%x status:0x%x\n",
entries[i], reg);
}
}
@@ -550,7 +545,7 @@ void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl,
reg |= (cfg->insert_dcs_command ? BIT(16) : 0);
DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_DCS_CMD_CTRL, reg);
pr_debug("[DSI_%d] Cmd engine setup done\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "Cmd engine setup done\n");
}
/**
@@ -571,7 +566,7 @@ void dsi_ctrl_hw_cmn_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on)
DSI_W32(ctrl, DSI_CTRL, reg);
pr_debug("[DSI_%d] Video engine = %d\n", ctrl->index, on);
DSI_CTRL_HW_DBG(ctrl, "Video engine = %d\n", on);
}
/**
@@ -601,7 +596,7 @@ void dsi_ctrl_hw_cmn_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on)
DSI_W32(ctrl, DSI_CLK_CTRL, clk_ctrl);
wmb(); /* make sure clocks are restored */
pr_debug("[DSI_%d] Controller engine = %d\n", ctrl->index, on);
DSI_CTRL_HW_DBG(ctrl, "Controller engine = %d\n", on);
}
/**
@@ -622,7 +617,7 @@ void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on)
DSI_W32(ctrl, DSI_CTRL, reg);
pr_debug("[DSI_%d] command engine = %d\n", ctrl->index, on);
DSI_CTRL_HW_DBG(ctrl, "command engine = %d\n", on);
}
/**
@@ -746,8 +741,7 @@ void dsi_ctrl_hw_cmn_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl,
if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
pr_debug("[DSI_%d]size=%d, trigger = %d\n",
ctrl->index, cmd->size,
DSI_CTRL_HW_DBG(ctrl, "size=%d, trigger = %d\n", cmd->size,
(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER) ? false : true);
}
@@ -772,7 +766,7 @@ void dsi_ctrl_hw_cmn_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl)
void dsi_ctrl_hw_cmn_trigger_command_dma(struct dsi_ctrl_hw *ctrl)
{
DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
pr_debug("[DSI_%d] CMD DMA triggered\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "CMD DMA triggered\n");
}
/**
@@ -827,7 +821,7 @@ u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
if (ack_err)
read_cnt -= 4;
if (!read_cnt) {
pr_err("Panel detected error, no data read\n");
DSI_CTRL_HW_ERR(ctrl, "Panel detected error, no data read\n");
return 0;
}
@@ -861,7 +855,7 @@ u32 dsi_ctrl_hw_cmn_get_cmd_read_data(struct dsi_ctrl_hw *ctrl,
}
*hw_read_cnt = read_cnt;
pr_debug("[DSI_%d] Read %d bytes\n", ctrl->index, rx_byte);
DSI_CTRL_HW_DBG(ctrl, "Read %d bytes\n", rx_byte);
return rx_byte;
}
@@ -903,8 +897,8 @@ u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl)
if (reg & BIT(24))
ints |= DSI_ERROR;
pr_debug("[DSI_%d] Interrupt status = 0x%x, INT_CTRL=0x%x\n",
ctrl->index, ints, reg);
DSI_CTRL_HW_DBG(ctrl, "Interrupt status = 0x%x, INT_CTRL=0x%x\n",
ints, reg);
return ints;
}
@@ -946,8 +940,8 @@ void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints)
reg &= ~BIT(24);
DSI_W32(ctrl, DSI_INT_CTRL, reg);
pr_debug("[DSI_%d] Clear interrupts, ints = 0x%x, INT_CTRL=0x%x\n",
ctrl->index, ints, reg);
DSI_CTRL_HW_DBG(ctrl, "Clear interrupts, ints = 0x%x, INT_CTRL=0x%x\n",
ints, reg);
}
/**
@@ -988,8 +982,8 @@ void dsi_ctrl_hw_cmn_enable_status_interrupts(
DSI_W32(ctrl, DSI_INT_CTRL, reg);
pr_debug("[DSI_%d] Enable interrupts 0x%x, INT_CTRL=0x%x\n",
ctrl->index, ints, reg);
DSI_CTRL_HW_DBG(ctrl, "Enable interrupts 0x%x, INT_CTRL=0x%x\n", ints,
reg);
}
/**
@@ -1076,10 +1070,10 @@ u64 dsi_ctrl_hw_cmn_get_error_status(struct dsi_ctrl_hw *ctrl)
if (dsi_status & BIT(31))
errors |= DSI_INTERLEAVE_OP_CONTENTION;
pr_debug("[DSI_%d] Error status = 0x%llx, phy=0x%x, fifo=0x%x\n",
ctrl->index, errors, dln0_phy_err, fifo_status);
pr_debug("[DSI_%d] ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
ctrl->index, ack_error, timeout_errors, clk_error, dsi_status);
DSI_CTRL_HW_DBG(ctrl, "Error status = 0x%llx, phy=0x%x, fifo=0x%x\n",
errors, dln0_phy_err, fifo_status);
DSI_CTRL_HW_DBG(ctrl, "ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
ack_error, timeout_errors, clk_error, dsi_status);
return errors;
}
@@ -1165,10 +1159,10 @@ void dsi_ctrl_hw_cmn_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors)
DSI_W32(ctrl, DSI_CLK_STATUS, clk_error);
DSI_W32(ctrl, DSI_STATUS, dsi_status);
pr_debug("[DSI_%d] clear errors = 0x%llx, phy=0x%x, fifo=0x%x\n",
ctrl->index, errors, dln0_phy_err, fifo_status);
pr_debug("[DSI_%d] ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
ctrl->index, ack_error, timeout_error, clk_error, dsi_status);
DSI_CTRL_HW_DBG(ctrl, "clear errors = 0x%llx, phy=0x%x, fifo=0x%x\n",
errors, dln0_phy_err, fifo_status);
DSI_CTRL_HW_DBG(ctrl, "ack=0x%x, timeout=0x%x, clk=0x%x, dsi=0x%x\n",
ack_error, timeout_error, clk_error, dsi_status);
}
/**
@@ -1252,8 +1246,8 @@ void dsi_ctrl_hw_cmn_enable_error_interrupts(struct dsi_ctrl_hw *ctrl,
DSI_W32(ctrl, DSI_INT_CTRL, int_ctrl);
DSI_W32(ctrl, DSI_ERR_INT_MASK0, int_mask0);
pr_debug("[DSI_%d] enable errors = 0x%llx, int_mask0=0x%x\n",
ctrl->index, errors, int_mask0);
DSI_CTRL_HW_DBG(ctrl, "[DSI_%d] enable errors = 0x%llx, int_mask0=0x%x\n",
errors, int_mask0);
}
/**
@@ -1288,7 +1282,7 @@ void dsi_ctrl_hw_cmn_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
DSI_W32(ctrl, DSI_TPG_VIDEO_CONFIG, 0x5);
DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
pr_debug("[DSI_%d] Video test pattern setup done\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "Video test pattern setup done\n");
}
/**
@@ -1345,7 +1339,7 @@ void dsi_ctrl_hw_cmn_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl,
}
DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
pr_debug("[DSI_%d] Cmd test pattern setup done\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "Cmd test pattern setup done\n");
}
/**
@@ -1365,7 +1359,7 @@ void dsi_ctrl_hw_cmn_test_pattern_enable(struct dsi_ctrl_hw *ctrl,
DSI_W32(ctrl, DSI_TEST_PATTERN_GEN_CTRL, reg);
pr_debug("[DSI_%d] Test pattern enable=%d\n", ctrl->index, enable);
DSI_CTRL_HW_DBG(ctrl, "Test pattern enable=%d\n", enable);
}
/**
@@ -1391,7 +1385,7 @@ void dsi_ctrl_hw_cmn_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl,
break;
}
pr_debug("[DSI_%d] Cmd Test pattern trigger\n", ctrl->index);
DSI_CTRL_HW_DBG(ctrl, "Cmd Test pattern trigger\n");
}
void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl)
@@ -1405,7 +1399,7 @@ void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl)
status = DSI_R32(ctrl, DSI_DLN0_PHY_ERR);
if (status & 0x011111) {
DSI_W32(ctrl, DSI_DLN0_PHY_ERR, status);
pr_err("%s: phy_err_status = %x\n", __func__, status);
DSI_CTRL_HW_ERR(ctrl, "phy_err_status = %x\n", status);
}
}
@@ -1431,8 +1425,7 @@ int dsi_ctrl_hw_cmn_ctrl_reset(struct dsi_ctrl_hw *ctrl,
int rc = 0;
u32 data;
pr_debug("DSI CTRL and PHY reset. ctrl-num = %d %d\n",
ctrl->index, mask);
DSI_CTRL_HW_DBG(ctrl, "DSI CTRL and PHY reset, mask=%d\n", mask);
data = DSI_R32(ctrl, 0x0004);
/* Disable DSI video mode */
@@ -1563,7 +1556,7 @@ int dsi_ctrl_hw_cmn_wait_for_cmd_mode_mdp_idle(struct dsi_ctrl_hw *ctrl)
rc = readl_poll_timeout(ctrl->base + DSI_STATUS, val,
!(val & cmd_mode_mdp_busy_mask), sleep_us, timeout_us);
if (rc)
pr_err("%s: timed out waiting for idle\n", __func__);
DSI_CTRL_HW_ERR(ctrl, "timed out waiting for idle\n");
return rc;
}
@@ -1604,7 +1597,7 @@ int dsi_ctrl_hw_cmn_wait4dynamic_refresh_done(struct dsi_ctrl_hw *ctrl)
rc = readl_poll_timeout(ctrl->base + DSI_INT_CTRL, reg,
(reg & dyn_refresh_done), sleep_us, timeout_us);
if (rc) {
pr_err("wait4dynamic refresh timedout %d\n", rc);
DSI_CTRL_HW_ERR(ctrl, "wait4dynamic refresh timedout %d\n", rc);
return rc;
}