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msm: camera: csiphy: Add more datarate setting ranges

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Add more datarate specific setting ranges to cover the
finer gsps ranges. Dump all the common status registers
on the error rather than just the irq status registers.

CRs-Fixed: 3022770
Change-Id: I6dc5e8d695a40c1633c054e5420084f1ec771485
Signed-off-by: Jigar Agrawal <jigar@codeaurora.org>
This commit is contained in:
Jigar Agrawal
2021-08-19 09:48:03 -07:00
parent 7eff3cb4b6
commit 6c439c1a5a
14 changed files with 465 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c
View File

@@ -762,8 +762,8 @@ irqreturn_t cam_csiphy_irq(int irq_num, void *data)
base = csiphy_dev->soc_info.reg_map[0].mem_base;
csiphy_reg = &csiphy_dev->ctrl_reg->csiphy_reg;
if (csiphy_dev->enable_irq_status_reg_dump) {
cam_csiphy_irq_status_reg_dmp(csiphy_dev);
if (csiphy_dev->en_common_status_reg_dump) {
cam_csiphy_common_status_reg_dump(csiphy_dev);
cam_io_w_mb(0x1, base + csiphy_reg->mipi_csiphy_glbl_irq_cmd_addr);
cam_io_w_mb(0x0, base + csiphy_reg->mipi_csiphy_glbl_irq_cmd_addr);
}

6
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.c
View File

@@ -25,7 +25,7 @@ static void cam_csiphy_subdev_handle_message(
CAM_INFO(CAM_CSIPHY, "subdev index : %d CSIPHY index: %d",
csiphy_dev->soc_info.index, data);
if (data == csiphy_dev->soc_info.index) {
cam_csiphy_irq_status_reg_dmp(csiphy_dev);
cam_csiphy_common_status_reg_dump(csiphy_dev);
if (csiphy_dev->en_full_phy_reg_dump)
cam_csiphy_reg_dump(&csiphy_dev->soc_info);
@@ -71,8 +71,8 @@ static int cam_csiphy_debug_register(struct csiphy_device *csiphy_dev)
return -ENOENT;
}
debugfs_create_bool("en_irq_status_reg_dump", 0644,
dbgfileptr, &csiphy_dev->enable_irq_status_reg_dump);
debugfs_create_bool("en_common_status_reg_dump", 0644,
dbgfileptr, &csiphy_dev->en_common_status_reg_dump);
debugfs_create_bool("en_lane_status_reg_dump", 0644,
dbgfileptr, &csiphy_dev->en_lane_status_reg_dump);

9
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h
View File

@@ -34,7 +34,7 @@
#define MAX_LANES 5
#define MAX_SETTINGS_PER_LANE 50
#define MAX_DATA_RATES 3
#define MAX_DATA_RATES 12
#define MAX_DATA_RATE_REGS 30
#define CAMX_CSIPHY_DEV_NAME "cam-csiphy-driver"
@@ -113,6 +113,8 @@ struct cam_cphy_dphy_status_reg_params_t {
* @mipi_csiphy_interrupt_mask_val : CSIPhy interrupt mask val
* @mipi_csiphy_interrupt_clear0_addr : CSIPhy interrupt clear addr
* @csiphy_version : CSIPhy Version
* @csiphy_interrupt_status_size : Number of interrupt status registers
* @csiphy_num_common_status_regs : Number of common status registers
* @csiphy_common_array_size : CSIPhy common array size
* @csiphy_reset_enter_array_size : CSIPhy reset array size
* @csiphy_reset_exit_array_size : CSIPhy reset release array size
@@ -139,6 +141,7 @@ struct csiphy_reg_parms_t {
uint32_t mipi_csiphy_interrupt_clear0_addr;
uint32_t csiphy_version;
uint32_t csiphy_interrupt_status_size;
uint32_t csiphy_num_common_status_regs;
uint32_t csiphy_common_array_size;
uint32_t csiphy_reset_enter_array_size;
uint32_t csiphy_reset_exit_array_size;
@@ -312,7 +315,7 @@ struct csiphy_work_queue {
* @ops : KMD operations
* @crm_cb : Callback API pointers
* @prgm_cmn_reg_across_csiphy : Flag to decide if com settings need to be programmed for all PHYs
* @enable_irq_status_reg_dump : Debugfs flag to enable hw IRQ status register dump
* @en_common_status_reg_dump : Debugfs flag to enable common status register dump
* @en_lane_status_reg_dump : Debugfs flag to enable cphy/dphy lane status dump
* @en_full_phy_reg_dump : Debugfs flag to enable the dump for all the Phy registers
* @preamble_enable : To enable preamble pattern
@@ -347,7 +350,7 @@ struct csiphy_device {
struct cam_req_mgr_kmd_ops ops;
struct cam_req_mgr_crm_cb *crm_cb;
bool prgm_cmn_reg_across_csiphy;
bool enable_irq_status_reg_dump;
bool en_common_status_reg_dump;
bool en_lane_status_reg_dump;
bool en_full_phy_reg_dump;
uint16_t preamble_enable;

17
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c
View File

@@ -92,14 +92,14 @@ int32_t cam_csiphy_reg_dump(struct cam_hw_soc_info *soc_info)
return rc;
}
int32_t cam_csiphy_irq_status_reg_dmp(struct csiphy_device *csiphy_dev)
int32_t cam_csiphy_common_status_reg_dump(struct csiphy_device *csiphy_dev)
{
struct csiphy_reg_parms_t *csiphy_reg = NULL;
int32_t rc = 0;
resource_size_t size = 0;
void __iomem *phy_base = NULL;
int reg_id = 0;
uint32_t irq, status_reg, clear_reg;
uint32_t val, status_reg, clear_reg;
if (!csiphy_dev) {
rc = -EINVAL;
@@ -111,19 +111,20 @@ int32_t cam_csiphy_irq_status_reg_dmp(struct csiphy_device *csiphy_dev)
phy_base = csiphy_dev->soc_info.reg_map[0].mem_base;
status_reg = csiphy_reg->mipi_csiphy_interrupt_status0_addr;
clear_reg = csiphy_reg->mipi_csiphy_interrupt_clear0_addr;
size = csiphy_reg->csiphy_interrupt_status_size;
size = csiphy_reg->csiphy_num_common_status_regs;
CAM_INFO(CAM_CSIPHY, "PHY base addr=%pK offset=0x%x size=%d",
phy_base, status_reg, size);
if (phy_base != NULL) {
for (reg_id = 0; reg_id < size; reg_id++) {
irq = cam_io_r(phy_base + status_reg + (0x4 * reg_id));
cam_io_w_mb(irq, phy_base + clear_reg + (0x4 * reg_id));
val = cam_io_r(phy_base + status_reg + (0x4 * reg_id));
CAM_INFO(CAM_CSIPHY,
"CSIPHY%d_IRQ_STATUS_ADDR%d = 0x%x",
csiphy_dev->soc_info.index, reg_id, irq);
if (reg_id < csiphy_reg->csiphy_interrupt_status_size)
cam_io_w_mb(val, phy_base + clear_reg + (0x4 * reg_id));
CAM_INFO(CAM_CSIPHY, "CSIPHY%d_COMMON_STATUS%u = 0x%x",
csiphy_dev->soc_info.index, reg_id, val);
}
} else {
rc = -EINVAL;

2
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h
View File

@@ -75,5 +75,5 @@ int cam_csiphy_reg_dump(struct cam_hw_soc_info *soc_info);
*
* This API dumps memory for the entire status region
*/
int32_t cam_csiphy_irq_status_reg_dmp(struct csiphy_device *csiphy_dev);
int32_t cam_csiphy_common_status_reg_dump(struct csiphy_device *csiphy_dev);
#endif /* _CAM_CSIPHY_SOC_H_ */

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_0_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v1_0 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 11,
.csiphy_common_array_size = 5,
.csiphy_reset_enter_array_size = 5,
.csiphy_reset_exit_array_size = 0,

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_1_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v1_1 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 11,
.csiphy_common_array_size = 5,
.csiphy_reset_enter_array_size = 5,
.csiphy_reset_exit_array_size = 0,

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_1_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_1 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 11,
.csiphy_common_array_size = 7,
.csiphy_reset_enter_array_size = 5,
.csiphy_reset_exit_array_size = 0,

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_2_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_2 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 11,
.csiphy_common_array_size = 8,
.csiphy_reset_enter_array_size = 5,
.csiphy_reset_exit_array_size = 0,

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_3 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 12,
.csiphy_common_array_size = 5,
.csiphy_reset_enter_array_size = 2,
.csiphy_reset_exit_array_size = 0,

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_5_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v1_2_5 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 11,
.csiphy_common_array_size = 6,
.csiphy_reset_enter_array_size = 5,
.csiphy_reset_exit_array_size = 0,

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v1_2 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 11,
.csiphy_common_array_size = 7,
.csiphy_reset_enter_array_size = 5,
.csiphy_reset_exit_array_size = 0,

1
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_0_hwreg.h
View File

@@ -15,6 +15,7 @@ struct csiphy_reg_parms_t csiphy_v2_0 = {
.status_reg_params = NULL,
.size_offset_betn_lanes = 0x200,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 11,
.csiphy_common_array_size = 8,
.csiphy_reset_enter_array_size = 5,
.csiphy_reset_exit_array_size = 0,

478
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_0_hwreg.h
View File

@@ -32,10 +32,11 @@ struct csiphy_reg_parms_t csiphy_v2_1_0 = {
.csiphy_reset_enter_array_size = 2,
.csiphy_reset_exit_array_size = 3,
.csiphy_2ph_config_array_size = 23,
.csiphy_3ph_config_array_size = 38,
.csiphy_3ph_config_array_size = 37,
.csiphy_2ph_clock_lane = 0x1,
.csiphy_2ph_combo_ck_ln = 0x10,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 20,
.aon_sel_params = &aon_cam_select_params,
};
@@ -338,7 +339,6 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x02F0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
{0x02F0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
{0x0294, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x020C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -378,7 +378,6 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x06F0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
{0x06F0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
{0x0694, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x060C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -418,7 +417,6 @@ struct csiphy_reg_t csiphy_3ph_v2_1_0_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{0x0AF0, 0x00, 0x02, CSIPHY_DEFAULT_PARAMS},
{0x0AF0, 0xEF, 0x64, CSIPHY_DEFAULT_PARAMS},
{0x0A94, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A0C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
@@ -504,101 +502,280 @@ struct bist_reg_settings_t bist_setting_2_1_0 = {
};
struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
.num_data_rate_settings = 3,
.num_data_rate_settings = 12,
.data_rate_settings = {
{
/* ((1 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 2280000000,
.data_rate_reg_array_size = 6,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x10, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((2 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 4560000000,
.data_rate_reg_array_size = 6,
/* ((1.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 3420000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x40, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x4D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((3.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 7980000000,
.data_rate_reg_array_size = 6,
/* ((1.7 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 3876000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((2.1 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 4788000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x32, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((2.35 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 5358000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x2E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((2.6 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 5928000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x24, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xE0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((2.8 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 6384000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x13, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
@@ -606,10 +783,11 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x13, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
@@ -617,10 +795,226 @@ struct data_rate_settings_t data_rate_delta_table_2_1_0 = {
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x13, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x28, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((3.3 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 7524000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x1D, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((3.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 7980000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x15, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((4 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 9120000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((4.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 10260000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((5.0 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value */
.bandwidth = 11400000000,
.data_rate_reg_array_size = 7,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0xC1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x18, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
},
},