Merge "disp: msm: dsi: rework DSI PLL to be configured within PHY" into display-kernel.lnx.5.10
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@@ -2608,26 +2608,68 @@ error:
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return rc;
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}
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int dsi_display_phy_pll_toggle(void *priv, bool prepare)
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{
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int rc = 0;
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struct dsi_display *display = priv;
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struct dsi_display_ctrl *m_ctrl;
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if (!display) {
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DSI_ERR("invalid arguments\n");
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return -EINVAL;
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}
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m_ctrl = &display->ctrl[display->clk_master_idx];
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if (!m_ctrl->phy) {
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DSI_ERR("[%s] PHY not found\n", display->name);
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return -EINVAL;
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}
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rc = dsi_phy_pll_toggle(m_ctrl->phy, prepare);
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return rc;
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}
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int dsi_display_phy_configure(void *priv, bool commit)
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{
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int rc = 0;
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struct dsi_display *display = priv;
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struct dsi_display_ctrl *m_ctrl;
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struct dsi_pll_resource *pll_res;
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struct dsi_ctrl *ctrl;
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if (!display) {
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DSI_ERR("invalid arguments\n");
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return -EINVAL;
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}
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m_ctrl = &display->ctrl[display->clk_master_idx];
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if ((!m_ctrl->phy) || (!m_ctrl->ctrl)) {
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DSI_ERR("[%s] PHY not found\n", display->name);
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return -EINVAL;
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}
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pll_res = m_ctrl->phy->pll;
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if (!pll_res) {
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DSI_ERR("[%s] PLL res not found\n", display->name);
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return -EINVAL;
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}
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ctrl = m_ctrl->ctrl;
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pll_res->byteclk_rate = ctrl->clk_freq.byte_clk_rate;
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pll_res->pclk_rate = ctrl->clk_freq.pix_clk_rate;
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rc = dsi_phy_configure(m_ctrl->phy, commit);
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return rc;
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}
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static int dsi_display_set_clk_src(struct dsi_display *display)
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{
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int rc = 0;
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int i;
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struct dsi_display_ctrl *m_ctrl, *ctrl;
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/*
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* For CPHY mode, the parent of mux_clks need to be set
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* to Cphy_clks to have correct dividers for byte and
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* pixel clocks.
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*/
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if (display->panel->host_config.phy_type == DSI_PHY_TYPE_CPHY) {
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rc = dsi_clk_update_parent(&display->clock_info.cphy_clks,
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&display->clock_info.mux_clks);
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if (rc) {
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DSI_ERR("failed update mux parent to shadow\n");
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return rc;
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}
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}
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/*
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* In case of split DSI usecases, the clock for master controller should
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* be enabled before the other controller. Master controller in the
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@@ -2636,7 +2678,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display)
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m_ctrl = &display->ctrl[display->clk_master_idx];
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rc = dsi_ctrl_set_clock_source(m_ctrl->ctrl,
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&display->clock_info.mux_clks);
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&display->clock_info.pll_clks);
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if (rc) {
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DSI_ERR("[%s] failed to set source clocks for master, rc=%d\n",
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display->name, rc);
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@@ -2650,7 +2692,7 @@ static int dsi_display_set_clk_src(struct dsi_display *display)
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continue;
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rc = dsi_ctrl_set_clock_source(ctrl->ctrl,
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&display->clock_info.mux_clks);
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&display->clock_info.pll_clks);
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if (rc) {
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DSI_ERR("[%s] failed to set source clocks, rc=%d\n",
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display->name, rc);
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@@ -3320,46 +3362,6 @@ static int dsi_display_mipi_host_deinit(struct dsi_display *display)
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return rc;
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}
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static int dsi_display_clocks_deinit(struct dsi_display *display)
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{
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int rc = 0;
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struct dsi_clk_link_set *src = &display->clock_info.src_clks;
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struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
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struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
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if (src->byte_clk) {
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devm_clk_put(&display->pdev->dev, src->byte_clk);
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src->byte_clk = NULL;
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}
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if (src->pixel_clk) {
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devm_clk_put(&display->pdev->dev, src->pixel_clk);
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src->pixel_clk = NULL;
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}
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if (mux->byte_clk) {
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devm_clk_put(&display->pdev->dev, mux->byte_clk);
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mux->byte_clk = NULL;
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}
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if (mux->pixel_clk) {
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devm_clk_put(&display->pdev->dev, mux->pixel_clk);
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mux->pixel_clk = NULL;
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}
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if (shadow->byte_clk) {
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devm_clk_put(&display->pdev->dev, shadow->byte_clk);
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shadow->byte_clk = NULL;
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}
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if (shadow->pixel_clk) {
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devm_clk_put(&display->pdev->dev, shadow->pixel_clk);
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shadow->pixel_clk = NULL;
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}
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return rc;
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}
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static bool dsi_display_check_prefix(const char *clk_prefix,
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const char *clk_name)
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{
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@@ -3393,20 +3395,9 @@ static int dsi_display_clocks_init(struct dsi_display *display)
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{
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int i, rc = 0, num_clk = 0;
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const char *clk_name;
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const char *src_byte = "src_byte", *src_pixel = "src_pixel";
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const char *mux_byte = "mux_byte", *mux_pixel = "mux_pixel";
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const char *cphy_byte = "cphy_byte", *cphy_pixel = "cphy_pixel";
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const char *shadow_byte = "shadow_byte", *shadow_pixel = "shadow_pixel";
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const char *shadow_cphybyte = "shadow_cphybyte",
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*shadow_cphypixel = "shadow_cphypixel";
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const char *pll_byte = "pll_byte", *pll_dsi = "pll_dsi";
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struct clk *dsi_clk;
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struct dsi_clk_link_set *src = &display->clock_info.src_clks;
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struct dsi_clk_link_set *mux = &display->clock_info.mux_clks;
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struct dsi_clk_link_set *cphy = &display->clock_info.cphy_clks;
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struct dsi_clk_link_set *shadow = &display->clock_info.shadow_clks;
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struct dsi_clk_link_set *shadow_cphy =
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&display->clock_info.shadow_cphy_clks;
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struct dsi_dyn_clk_caps *dyn_clk_caps = &(display->panel->dyn_clk_caps);
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struct dsi_clk_link_set *pll = &display->clock_info.pll_clks;
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char *dsi_clock_name;
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if (!strcmp(display->display_type, "primary"))
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@@ -3416,8 +3407,6 @@ static int dsi_display_clocks_init(struct dsi_display *display)
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num_clk = dsi_display_get_clocks_count(display, dsi_clock_name);
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DSI_DEBUG("clk count=%d\n", num_clk);
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for (i = 0; i < num_clk; i++) {
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dsi_display_get_clock_name(display, dsi_clock_name, i,
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&clk_name);
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@@ -3430,105 +3419,30 @@ static int dsi_display_clocks_init(struct dsi_display *display)
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DSI_ERR("failed to get %s, rc=%d\n", clk_name, rc);
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if (dsi_display_check_prefix(mux_byte, clk_name)) {
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mux->byte_clk = NULL;
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goto error;
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}
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if (dsi_display_check_prefix(mux_pixel, clk_name)) {
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mux->pixel_clk = NULL;
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if (dsi_display_check_prefix(pll_byte, clk_name)) {
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pll->byte_clk = NULL;
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goto error;
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}
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if (dsi_display_check_prefix(cphy_byte, clk_name)) {
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cphy->byte_clk = NULL;
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if (dsi_display_check_prefix(pll_dsi, clk_name)) {
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pll->pixel_clk = NULL;
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goto error;
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}
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if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
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cphy->pixel_clk = NULL;
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goto error;
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}
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if (dyn_clk_caps->dyn_clk_support &&
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(display->panel->panel_mode ==
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DSI_OP_VIDEO_MODE)) {
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if (dsi_display_check_prefix(src_byte,
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clk_name))
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src->byte_clk = NULL;
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if (dsi_display_check_prefix(src_pixel,
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clk_name))
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src->pixel_clk = NULL;
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if (dsi_display_check_prefix(shadow_byte,
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clk_name))
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shadow->byte_clk = NULL;
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if (dsi_display_check_prefix(shadow_pixel,
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clk_name))
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shadow->pixel_clk = NULL;
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if (dsi_display_check_prefix(shadow_cphybyte,
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clk_name))
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shadow_cphy->byte_clk = NULL;
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if (dsi_display_check_prefix(shadow_cphypixel,
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clk_name))
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shadow_cphy->pixel_clk = NULL;
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dyn_clk_caps->dyn_clk_support = false;
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}
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}
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if (dsi_display_check_prefix(src_byte, clk_name)) {
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src->byte_clk = dsi_clk;
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if (dsi_display_check_prefix(pll_byte, clk_name)) {
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pll->byte_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(pll_dsi, clk_name)) {
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pll->pixel_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(src_pixel, clk_name)) {
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src->pixel_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(cphy_byte, clk_name)) {
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cphy->byte_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(cphy_pixel, clk_name)) {
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cphy->pixel_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(mux_byte, clk_name)) {
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mux->byte_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(mux_pixel, clk_name)) {
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mux->pixel_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(shadow_byte, clk_name)) {
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shadow->byte_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(shadow_pixel, clk_name)) {
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shadow->pixel_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(shadow_cphybyte, clk_name)) {
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shadow_cphy->byte_clk = dsi_clk;
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continue;
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}
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if (dsi_display_check_prefix(shadow_cphypixel, clk_name)) {
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shadow_cphy->pixel_clk = dsi_clk;
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continue;
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}
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}
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return 0;
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error:
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(void)dsi_display_clocks_deinit(display);
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return rc;
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}
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@@ -4168,10 +4082,6 @@ static int dsi_display_res_deinit(struct dsi_display *display)
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int i;
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struct dsi_display_ctrl *ctrl;
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rc = dsi_display_clocks_deinit(display);
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if (rc)
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DSI_ERR("clocks deinit failed, rc=%d\n", rc);
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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dsi_phy_put(ctrl->phy);
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@@ -4506,28 +4416,17 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display,
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u8 ctrl_version;
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struct dsi_display_ctrl *m_ctrl, *ctrl;
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struct dsi_dyn_clk_caps *dyn_clk_caps;
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struct dsi_clk_link_set *parent_clk, *enable_clk;
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struct dsi_clk_link_set *enable_clk;
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m_ctrl = &display->ctrl[display->clk_master_idx];
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dyn_clk_caps = &(display->panel->dyn_clk_caps);
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ctrl_version = m_ctrl->ctrl->version;
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if (dsi_display_is_type_cphy(display)) {
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enable_clk = &display->clock_info.cphy_clks;
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parent_clk = &display->clock_info.shadow_cphy_clks;
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} else {
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enable_clk = &display->clock_info.src_clks;
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parent_clk = &display->clock_info.shadow_clks;
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}
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enable_clk = &display->clock_info.pll_clks;
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dsi_clk_prepare_enable(enable_clk);
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rc = dsi_clk_update_parent(parent_clk,
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&display->clock_info.mux_clks);
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if (rc) {
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DSI_ERR("failed to update mux parent\n");
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goto exit;
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}
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dsi_display_phy_configure(display, false);
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display_for_each_ctrl(i, display) {
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ctrl = &display->ctrl[i];
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@@ -4584,8 +4483,6 @@ static int _dsi_display_dyn_update_clks(struct dsi_display *display,
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}
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defer_dfps_wait:
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rc = dsi_clk_update_parent(enable_clk,
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&display->clock_info.mux_clks);
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if (rc)
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DSI_ERR("could not switch back to src clks %d\n", rc);
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@@ -4612,9 +4509,6 @@ recover_byte_clk:
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bkp_freq->byte_intf_clk_rate, i);
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}
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exit:
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dsi_clk_disable_unprepare(&display->clock_info.src_clks);
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return rc;
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}
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@@ -5530,6 +5424,8 @@ static int dsi_display_bind(struct device *dev,
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info.pre_clkon_cb = dsi_pre_clkon_cb;
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info.post_clkoff_cb = dsi_post_clkoff_cb;
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info.post_clkon_cb = dsi_post_clkon_cb;
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info.phy_config_cb = dsi_display_phy_configure;
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info.phy_pll_toggle_cb = dsi_display_phy_pll_toggle;
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info.priv_data = display;
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info.master_ndx = display->clk_master_idx;
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info.dsi_ctrl_count = display->ctrl_count;
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