disp: msm: dp: enable data flow related interrupts

Enable interrupts to monitor SST/MST data flow related notifications
from hw.

Change-Id: I28ffc7af1445fdb48f38b11974a05bf84f7e6bc7
Signed-off-by: Nisarg Bhavsar <[email protected]>
Signed-off-by: Rajkumar Subbiah <[email protected]>

msm/dp/dp_catalog.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -36,10 +36,18 @@
 
 #define DP_INTERRUPT_STATUS2 \
 	(DP_INTR_READY_FOR_VIDEO | DP_INTR_IDLE_PATTERN_SENT | \
-	DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED)
+	DP_INTR_FRAME_END | DP_INTR_CRC_UPDATED | DP_INTR_SST_FIFO_UNDERFLOW)
 
 #define DP_INTR_MASK2		(DP_INTERRUPT_STATUS2 << 2)
 
+
+#define DP_INTERRUPT_STATUS3 \
+	(DP_INTR_SST_ML_FIFO_OVERFLOW | DP_INTR_MST0_ML_FIFO_OVERFLOW | \
+	DP_INTR_MST1_ML_FIFO_OVERFLOW | DP_INTR_DP1_FRAME_END | DP_INTR_SDP0_COLLISION | \
+	DP_INTR_SDP1_COLLISION)
+
+#define DP_INTR_MASK3		(DP_INTERRUPT_STATUS3 << 2)
+
 #define DP_INTERRUPT_STATUS5 \
 	(DP_INTR_MST_DP0_VCPF_SENT | DP_INTR_MST_DP1_VCPF_SENT)
 
@@ -47,6 +55,11 @@
 #define DP_TPG_PATTERN_MAX	9
 #define DP_TPG_PATTERN_DEFAULT	8
 
+#define DP_INTERRUPT_STATUS6 \
+	(DP_INTR_SST_BS_LATE | DP_INTR_DP0_BACKPRESSURE_ERROR | DP_INTR_DP1_BACKPRESSURE_ERROR)
+
+#define DP_INTR_MASK6		(DP_INTERRUPT_STATUS6 << 2)
+
 #define dp_catalog_fill_io(x) { \
 	catalog->io.x = parser->get_io(parser, #x); \
 }
@@ -1800,18 +1813,25 @@ static void dp_catalog_ctrl_enable_irq(struct dp_catalog_ctrl *ctrl,
 	if (enable) {
 		dp_write(DP_INTR_STATUS, DP_INTR_MASK1);
 		dp_write(DP_INTR_STATUS2, DP_INTR_MASK2);
+		dp_write(DP_INTR_STATUS3, DP_INTR_MASK3);
 		dp_write(DP_INTR_STATUS5, DP_INTR_MASK5);
+		dp_write(DP_INTR_STATUS6, DP_INTR_MASK6);
 	} else {
 		/* disable interrupts */
 		dp_write(DP_INTR_STATUS, 0x00);
 		dp_write(DP_INTR_STATUS2, 0x00);
+		dp_write(DP_INTR_STATUS3, 0x00);
 		dp_write(DP_INTR_STATUS5, 0x00);
+		dp_write(DP_INTR_STATUS6, 0x00);
 		wmb();
 
 		/* clear all pending interrupts */
 		dp_write(DP_INTR_STATUS, DP_INTERRUPT_STATUS1 << 1);
 		dp_write(DP_INTR_STATUS2, DP_INTERRUPT_STATUS2 << 1);
+		dp_write(DP_INTR_STATUS3, DP_INTERRUPT_STATUS3 << 1);
 		dp_write(DP_INTR_STATUS5, DP_INTERRUPT_STATUS5 << 1);
+		dp_write(DP_INTR_STATUS6, DP_INTERRUPT_STATUS6 << 1);
+
 		wmb();
 	}
 }
@@ -1837,12 +1857,27 @@ static void dp_catalog_ctrl_get_interrupt(struct dp_catalog_ctrl *ctrl)
 	ack |= DP_INTR_MASK2;
 	dp_write(DP_INTR_STATUS2, ack);
 
+	ctrl->isr3 = dp_read(DP_INTR_STATUS3);
+	ctrl->isr3 &= ~DP_INTR_MASK3;
+	ack = ctrl->isr3 & DP_INTERRUPT_STATUS3;
+	ack <<= 1;
+	ack |= DP_INTR_MASK3;
+	dp_write(DP_INTR_STATUS3, ack);
+
 	ctrl->isr5 = dp_read(DP_INTR_STATUS5);
 	ctrl->isr5 &= ~DP_INTR_MASK5;
 	ack = ctrl->isr5 & DP_INTERRUPT_STATUS5;
 	ack <<= 1;
 	ack |= DP_INTR_MASK5;
 	dp_write(DP_INTR_STATUS5, ack);
+
+	ctrl->isr6 = dp_read(DP_INTR_STATUS6);
+	ctrl->isr6 &= ~DP_INTR_MASK6;
+	ack = ctrl->isr6 & DP_INTERRUPT_STATUS6;
+	ack <<= 1;
+	ack |= DP_INTR_MASK6;
+	dp_write(DP_INTR_STATUS6, ack);
+
 }
 
 static void dp_catalog_ctrl_phy_reset(struct dp_catalog_ctrl *ctrl)

msm/dp/dp_catalog.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -33,10 +33,23 @@
 #define DP_INTR_IDLE_PATTERN_SENT	BIT(3)
 #define DP_INTR_FRAME_END		BIT(6)
 #define DP_INTR_CRC_UPDATED		BIT(9)
+#define DP_INTR_SST_FIFO_UNDERFLOW	BIT(28)
 
 #define DP_INTR_MST_DP0_VCPF_SENT	BIT(0)
 #define DP_INTR_MST_DP1_VCPF_SENT	BIT(3)
 
+#define DP_INTR_SST_ML_FIFO_OVERFLOW	BIT(12)
+#define DP_INTR_MST0_ML_FIFO_OVERFLOW	BIT(15)
+#define DP_INTR_MST1_ML_FIFO_OVERFLOW	BIT(18)
+#define DP_INTR_DP1_FRAME_END		BIT(21)
+#define DP_INTR_SDP0_COLLISION		BIT(24)
+#define DP_INTR_SDP1_COLLISION		BIT(27)
+
+#define DP_INTR_DP0_BACKPRESSURE_ERROR	(BIT(1) | BIT(0))
+#define DP_INTR_DP1_BACKPRESSURE_ERROR	(BIT(5) | BIT(4))
+#define DP_INTR_SST_BS_LATE	BIT(8)
+
+
 #define DP_MAX_TIME_SLOTS	64
 
 /* stream id */
@@ -76,7 +89,9 @@ struct dp_catalog_aux {
 
 struct dp_catalog_ctrl {
 	u32 isr;
+	u32 isr3;
 	u32 isr5;
+	u32 isr6;
 
 	void (*state_ctrl)(struct dp_catalog_ctrl *ctrl, u32 state);
 	void (*config_ctrl)(struct dp_catalog_ctrl *ctrl, u8 ln_cnt);

msm/dp/dp_ctrl.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2012-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -1484,14 +1484,14 @@ static void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
 {
 	struct dp_ctrl_private *ctrl;
 
-	SDE_EVT32_EXTERNAL(SDE_EVTLOG_FUNC_ENTRY);
 	if (!dp_ctrl)
 		return;
 
 	ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
 
 	ctrl->catalog->get_interrupt(ctrl->catalog);
-	SDE_EVT32_EXTERNAL(ctrl->catalog->isr);
+	SDE_EVT32_EXTERNAL(ctrl->catalog->isr, ctrl->catalog->isr3, ctrl->catalog->isr5,
+			ctrl->catalog->isr6);
 
 	if (ctrl->catalog->isr & DP_CTRL_INTR_READY_FOR_VIDEO)
 		dp_ctrl_video_ready(ctrl);
@@ -1504,7 +1504,6 @@ static void dp_ctrl_isr(struct dp_ctrl *dp_ctrl)
 
 	if (ctrl->catalog->isr5 & DP_CTRL_INTR_MST_DP1_VCPF_SENT)
 		dp_ctrl_idle_patterns_sent(ctrl);
-	SDE_EVT32_EXTERNAL(SDE_EVTLOG_FUNC_EXIT);
 }
 
 void dp_ctrl_set_sim_mode(struct dp_ctrl *dp_ctrl, bool en)

msm/dp/dp_reg.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
- * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
  */
 
@@ -17,6 +17,7 @@
 #define DP_INTR_STATUS2				(0x00000024)
 #define DP_INTR_STATUS3				(0x00000028)
 #define DP_INTR_STATUS5				(0x00000034)
+#define DP_INTR_STATUS6				(0x00000038)
 
 #define DP_DP_HPD_CTRL				(0x00000000)
 #define DP_DP_HPD_INT_STATUS			(0x00000004)