qcacmn: Do msi init first and write to PRODUCER_INT_SETUP
PRODUCER_INT_SETUP register write was missed. MSI init should be done before configuring interrupt triggers. Change-Id: Idf356b889ba2aa9d1269e0c07dcad02cc9c63a6a CRs-Fixed: 1089874
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@@ -589,6 +589,22 @@ static inline void hal_srng_src_hw_init(struct hal_soc *hal,
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uint32_t reg_val = 0;
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uint32_t reg_val = 0;
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uint64_t tp_addr = 0;
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uint64_t tp_addr = 0;
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HIF_INFO("%s: hw_init srng %d", __func__, srng->ring_id);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB,
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srng->msi_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR),
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(uint64_t)(srng->msi_addr) >> 32) |
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SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
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MSI1_ENABLE), 1);
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
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}
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HIF_INFO("%s: hw_init srng (msi_end) %d", __func__, srng->ring_id);
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SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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SRNG_SRC_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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reg_val = SRNG_SM(SRNG_SRC_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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@@ -639,17 +655,6 @@ static inline void hal_srng_src_hw_init(struct hal_soc *hal,
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SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val);
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SRNG_SRC_REG_WRITE(srng, CONSUMER_INT_SETUP_IX1, reg_val);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_LSB,
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srng->msi_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB, ADDR),
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(uint64_t)(srng->msi_addr) >> 32) |
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SRNG_SM(SRNG_SRC_FLD(MSI1_BASE_MSB,
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MSI1_ENABLE), 1);
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SRNG_SRC_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_SRC_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
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}
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tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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tp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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((unsigned long)(srng->u.src_ring.tp_addr) -
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((unsigned long)(srng->u.src_ring.tp_addr) -
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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@@ -674,6 +679,21 @@ static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
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uint32_t reg_val = 0;
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uint32_t reg_val = 0;
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uint64_t hp_addr = 0;
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uint64_t hp_addr = 0;
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HIF_INFO("%s: hw_init srng %d", __func__, srng->ring_id);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
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SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB,
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srng->msi_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR),
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(uint64_t)(srng->msi_addr) >> 32) |
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SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
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MSI1_ENABLE), 1);
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SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
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}
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HIF_INFO("%s: hw_init srng msi end %d", __func__, srng->ring_id);
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SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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SRNG_DST_REG_WRITE(srng, BASE_LSB, srng->ring_base_paddr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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reg_val = SRNG_SM(SRNG_DST_FLD(BASE_MSB, RING_BASE_ADDR_MSB),
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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((uint64_t)(srng->ring_base_paddr) >> 32)) |
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@@ -712,19 +732,8 @@ static inline void hal_srng_dst_hw_init(struct hal_soc *hal,
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srng->intr_batch_cntr_thres_entries *
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srng->intr_batch_cntr_thres_entries *
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srng->entry_size);
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srng->entry_size);
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}
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}
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SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val);
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SRNG_DST_REG_WRITE(srng, PRODUCER_INT_SETUP, reg_val);
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if (srng->flags & HAL_SRNG_MSI_INTR) {
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SRNG_DST_REG_WRITE(srng, MSI1_BASE_LSB,
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srng->msi_addr & 0xffffffff);
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reg_val = SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB, ADDR),
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(uint64_t)(srng->msi_addr) >> 32) |
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SRNG_SM(SRNG_DST_FLD(MSI1_BASE_MSB,
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MSI1_ENABLE), 1);
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SRNG_DST_REG_WRITE(srng, MSI1_BASE_MSB, reg_val);
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SRNG_DST_REG_WRITE(srng, MSI1_DATA, srng->msi_data);
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}
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hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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hp_addr = (uint64_t)(hal->shadow_rdptr_mem_paddr +
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((unsigned long)(srng->u.dst_ring.hp_addr) -
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((unsigned long)(srng->u.dst_ring.hp_addr) -
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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(unsigned long)(hal->shadow_rdptr_mem_vaddr)));
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