msm: camera: isp: Fixing CSID halt sequence

PP overflow, Pdaf violation issues were observed after
flush in stop sequence on crow. This change fixes csid
halt sequence for any usecase by correctly setting halt
mode and cmd while enabling and disabling ipp/ppp paths.
Here we are setting halt cmd to resume at frame boundary
at start and halt at frame boundary at stop.

CRs-Fixed: 3628412
Change-Id: I804e8077676e461376b49446ffbf74d0fb8c092e
Signed-off-by: Yash Upadhyay <[email protected]>

drivers/cam_isp/isp_hw_mgr/cam_tfe_hw_mgr.c

@@ -2442,6 +2442,10 @@ static int cam_tfe_mgr_acquire_hw(void *hw_mgr_priv, void *acquire_hw_args)
 	if (is_shdr_en && !is_shdr_master)
 		tfe_ctx->is_shdr_slave = true;
 
+	CAM_INFO(CAM_ISP, "ctx %d TFE index %d is_dual=%d is_shdr=%d shdr_master=%d",
+		tfe_ctx->ctx_index, tfe_ctx->base[0].idx, tfe_ctx->is_dual,
+		is_shdr_en, is_shdr_master);
+
 	for (i = 0; i < acquire_hw_info->num_inputs; i++) {
 		cam_tfe_hw_mgr_preprocess_port(tfe_ctx, &in_port[i], &num_pix_port_per_in,
 			&num_rdi_port_per_in, &num_pd_port_per_in, &pdaf_enable, &lcr_enable);
@@ -3494,8 +3498,6 @@ static int cam_tfe_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args)
 		cam_tfe_mgr_csid_change_halt_mode(ctx,
 			CAM_TFE_CSID_HALT_MODE_INTERNAL);
 
-	CAM_DBG(CAM_ISP, "Stopping master CSID idx %d", master_base_idx);
-
 	/* Stop the master CSID path first */
 	cam_tfe_mgr_csid_stop_hw(ctx, &ctx->res_list_tfe_csid,
 		master_base_idx, csid_halt_type);

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.c

@@ -997,6 +997,8 @@ static int cam_tfe_csid_path_reserve(struct cam_tfe_csid_hw *csid_hw,
 	path_data->bayer_bin = reserve->in_port->bayer_bin;
 	path_data->qcfa_bin = reserve->in_port->qcfa_bin;
 	path_data->crop_enable = reserve->crop_enable;
+	path_data->is_shdr_master = reserve->in_port->is_shdr_master;
+	path_data->is_shdr = reserve->in_port->shdr_en;
 
 	csid_hw->event_cb = reserve->event_cb;
 	csid_hw->event_cb_priv = reserve->event_cb_prv;
@@ -1667,33 +1669,31 @@ static int cam_tfe_csid_enable_pxl_path(
 
 	CAM_DBG(CAM_ISP, "Enable IPP path");
 
-	/* Set master or slave path */
-	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)
-		/* Set halt mode as master */
-		val = (TFE_CSID_HALT_MODE_MASTER  <<
-			pxl_reg->halt_mode_shift) |
-			(pxl_reg->halt_master_sel_master_val <<
-			pxl_reg->halt_master_sel_shift);
-	else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)
-		/* Set halt mode as slave and set master idx */
-		val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift);
+	if ((path_data->is_shdr && path_data->is_shdr_master) ||
+		(path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER))
+		/* Set halt mode for master */
+		val = (TFE_CSID_HALT_MODE_MASTER << pxl_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_NONE << pxl_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift);
+	else if ((path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) ||
+			(path_data->is_shdr))
+		/* Set halt mode for slave */
+		val = (TFE_CSID_HALT_MODE_SLAVE << pxl_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_EXTERNAL << pxl_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift);
 	else
-		/* Default is internal halt mode */
-		val = 1 << pxl_reg->halt_master_sel_shift;
-
-	/*
-	 * Resume at frame boundary if Master or No Sync.
-	 * Slave will get resume command from Master.
-	 */
-	if ((path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER ||
-		path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) && !path_data->init_frame_drop)
-		val |= CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY;
+		/* Set halt mode for default */
+		val = (TFE_CSID_HALT_MODE_INTERNAL << pxl_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_NONE << pxl_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift);
 
 	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
 		pxl_reg->csid_pxl_ctrl_addr);
 
-	CAM_DBG(CAM_ISP, "CSID:%d IPP Ctrl val: 0x%x",
-		csid_hw->hw_intf->hw_idx, val);
+	CAM_DBG(CAM_ISP, "CSID:%d sync_mode=%d IPP_Ctrl:0x%x is_shdr=%d shdr_master=%d",
+		csid_hw->hw_intf->hw_idx, path_data->sync_mode,
+		cam_io_r_mb(soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_ctrl_addr),
+		path_data->is_shdr, path_data->is_shdr_master);
 
 	/* Enable the required pxl path interrupts */
 	val = TFE_CSID_PATH_INFO_RST_DONE |
@@ -1769,7 +1769,8 @@ static int cam_tfe_csid_change_pxl_halt_mode(
 static int cam_tfe_csid_disable_pxl_path(
 	struct cam_tfe_csid_hw          *csid_hw,
 	struct cam_isp_resource_node    *res,
-	enum cam_tfe_csid_halt_cmd       stop_cmd)
+	enum cam_tfe_csid_halt_cmd       stop_cmd,
+	bool csid_with_ppp_en)
 {
 	int rc = 0;
 	uint32_t val = 0;
@@ -1823,32 +1824,46 @@ static int cam_tfe_csid_disable_pxl_path(
 	cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
 		pxl_reg->csid_pxl_irq_mask_addr);
 
-	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER ||
-		path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) {
-		/* configure Halt */
-		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-		pxl_reg->csid_pxl_ctrl_addr);
-		val &= ~0x3;
-		val |= stop_cmd;
-		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
-			pxl_reg->csid_pxl_ctrl_addr);
-	}
-
-	if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE &&
-		stop_cmd == CAM_TFE_CSID_HALT_IMMEDIATELY) {
-		/* configure Halt for slave */
-		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-			pxl_reg->csid_pxl_ctrl_addr);
-		val &= ~0xF;
-		val |= stop_cmd;
-		val |= (TFE_CSID_HALT_MODE_MASTER << 2);
-		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
-			pxl_reg->csid_pxl_ctrl_addr);
-	}
-
 	path_data->init_frame_drop = 0;
 	path_data->res_sof_cnt     = 0;
 
+	if (((path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER) ||
+		(path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)) && !csid_with_ppp_en)
+		/* Set halt mode for dual master/slave without pdaf */
+		val = (TFE_CSID_HALT_MODE_GLOBAL << pxl_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_EXTERNAL << pxl_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_HALT_IMMEDIATELY << pxl_reg->halt_cmd_shift);
+	else if ((path_data->is_shdr && path_data->is_shdr_master) ||
+		(path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER))
+		/* Set halt mode for shdr/dual master */
+		val = (TFE_CSID_HALT_MODE_MASTER << pxl_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_NONE << pxl_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift);
+	else if ((path_data->is_shdr && !path_data->is_shdr_master) ||
+		(path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)) {
+		/* Set halt mode for shdr/dual slave */
+		CAM_DBG(CAM_ISP, "skip programming halt mode for slave in %s case",
+			(path_data->is_shdr) ? "SHDR" : "Dual TFE");
+		goto end;
+	} else if (csid_with_ppp_en)
+		/* Set halt mode for single tfe + pdaf */
+		val = (TFE_CSID_HALT_MODE_INTERNAL << pxl_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_NONE << pxl_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift);
+	else
+		/* Set halt mode for default */
+		val = (TFE_CSID_HALT_MODE_GLOBAL << pxl_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_EXTERNAL << pxl_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_HALT_AT_FRAME_BOUNDARY << pxl_reg->halt_cmd_shift);
+
+	cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
+		pxl_reg->csid_pxl_ctrl_addr);
+
+	CAM_DBG(CAM_ISP, "halt CSID:%d sync_mode:%d res_id:%d IPP path pxl_ctrl=0x%x",
+		csid_hw->hw_intf->hw_idx, path_data->sync_mode, res->res_id,
+		cam_io_r_mb(soc_info->reg_map[0].mem_base + pxl_reg->csid_pxl_ctrl_addr));
+
+end:
 	return rc;
 }
 
@@ -1883,34 +1898,29 @@ static int cam_tfe_csid_enable_ppp_path(
 
 	CAM_DBG(CAM_ISP, "CSID:%d Enable PPP path", csid_hw->hw_intf->hw_idx);
 
-	/* Set master or slave path */
-	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER)
-		/* Set halt mode as master */
-		val = (TFE_CSID_HALT_MODE_SLAVE  << ppp_reg->halt_mode_shift) |
-			(ppp_reg->halt_master_sel_master_val <<
-			ppp_reg->halt_master_sel_shift);
-	else if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE)
-		/* Set halt mode as slave and set master idx */
-		val = (TFE_CSID_HALT_MODE_SLAVE  << ppp_reg->halt_mode_shift) |
-			(ppp_reg->halt_master_sel_slave_val <<
-			ppp_reg->halt_master_sel_shift);
+	if ((path_data->is_shdr && path_data->is_shdr_master) ||
+		(path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER))
+		/* Set halt mode for master shdr/dual */
+		val = (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_INTERNAL1 << ppp_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << ppp_reg->halt_cmd_shift);
+	else if ((path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE) ||
+			(path_data->is_shdr))
+		/* Set halt mode for slave shdr/dual*/
+		val = (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_INTERNAL2 << ppp_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << ppp_reg->halt_cmd_shift);
 	else
-		/* Default is internal halt mode */
-		val = (TFE_CSID_HALT_MODE_SLAVE  << ppp_reg->halt_mode_shift) |
-			(ppp_reg->halt_master_sel_master_val <<
-			ppp_reg->halt_master_sel_shift);
-
-	/*
-	 * Resume at frame boundary if Master or No Sync.
-	 * Slave will get resume command from Master.
-	 */
-	if ((path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER ||
-		path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) && !path_data->init_frame_drop)
-		val |= CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY;
+		/* Set halt mode for default */
+		val = (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift) |
+			(TFE_CSID_HALT_CMD_SOURCE_INTERNAL1 << ppp_reg->halt_master_sel_shift) |
+			(CAM_TFE_CSID_RESUME_AT_FRAME_BOUNDARY << ppp_reg->halt_cmd_shift);
 
 	cam_io_w_mb(val, soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr);
 
-	CAM_DBG(CAM_ISP, "CSID:%d PPP Ctrl val: 0x%x", csid_hw->hw_intf->hw_idx, val);
+	CAM_DBG(CAM_ISP, "CSID:%d sync_mode:%d PPP Ctrl val: 0x%x",
+		csid_hw->hw_intf->hw_idx, path_data->sync_mode,
+		cam_io_r_mb(soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr));
 
 	/* Enable the required ppp path interrupts */
 	val = TFE_CSID_PATH_INFO_RST_DONE | TFE_CSID_PATH_ERROR_FIFO_OVERFLOW |
@@ -1939,7 +1949,6 @@ static int cam_tfe_csid_disable_ppp_path(
 	enum cam_tfe_csid_halt_cmd       stop_cmd)
 {
 	int rc = 0;
-	uint32_t val = 0;
 	const struct cam_tfe_csid_reg_offset       *csid_reg;
 	struct cam_hw_soc_info                     *soc_info;
 	struct cam_tfe_csid_path_cfg               *path_data;
@@ -1989,33 +1998,12 @@ static int cam_tfe_csid_disable_ppp_path(
 	cam_io_w_mb(0, soc_info->reg_map[0].mem_base +
 		ppp_reg->csid_pxl_irq_mask_addr);
 
-	if (path_data->sync_mode == CAM_ISP_HW_SYNC_MASTER ||
-		path_data->sync_mode == CAM_ISP_HW_SYNC_NONE) {
-		/* configure Halt */
-		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-		ppp_reg->csid_pxl_ctrl_addr);
-		val &= ~0x3F;
-		val |= (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift);
-		val |= (ppp_reg->halt_master_sel_master_val <<
-			ppp_reg->halt_master_sel_shift);
-		val |= stop_cmd;
-		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
-			ppp_reg->csid_pxl_ctrl_addr);
-	}
+	CAM_DBG(CAM_ISP, "CSID:%d res_id:%d Skip prgramming halt mode for PPP path",
+		csid_hw->hw_intf->hw_idx, res->res_id);
 
-	if (path_data->sync_mode == CAM_ISP_HW_SYNC_SLAVE &&
-		stop_cmd == CAM_TFE_CSID_HALT_IMMEDIATELY) {
-		/* configure Halt for slave */
-		val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
-			ppp_reg->csid_pxl_ctrl_addr);
-		val &= ~0x3F;
-		val |= (TFE_CSID_HALT_MODE_SLAVE << ppp_reg->halt_mode_shift);
-		val |= (ppp_reg->halt_master_sel_slave_val <<
-			ppp_reg->halt_master_sel_shift);
-		val |= stop_cmd;
-		cam_io_w_mb(val, soc_info->reg_map[0].mem_base +
-			ppp_reg->csid_pxl_ctrl_addr);
-	}
+	CAM_DBG(CAM_ISP, "CSID:%d sync_mode:%d res_id:%d PPP path halt_ctrl_reg=0x%x",
+		csid_hw->hw_intf->hw_idx, path_data->sync_mode, res->res_id,
+		cam_io_r_mb(soc_info->reg_map[0].mem_base + ppp_reg->csid_pxl_ctrl_addr));
 
 	path_data->init_frame_drop = 0;
 	path_data->res_sof_cnt     = 0;
@@ -2319,6 +2307,9 @@ static int cam_tfe_csid_poll_stop_status(
 	uint32_t csid_status_addr = 0, val = 0, res_id = 0;
 	const struct cam_tfe_csid_reg_offset       *csid_reg;
 	struct cam_hw_soc_info                     *soc_info;
+	uint32_t csid_ctrl_reg = 0;
+	uint32_t csid_cfg0_reg = 0;
+	uint32_t csid_cfg1_reg = 0;
 
 	csid_reg = csid_hw->csid_info->csid_reg;
 	soc_info = &csid_hw->hw_info->soc_info;
@@ -2332,6 +2323,10 @@ static int cam_tfe_csid_poll_stop_status(
 			csid_status_addr =
 			csid_reg->ipp_reg->csid_pxl_status_addr;
 
+			csid_ctrl_reg = csid_reg->ipp_reg->csid_pxl_ctrl_addr;
+			csid_cfg0_reg = csid_reg->ipp_reg->csid_pxl_cfg0_addr;
+			csid_cfg1_reg = csid_reg->ipp_reg->csid_pxl_cfg1_addr;
+
 			if (csid_hw->ipp_res.res_state !=
 				CAM_ISP_RESOURCE_STATE_STREAMING)
 				continue;
@@ -2339,6 +2334,9 @@ static int cam_tfe_csid_poll_stop_status(
 		} else if (res_id == CAM_TFE_CSID_PATH_RES_PPP) {
 			csid_status_addr =
 			csid_reg->ppp_reg->csid_pxl_status_addr;
+			csid_ctrl_reg = csid_reg->ppp_reg->csid_pxl_ctrl_addr;
+			csid_cfg0_reg = csid_reg->ppp_reg->csid_pxl_cfg0_addr;
+			csid_cfg1_reg = csid_reg->ppp_reg->csid_pxl_cfg1_addr;
 
 			if (csid_hw->ppp_res.res_state !=
 				CAM_ISP_RESOURCE_STATE_STREAMING)
@@ -2347,6 +2345,9 @@ static int cam_tfe_csid_poll_stop_status(
 		} else {
 			csid_status_addr =
 				csid_reg->rdi_reg[res_id]->csid_rdi_status_addr;
+			csid_ctrl_reg = csid_reg->rdi_reg[res_id]->csid_rdi_ctrl_addr;
+			csid_cfg0_reg = csid_reg->rdi_reg[res_id]->csid_rdi_cfg0_addr;
+			csid_cfg1_reg = csid_reg->rdi_reg[res_id]->csid_rdi_cfg1_addr;
 
 			if (csid_hw->rdi_res[res_id].res_state !=
 				CAM_ISP_RESOURCE_STATE_STREAMING)
@@ -2367,6 +2368,13 @@ static int cam_tfe_csid_poll_stop_status(
 		if (rc < 0) {
 			CAM_ERR(CAM_ISP, "CSID:%d res:%d halt failed rc %d",
 				csid_hw->hw_intf->hw_idx, res_id, rc);
+
+			CAM_ERR(CAM_ISP, "CSID:%d status:0x%x ctrl_reg:0x%x cfg0:0x%x cfg1:0x%x",
+				csid_hw->hw_intf->hw_idx,
+				cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_status_addr),
+				cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_ctrl_reg),
+				cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_cfg0_reg),
+				cam_io_r_mb(soc_info->reg_map[0].mem_base + csid_cfg1_reg));
 			rc = -ETIMEDOUT;
 			break;
 		}
@@ -3057,6 +3065,7 @@ static int cam_tfe_csid_stop(void *hw_priv,
 	struct cam_tfe_csid_hw_stop_args     *csid_stop;
 	uint32_t  i;
 	uint32_t res_mask = 0;
+	bool csid_with_ppp_en = false;
 
 	if (!hw_priv || !stop_args ||
 		(arg_size != sizeof(struct cam_tfe_csid_hw_stop_args))) {
@@ -3072,9 +3081,13 @@ static int cam_tfe_csid_stop(void *hw_priv,
 
 	csid_hw_info = (struct cam_hw_info  *)hw_priv;
 	csid_hw = (struct cam_tfe_csid_hw   *)csid_hw_info->core_info;
-	CAM_DBG(CAM_ISP, "CSID:%d num_res %d",
-		csid_hw->hw_intf->hw_idx,
-		csid_stop->num_res);
+
+	if (csid_hw->ppp_res.res_state == CAM_ISP_RESOURCE_STATE_STREAMING)
+		csid_with_ppp_en = true;
+
+	CAM_DBG(CAM_ISP, "CSID:%d num_res %d csid_with_ppp_en:%d",
+		csid_hw->hw_intf->hw_idx, csid_stop->num_res,
+		csid_with_ppp_en);
 
 	/* Stop the resource first */
 	for (i = 0; i < csid_stop->num_res; i++) {
@@ -3087,7 +3100,7 @@ static int cam_tfe_csid_stop(void *hw_priv,
 			res_mask |= (1 << res->res_id);
 			if (res->res_id == CAM_TFE_CSID_PATH_RES_IPP)
 				rc = cam_tfe_csid_disable_pxl_path(csid_hw,
-					res, csid_stop->stop_cmd);
+					res, csid_stop->stop_cmd, csid_with_ppp_en);
 			else if (res->res_id == CAM_TFE_CSID_PATH_RES_PPP)
 				rc = cam_tfe_csid_disable_ppp_path(csid_hw,
 					res, csid_stop->stop_cmd);

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_csid_hw/cam_tfe_csid_core.h

@@ -160,6 +160,7 @@ struct cam_tfe_csid_pxl_reg_offset {
 	uint32_t early_eof_en_shift_val;
 	uint32_t halt_master_sel_shift;
 	uint32_t halt_mode_shift;
+	uint32_t halt_cmd_shift;
 	uint32_t halt_master_sel_master_val;
 	uint32_t halt_master_sel_slave_val;
 	uint32_t binning_supported;
@@ -424,7 +425,8 @@ struct cam_tfe_csid_cid_data {
  *                      one more frame than pix.
  * @res_sof_cnt         path resource sof count value. it used for initial
  *                      frame drop
- *
+ * @is_shdr_master      flag to indicate path to be shdr master
+ * @is_shdr             flag to indicate if shdr mode is enabled
  */
 struct cam_tfe_csid_path_cfg {
 	struct vc_dt_data               vc_dt[CAM_ISP_TFE_VC_DT_CFG];
@@ -452,6 +454,8 @@ struct cam_tfe_csid_path_cfg {
 	uint32_t                        usage_type;
 	uint32_t                        init_frame_drop;
 	uint32_t                        res_sof_cnt;
+	bool                            is_shdr_master;
+	bool                            is_shdr;
 };
 
 /**

drivers/cam_isp/isp_hw_mgr/isp_hw/tfe_hw/cam_tfe_core.c

@@ -2478,8 +2478,8 @@ static int cam_tfe_camif_resource_start(
 	cam_io_w_mb(val, rsrc_data->mem_base +
 		rsrc_data->common_reg->core_cfg_0);
 
-	CAM_DBG(CAM_ISP, "TFE:%d core_cfg 0 val:0x%x", core_info->core_index,
-		val);
+	CAM_DBG(CAM_ISP, "TFE:%d core_cfg_0 val:0x%x", core_info->core_index,
+		cam_io_r_mb(rsrc_data->mem_base + rsrc_data->common_reg->core_cfg_0));
 
 	if (cam_cpas_get_cpas_hw_version(&camera_hw_version))
 		CAM_ERR(CAM_ISP, "Failed to get HW version");