asoc: dsp: prm: Add support to send reg info to PRM for UPD

Send codec register's and its value to enable/disable EAR PA
when codec duty cycling is enabled.

Change-Id: I6ce7183bda3dd2d02829d280d27e5a5573e3efcc
signed-off-by: sarath varma ganapahiraju <[email protected]>

dsp/audio_prm.c

@@ -296,6 +296,97 @@ static int audio_prm_set_lpass_clk_cfg_rel(struct clk_cfg *cfg)
         return ret;
 }
 
+/**
+ * audio_prm_set_cdc_earpa_duty_cycling_req() - send codec reg values
+ * for codec duty cycling.
+ *
+ * Return: 0 if reg passing is success.
+ */
+int audio_prm_set_cdc_earpa_duty_cycling_req(struct prm_earpa_hw_intf_config *earpa_config,
+								uint32_t enable)
+{
+	struct gpr_pkt *pkt;
+	prm_cmd_request_cdc_duty_cycling_t prm_rsc_request_reg_info;
+	int ret = 0;
+	uint32_t size;
+
+	size = GPR_HDR_SIZE + sizeof(prm_cmd_request_cdc_duty_cycling_t);
+	pkt = kzalloc(size,  GFP_KERNEL);
+	if (!pkt)
+		return -ENOMEM;
+	pkt->hdr.header = GPR_SET_FIELD(GPR_PKT_VERSION, GPR_PKT_VER) |
+			GPR_SET_FIELD(GPR_PKT_HEADER_SIZE, GPR_PKT_HEADER_WORD_SIZE_V) |
+			GPR_SET_FIELD(GPR_PKT_PACKET_SIZE, size);
+
+	pkt->hdr.src_port = GPR_SVC_ASM;
+	pkt->hdr.dst_port = PRM_MODULE_INSTANCE_ID;
+	pkt->hdr.dst_domain_id = GPR_IDS_DOMAIN_ID_ADSP_V;
+	pkt->hdr.src_domain_id = GPR_IDS_DOMAIN_ID_APPS_V;
+	pkt->hdr.token = 0;
+	if (enable)
+		pkt->hdr.opcode = PRM_CMD_REQUEST_HW_RSC;
+	else
+		pkt->hdr.opcode = PRM_CMD_RELEASE_HW_RSC;
+
+	memset(&prm_rsc_request_reg_info, 0, sizeof(prm_cmd_request_cdc_duty_cycling_t));
+	prm_rsc_request_reg_info.payload_header.payload_address_lsw = 0;
+	prm_rsc_request_reg_info.payload_header.payload_address_msw = 0;
+	prm_rsc_request_reg_info.payload_header.mem_map_handle = 0;
+	prm_rsc_request_reg_info.payload_header.payload_size =
+			sizeof(prm_cmd_request_cdc_duty_cycling_t) - sizeof(apm_cmd_header_t);
+
+	/* Populate the param payload */
+	prm_rsc_request_reg_info.module_payload_0.module_instance_id =
+							PRM_MODULE_INSTANCE_ID;
+	prm_rsc_request_reg_info.module_payload_0.error_code = 0;
+	prm_rsc_request_reg_info.module_payload_0.param_id =
+						PARAM_ID_RSC_HW_CODEC_REG_INFO;
+	prm_rsc_request_reg_info.module_payload_0.param_size =
+			sizeof(prm_cmd_request_cdc_duty_cycling_t) -
+			sizeof(apm_cmd_header_t) - sizeof(apm_module_param_data_t);
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.num_reg_info_t = MAX_EARPA_REG;
+	/* Setting up DIGITAL Mute register value */
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].hw_codec_reg_id =
+							HW_CODEC_DIG_REG_ID_MUTE_CTRL;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].hw_codec_reg_addr_msw = 0;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].hw_codec_reg_addr_lsw =
+			earpa_config->ear_pa_hw_reg_cfg.lpass_cdc_rx0_rx_path_ctl_phy_addr;
+
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].num_ops =
+							MAX_EARPA_CDC_DUTY_CYC_OPERATION;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].hw_codec_op[0].hw_codec_op_id =
+								HW_CODEC_OP_DIG_MUTE_ENABLE;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].hw_codec_op[0].hw_codec_op_value =
+								DIG_MUTE_ENABLE;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].hw_codec_op[1].hw_codec_op_id =
+								HW_CODEC_OP_DIG_MUTE_DISABLE;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[0].hw_codec_op[1].hw_codec_op_value =
+								DIG_MUTE_DISABLE;
+	/* Setting up LPASS_PA_REG Values */
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].hw_codec_reg_id =
+						HW_CODEC_ANALOG_REG_ID_CMD_FIFO_WRITE;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].hw_codec_reg_addr_msw = 0;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].hw_codec_reg_addr_lsw =
+					earpa_config->ear_pa_hw_reg_cfg.lpass_wr_fifo_reg_phy_addr;
+
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].num_ops =
+							MAX_EARPA_CDC_DUTY_CYC_OPERATION;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].hw_codec_op[0].hw_codec_op_id =
+							HW_CODEC_OP_ANA_PGA_ENABLE;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].hw_codec_op[0].hw_codec_op_value =
+					earpa_config->ear_pa_pkd_cfg.ear_pa_enable_pkd_reg_addr;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].hw_codec_op[1].hw_codec_op_id =
+							HW_CODEC_OP_ANA_PGA_DISABLE;
+	prm_rsc_request_reg_info.hw_codec_reg_info_t.hw_codec_reg[1].hw_codec_op[1].hw_codec_op_value =
+					earpa_config->ear_pa_pkd_cfg.ear_pa_disable_pkd_reg_addr;
+
+	memcpy(&pkt->payload, &prm_rsc_request_reg_info, sizeof(prm_cmd_request_cdc_duty_cycling_t));
+	ret = prm_gpr_send_pkt(pkt, &g_prm.wait);
+	kfree(pkt);
+	return ret;
+}
+EXPORT_SYMBOL(audio_prm_set_cdc_earpa_duty_cycling_req);
+
 int audio_prm_set_lpass_clk_cfg (struct clk_cfg *clk, uint8_t enable)
 {
 	int ret = 0;

include/dsp/audio_prm.h

@@ -1,4 +1,4 @@
-/* Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+/* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -208,6 +208,64 @@ typedef struct prm_cmd_request_hw_core_t
 
 #define HW_RSC_ID_AUDIO_HW_CLK 0x0800102C
 
+#define MAX_EARPA_REG 2
+#define MAX_EARPA_CDC_DUTY_CYC_OPERATION 2
+
+typedef struct audio_hw_codec_op_info_t {
+	uint32_t hw_codec_op_id;
+	uint32_t hw_codec_op_value;
+} audio_hw_codec_op_info_t;
+
+typedef struct audio_hw_codec_reg_op_info_t {
+	uint32_t hw_codec_reg_id;
+	uint32_t hw_codec_reg_addr_msw;
+	uint32_t hw_codec_reg_addr_lsw;
+	uint32_t num_ops;
+	audio_hw_codec_op_info_t hw_codec_op[MAX_EARPA_REG];
+} audio_hw_codec_reg_op_info_t;
+
+typedef struct audio_hw_codec_reg_info_t {
+	uint32_t num_reg_info_t;
+	audio_hw_codec_reg_op_info_t hw_codec_reg[MAX_EARPA_REG];
+} audio_hw_codec_reg_info_t;
+
+typedef struct prm_cmd_request_cdc_duty_cycling_t {
+	apm_cmd_header_t payload_header;
+	apm_module_param_data_t module_payload_0;
+	audio_hw_codec_reg_info_t   hw_codec_reg_info_t;
+} prm_cmd_request_cdc_duty_cycling_t;
+
+/* earpa_register config */
+#define DIG_MUTE_ENABLE 0x34
+#define DIG_MUTE_DISABLE 0x24
+
+struct lpass_swr_ear_pa_dep_cfg_t {
+	uint32_t ear_pa_enable_pkd_reg_addr;
+	uint32_t ear_pa_disable_pkd_reg_addr;
+} __packed;
+
+struct lpass_swr_ear_pa_reg_cfg_t {
+	uint32_t lpass_cdc_rx0_rx_path_ctl_phy_addr;
+	uint32_t lpass_wr_fifo_reg_phy_addr;
+} __packed;
+
+struct prm_earpa_hw_intf_config {
+	struct lpass_swr_ear_pa_reg_cfg_t ear_pa_hw_reg_cfg;
+	struct lpass_swr_ear_pa_dep_cfg_t ear_pa_pkd_cfg;
+	uint32_t ear_pa_pkd_reg_addr;
+	const char  *backend_used;
+} __packed;
+
+#define PARAM_ID_RSC_HW_CODEC_REG_INFO 0x0800131B
+
+#define HW_CODEC_DIG_REG_ID_MUTE_CTRL 0x1
+#define HW_CODEC_OP_DIG_MUTE_ENABLE 0x1
+#define HW_CODEC_OP_DIG_MUTE_DISABLE 0x2
+
+#define HW_CODEC_ANALOG_REG_ID_CMD_FIFO_WRITE 0x2
+#define HW_CODEC_OP_ANA_PGA_ENABLE 0x3
+#define HW_CODEC_OP_ANA_PGA_DISABLE 0x4
+
 /* Supported OSR clock values */
 #define OSR_CLOCK_12_P288_MHZ	0xBB8000
 #define OSR_CLOCK_11_P2896_MHZ	0xAC4400
@@ -522,5 +580,7 @@ typedef struct prm_cmd_request_hw_core_t
 
 int audio_prm_set_lpass_clk_cfg(struct clk_cfg *cfg, uint8_t enable);
 int audio_prm_set_lpass_hw_core_req(struct clk_cfg *cfg, uint32_t hw_core_id, uint8_t enable);
+int audio_prm_set_cdc_earpa_duty_cycling_req(struct prm_earpa_hw_intf_config *earpa_config,
+									uint32_t enable);
 
 #endif