qcacmn: htt support for compact tlv feature
Adding htt support for compact tlv feature Change-Id: If45b5b32c4cef482cb6c54b5f2919b56384a8a93 CRs-Fixed: 3293927
This commit is contained in:

committed by
Madan Koyyalamudi

parent
e308a57a37
commit
6aef607629
@@ -753,6 +753,31 @@ qdf_size_t dp_get_soc_context_size_be(void)
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return sizeof(struct dp_soc_be);
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}
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#ifdef CONFIG_WORD_BASED_TLV
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/**
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* dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
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* @soc: Common DP soc handle
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* @htt_tlv_filter: Rx SRNG TLV and filter setting
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*
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* Return: none
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*/
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static inline void
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dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
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struct htt_rx_ring_tlv_filter *htt_tlv_filter)
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{
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htt_tlv_filter->rx_msdu_end_wmask =
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hal_rx_msdu_end_wmask_get(soc->hal_soc);
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htt_tlv_filter->rx_mpdu_start_wmask =
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hal_rx_mpdu_start_wmask_get(soc->hal_soc);
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}
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#else
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static inline void
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dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
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struct htt_rx_ring_tlv_filter *htt_tlv_filter)
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{
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}
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#endif
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#ifdef NO_RX_PKT_HDR_TLV
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/**
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* dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
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@@ -825,6 +850,8 @@ dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
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htt_tlv_filter.rx_msdu_end_offset =
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hal_rx_msdu_end_offset_get(soc->hal_soc);
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dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
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for (i = 0; i < MAX_PDEV_CNT; i++) {
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struct dp_pdev *pdev = soc->pdev_list[i];
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@@ -2000,6 +2027,7 @@ void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
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arch_ops->dp_rx_desc_cookie_2_va =
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dp_rx_desc_cookie_2_va_be;
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arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
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arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
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arch_ops->txrx_soc_attach = dp_soc_attach_be;
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arch_ops->txrx_soc_detach = dp_soc_detach_be;
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@@ -1531,6 +1531,52 @@ rel_da_peer:
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#endif /* WLAN_MLO_MULTI_CHIP */
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#endif /* INTRA_BSS_FWD_OFFLOAD */
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#if defined(QCA_MONITOR_2_0_SUPPORT) || defined(CONFIG_WORD_BASED_TLV)
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void dp_rx_word_mask_subscribe_be(struct dp_soc *soc,
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uint32_t *msg_word,
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void *rx_filter)
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{
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struct htt_rx_ring_tlv_filter *tlv_filter =
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(struct htt_rx_ring_tlv_filter *)rx_filter;
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if (!msg_word || !tlv_filter)
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return;
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/* if word mask is zero, FW will set the default values */
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if (!(tlv_filter->rx_mpdu_start_wmask > 0 &&
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tlv_filter->rx_msdu_end_wmask > 0)) {
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msg_word += 4;
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*msg_word = 0;
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goto config_mon;
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}
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HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET(*msg_word, 1);
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/* word 14 */
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msg_word += 3;
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*msg_word = 0;
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HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(
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*msg_word,
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tlv_filter->rx_mpdu_start_wmask);
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/* word 15 */
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msg_word++;
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*msg_word = 0;
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HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(
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*msg_word,
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tlv_filter->rx_msdu_end_wmask);
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config_mon:
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msg_word--;
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dp_mon_rx_wmask_subscribe(soc, msg_word, tlv_filter);
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}
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#else
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void dp_rx_word_mask_subscribe_be(struct dp_soc *soc,
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uint32_t *msg_word,
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void *rx_filter)
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{
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}
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#endif
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/*
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* dp_rx_intrabss_handle_nawds_be() - Forward mcbc intrabss pkts in nawds case
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* @soc: core txrx main context
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@@ -72,6 +72,10 @@ dp_rx_intrabss_handle_nawds_be(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
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qdf_nbuf_t nbuf_copy,
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struct cdp_tid_rx_stats *tid_stats);
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void dp_rx_word_mask_subscribe_be(struct dp_soc *soc,
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uint32_t *msg_word,
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void *rx_filter);
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uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
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hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
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uint32_t quota);
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@@ -1659,6 +1659,11 @@ int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id,
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*msg_word = 0;
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}
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soc->dp_soc->arch_ops.dp_rx_word_mask_subscribe(
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soc->dp_soc,
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msg_word,
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(void *)htt_tlv_filter);
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if (mon_drop_th > 0)
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HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(*msg_word,
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mon_drop_th);
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@@ -1668,9 +1673,8 @@ int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id,
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/* word 14*/
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msg_word += 3;
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*msg_word = 0;
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dp_mon_rx_wmask_subscribe(soc->dp_soc, msg_word, htt_tlv_filter);
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/* word 15*/
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msg_word++;
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#ifdef FW_SUPPORT_NOT_YET
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/* word 17*/
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@@ -675,10 +675,10 @@ struct htt_rx_ring_tlv_filter {
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u_int32_t phy_err_mask;
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u_int32_t phy_err_mask_cont;
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#endif
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#ifdef QCA_MONITOR_2_0_SUPPORT
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#if defined(QCA_MONITOR_2_0_SUPPORT) || defined(CONFIG_WORD_BASED_TLV)
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uint16_t rx_mpdu_start_wmask;
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uint16_t rx_mpdu_end_wmask;
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uint16_t rx_msdu_end_wmask;
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uint32_t rx_msdu_end_wmask;
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uint16_t rx_pkt_tlv_offset;
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uint16_t mgmt_dma_length:3,
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ctrl_dma_length:3,
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@@ -1908,6 +1908,11 @@ struct dp_arch_ops {
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qdf_nbuf_t nbuf_copy,
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struct cdp_tid_rx_stats *tid_stats);
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void (*dp_rx_word_mask_subscribe)(
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struct dp_soc *soc,
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uint32_t *msg_word,
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void *rx_filter);
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struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc,
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uint32_t cookie);
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uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc,
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@@ -515,6 +515,12 @@ dp_rx_intrabss_handle_nawds_li(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
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return false;
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}
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static void dp_rx_word_mask_subscribe_li(struct dp_soc *soc,
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uint32_t *msg_word,
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void *rx_filter)
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{
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}
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static struct dp_peer *dp_find_peer_by_destmac_li(struct dp_soc *soc,
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uint8_t *dest_mac,
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uint8_t vdev_id)
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@@ -609,6 +615,7 @@ void dp_initialize_arch_ops_li(struct dp_arch_ops *arch_ops)
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arch_ops->dp_rx_desc_cookie_2_va =
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dp_rx_desc_cookie_2_va_li;
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arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_li;
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arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_li;
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arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_li;
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arch_ops->dp_rx_peer_metadata_peer_id_get =
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dp_rx_peer_metadata_peer_id_get_li;
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@@ -179,11 +179,6 @@ void
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dp_rx_mon_word_mask_subscribe(uint32_t *msg_word,
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struct htt_rx_ring_tlv_filter *tlv_filter)
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{
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if (!msg_word || !tlv_filter)
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return;
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HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(*msg_word,
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tlv_filter->rx_mpdu_start_wmask);
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#ifdef QCA_MONITOR_2_0_SUPPORT_WAR /* Yet to get FW support */
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HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(*msg_word,
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@@ -191,9 +186,6 @@ dp_rx_mon_word_mask_subscribe(uint32_t *msg_word,
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#endif
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/* word 15 */
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msg_word++;
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*msg_word = 0;
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HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(*msg_word,
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tlv_filter->rx_msdu_end_wmask);
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/* word 16 */
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msg_word++;
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@@ -1767,6 +1767,31 @@ static inline uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
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}
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#endif
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#ifdef CONFIG_WORD_BASED_TLV
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#define MPDU_START_WMASK 0x074C
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#define MSDU_END_WMASK 0x13FC1
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/**
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* hal_rx_mpdu_start_wmask_get_be(): API to get the mpdu_start_tlv word mask
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*
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* return: Word mask for MPDU start tlv
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*/
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static inline uint32_t hal_rx_mpdu_start_wmask_get_be(void)
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{
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return MPDU_START_WMASK;
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}
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/**
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* hal_rx_msdu_end_wmask_get_be(): API to get the msdu_end_tlv word mask
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*
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* return: Word mask for MSDU end tlv
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*/
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static inline uint32_t hal_rx_msdu_end_wmask_get_be(void)
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{
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return MSDU_END_WMASK;
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}
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#endif
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#ifdef RECEIVE_OFFLOAD
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static inline int
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hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv,
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@@ -1015,6 +1015,8 @@ struct hal_hw_txrx_ops {
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uint32_t (*hal_rx_mpdu_start_offset_get)(void);
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uint32_t (*hal_rx_mpdu_end_offset_get)(void);
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uint32_t (*hal_rx_pkt_tlv_offset_get)(void);
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uint32_t (*hal_rx_msdu_end_wmask_get)(void);
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uint32_t (*hal_rx_mpdu_start_wmask_get)(void);
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void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst,
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uint32_t table_offset,
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uint8_t *rx_flow);
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@@ -2494,6 +2494,48 @@ uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
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return hal_soc->ops->hal_rx_mpdu_end_offset_get();
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}
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#ifdef CONFIG_WORD_BASED_TLV
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/**
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* hal_rx_mpdu_start_wmask_get(): Get the MPDU start word mask
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*
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* @hal_soc_hdl: HAL SOC handle
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* return: mpdu_start_tlv word mask value
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*/
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static inline
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uint32_t hal_rx_mpdu_start_wmask_get(hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return 0;
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}
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return hal_soc->ops->hal_rx_mpdu_start_wmask_get();
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}
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/**
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* hal_rx_msdu_end_wmask_get(): Get the MSDU END word mask
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*
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* @hal_soc_hdl: HAL SOC handle
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* return: msdu_end_tlv word mask value
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*/
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static inline
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uint32_t hal_rx_msdu_end_wmask_get(hal_soc_handle_t hal_soc_hdl)
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{
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struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
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if (!hal_soc || !hal_soc->ops) {
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hal_err("hal handle is NULL");
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QDF_BUG(0);
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return 0;
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}
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return hal_soc->ops->hal_rx_msdu_end_wmask_get();
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}
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#endif
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/**
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* hal_rx_attn_offset_get(): Get the ATTENTION offset from
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* rx_pkt_tlvs structure
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@@ -2093,6 +2093,12 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
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hal_tx_populate_bank_register_be;
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hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
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hal_tx_vdev_mcast_ctrl_set_be;
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#ifdef CONFIG_WORD_BASED_TLV
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hal_soc->ops->hal_rx_mpdu_start_wmask_get =
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hal_rx_mpdu_start_wmask_get_be;
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hal_soc->ops->hal_rx_msdu_end_wmask_get =
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hal_rx_msdu_end_wmask_get_be;
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#endif
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};
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/**
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