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@@ -753,6 +753,31 @@ qdf_size_t dp_get_soc_context_size_be(void)
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return sizeof(struct dp_soc_be);
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}
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+#ifdef CONFIG_WORD_BASED_TLV
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+/**
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+ * dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
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+ * @soc: Common DP soc handle
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+ * @htt_tlv_filter: Rx SRNG TLV and filter setting
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+ *
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+ * Return: none
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+ */
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+static inline void
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+dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
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+ struct htt_rx_ring_tlv_filter *htt_tlv_filter)
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+{
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+ htt_tlv_filter->rx_msdu_end_wmask =
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+ hal_rx_msdu_end_wmask_get(soc->hal_soc);
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+ htt_tlv_filter->rx_mpdu_start_wmask =
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+ hal_rx_mpdu_start_wmask_get(soc->hal_soc);
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+}
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+#else
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+static inline void
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+dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
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+ struct htt_rx_ring_tlv_filter *htt_tlv_filter)
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+{
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+}
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+#endif
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+
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#ifdef NO_RX_PKT_HDR_TLV
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/**
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* dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
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@@ -825,6 +850,8 @@ dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
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htt_tlv_filter.rx_msdu_end_offset =
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hal_rx_msdu_end_offset_get(soc->hal_soc);
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+ dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
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+
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for (i = 0; i < MAX_PDEV_CNT; i++) {
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struct dp_pdev *pdev = soc->pdev_list[i];
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@@ -2000,6 +2027,7 @@ void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
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arch_ops->dp_rx_desc_cookie_2_va =
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dp_rx_desc_cookie_2_va_be;
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arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
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+ arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
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arch_ops->txrx_soc_attach = dp_soc_attach_be;
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arch_ops->txrx_soc_detach = dp_soc_detach_be;
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