qcacmn: htt support for compact tlv feature

Adding htt support for compact tlv feature

Change-Id: If45b5b32c4cef482cb6c54b5f2919b56384a8a93
CRs-Fixed: 3293927
This commit is contained in:
Sai Rupesh Chevuru
2022-09-18 19:11:10 +05:30
committed by Madan Koyyalamudi
parent e308a57a37
commit 6aef607629
12 changed files with 174 additions and 13 deletions

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@@ -753,6 +753,31 @@ qdf_size_t dp_get_soc_context_size_be(void)
return sizeof(struct dp_soc_be); return sizeof(struct dp_soc_be);
} }
#ifdef CONFIG_WORD_BASED_TLV
/**
* dp_rxdma_ring_wmask_cfg_be() - Setup RXDMA ring word mask config
* @soc: Common DP soc handle
* @htt_tlv_filter: Rx SRNG TLV and filter setting
*
* Return: none
*/
static inline void
dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
struct htt_rx_ring_tlv_filter *htt_tlv_filter)
{
htt_tlv_filter->rx_msdu_end_wmask =
hal_rx_msdu_end_wmask_get(soc->hal_soc);
htt_tlv_filter->rx_mpdu_start_wmask =
hal_rx_mpdu_start_wmask_get(soc->hal_soc);
}
#else
static inline void
dp_rxdma_ring_wmask_cfg_be(struct dp_soc *soc,
struct htt_rx_ring_tlv_filter *htt_tlv_filter)
{
}
#endif
#ifdef NO_RX_PKT_HDR_TLV #ifdef NO_RX_PKT_HDR_TLV
/** /**
* dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config * dp_rxdma_ring_sel_cfg_be() - Setup RXDMA ring config
@@ -825,6 +850,8 @@ dp_rxdma_ring_sel_cfg_be(struct dp_soc *soc)
htt_tlv_filter.rx_msdu_end_offset = htt_tlv_filter.rx_msdu_end_offset =
hal_rx_msdu_end_offset_get(soc->hal_soc); hal_rx_msdu_end_offset_get(soc->hal_soc);
dp_rxdma_ring_wmask_cfg_be(soc, &htt_tlv_filter);
for (i = 0; i < MAX_PDEV_CNT; i++) { for (i = 0; i < MAX_PDEV_CNT; i++) {
struct dp_pdev *pdev = soc->pdev_list[i]; struct dp_pdev *pdev = soc->pdev_list[i];
@@ -2000,6 +2027,7 @@ void dp_initialize_arch_ops_be(struct dp_arch_ops *arch_ops)
arch_ops->dp_rx_desc_cookie_2_va = arch_ops->dp_rx_desc_cookie_2_va =
dp_rx_desc_cookie_2_va_be; dp_rx_desc_cookie_2_va_be;
arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be; arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_be;
arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_be;
arch_ops->txrx_soc_attach = dp_soc_attach_be; arch_ops->txrx_soc_attach = dp_soc_attach_be;
arch_ops->txrx_soc_detach = dp_soc_detach_be; arch_ops->txrx_soc_detach = dp_soc_detach_be;

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@@ -1531,6 +1531,52 @@ rel_da_peer:
#endif /* WLAN_MLO_MULTI_CHIP */ #endif /* WLAN_MLO_MULTI_CHIP */
#endif /* INTRA_BSS_FWD_OFFLOAD */ #endif /* INTRA_BSS_FWD_OFFLOAD */
#if defined(QCA_MONITOR_2_0_SUPPORT) || defined(CONFIG_WORD_BASED_TLV)
void dp_rx_word_mask_subscribe_be(struct dp_soc *soc,
uint32_t *msg_word,
void *rx_filter)
{
struct htt_rx_ring_tlv_filter *tlv_filter =
(struct htt_rx_ring_tlv_filter *)rx_filter;
if (!msg_word || !tlv_filter)
return;
/* if word mask is zero, FW will set the default values */
if (!(tlv_filter->rx_mpdu_start_wmask > 0 &&
tlv_filter->rx_msdu_end_wmask > 0)) {
msg_word += 4;
*msg_word = 0;
goto config_mon;
}
HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACTION_ENABLE_SET(*msg_word, 1);
/* word 14 */
msg_word += 3;
*msg_word = 0;
HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(
*msg_word,
tlv_filter->rx_mpdu_start_wmask);
/* word 15 */
msg_word++;
*msg_word = 0;
HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(
*msg_word,
tlv_filter->rx_msdu_end_wmask);
config_mon:
msg_word--;
dp_mon_rx_wmask_subscribe(soc, msg_word, tlv_filter);
}
#else
void dp_rx_word_mask_subscribe_be(struct dp_soc *soc,
uint32_t *msg_word,
void *rx_filter)
{
}
#endif
/* /*
* dp_rx_intrabss_handle_nawds_be() - Forward mcbc intrabss pkts in nawds case * dp_rx_intrabss_handle_nawds_be() - Forward mcbc intrabss pkts in nawds case
* @soc: core txrx main context * @soc: core txrx main context

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@@ -72,6 +72,10 @@ dp_rx_intrabss_handle_nawds_be(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
qdf_nbuf_t nbuf_copy, qdf_nbuf_t nbuf_copy,
struct cdp_tid_rx_stats *tid_stats); struct cdp_tid_rx_stats *tid_stats);
void dp_rx_word_mask_subscribe_be(struct dp_soc *soc,
uint32_t *msg_word,
void *rx_filter);
uint32_t dp_rx_process_be(struct dp_intr *int_ctx, uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num, hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
uint32_t quota); uint32_t quota);

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@@ -1659,6 +1659,11 @@ int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id,
*msg_word = 0; *msg_word = 0;
} }
soc->dp_soc->arch_ops.dp_rx_word_mask_subscribe(
soc->dp_soc,
msg_word,
(void *)htt_tlv_filter);
if (mon_drop_th > 0) if (mon_drop_th > 0)
HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(*msg_word, HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_SET(*msg_word,
mon_drop_th); mon_drop_th);
@@ -1668,9 +1673,8 @@ int htt_h2t_rx_ring_cfg(struct htt_soc *htt_soc, int pdev_id,
/* word 14*/ /* word 14*/
msg_word += 3; msg_word += 3;
*msg_word = 0; /* word 15*/
msg_word++;
dp_mon_rx_wmask_subscribe(soc->dp_soc, msg_word, htt_tlv_filter);
#ifdef FW_SUPPORT_NOT_YET #ifdef FW_SUPPORT_NOT_YET
/* word 17*/ /* word 17*/

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@@ -675,10 +675,10 @@ struct htt_rx_ring_tlv_filter {
u_int32_t phy_err_mask; u_int32_t phy_err_mask;
u_int32_t phy_err_mask_cont; u_int32_t phy_err_mask_cont;
#endif #endif
#ifdef QCA_MONITOR_2_0_SUPPORT #if defined(QCA_MONITOR_2_0_SUPPORT) || defined(CONFIG_WORD_BASED_TLV)
uint16_t rx_mpdu_start_wmask; uint16_t rx_mpdu_start_wmask;
uint16_t rx_mpdu_end_wmask; uint16_t rx_mpdu_end_wmask;
uint16_t rx_msdu_end_wmask; uint32_t rx_msdu_end_wmask;
uint16_t rx_pkt_tlv_offset; uint16_t rx_pkt_tlv_offset;
uint16_t mgmt_dma_length:3, uint16_t mgmt_dma_length:3,
ctrl_dma_length:3, ctrl_dma_length:3,

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@@ -1908,6 +1908,11 @@ struct dp_arch_ops {
qdf_nbuf_t nbuf_copy, qdf_nbuf_t nbuf_copy,
struct cdp_tid_rx_stats *tid_stats); struct cdp_tid_rx_stats *tid_stats);
void (*dp_rx_word_mask_subscribe)(
struct dp_soc *soc,
uint32_t *msg_word,
void *rx_filter);
struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc, struct dp_rx_desc *(*dp_rx_desc_cookie_2_va)(struct dp_soc *soc,
uint32_t cookie); uint32_t cookie);
uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc, uint32_t (*dp_service_near_full_srngs)(struct dp_soc *soc,

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@@ -515,6 +515,12 @@ dp_rx_intrabss_handle_nawds_li(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
return false; return false;
} }
static void dp_rx_word_mask_subscribe_li(struct dp_soc *soc,
uint32_t *msg_word,
void *rx_filter)
{
}
static struct dp_peer *dp_find_peer_by_destmac_li(struct dp_soc *soc, static struct dp_peer *dp_find_peer_by_destmac_li(struct dp_soc *soc,
uint8_t *dest_mac, uint8_t *dest_mac,
uint8_t vdev_id) uint8_t vdev_id)
@@ -609,6 +615,7 @@ void dp_initialize_arch_ops_li(struct dp_arch_ops *arch_ops)
arch_ops->dp_rx_desc_cookie_2_va = arch_ops->dp_rx_desc_cookie_2_va =
dp_rx_desc_cookie_2_va_li; dp_rx_desc_cookie_2_va_li;
arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_li; arch_ops->dp_rx_intrabss_handle_nawds = dp_rx_intrabss_handle_nawds_li;
arch_ops->dp_rx_word_mask_subscribe = dp_rx_word_mask_subscribe_li;
arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_li; arch_ops->dp_rxdma_ring_sel_cfg = dp_rxdma_ring_sel_cfg_li;
arch_ops->dp_rx_peer_metadata_peer_id_get = arch_ops->dp_rx_peer_metadata_peer_id_get =
dp_rx_peer_metadata_peer_id_get_li; dp_rx_peer_metadata_peer_id_get_li;

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@@ -179,11 +179,6 @@ void
dp_rx_mon_word_mask_subscribe(uint32_t *msg_word, dp_rx_mon_word_mask_subscribe(uint32_t *msg_word,
struct htt_rx_ring_tlv_filter *tlv_filter) struct htt_rx_ring_tlv_filter *tlv_filter)
{ {
if (!msg_word || !tlv_filter)
return;
HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_WORD_MASK_SET(*msg_word,
tlv_filter->rx_mpdu_start_wmask);
#ifdef QCA_MONITOR_2_0_SUPPORT_WAR /* Yet to get FW support */ #ifdef QCA_MONITOR_2_0_SUPPORT_WAR /* Yet to get FW support */
HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(*msg_word, HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_WORD_MASK_SET(*msg_word,
@@ -191,9 +186,6 @@ dp_rx_mon_word_mask_subscribe(uint32_t *msg_word,
#endif #endif
/* word 15 */ /* word 15 */
msg_word++; msg_word++;
*msg_word = 0;
HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_WORD_MASK_SET(*msg_word,
tlv_filter->rx_msdu_end_wmask);
/* word 16 */ /* word 16 */
msg_word++; msg_word++;

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@@ -1767,6 +1767,31 @@ static inline uint32_t hal_rx_pkt_tlv_offset_get_generic(void)
} }
#endif #endif
#ifdef CONFIG_WORD_BASED_TLV
#define MPDU_START_WMASK 0x074C
#define MSDU_END_WMASK 0x13FC1
/**
* hal_rx_mpdu_start_wmask_get_be(): API to get the mpdu_start_tlv word mask
*
* return: Word mask for MPDU start tlv
*/
static inline uint32_t hal_rx_mpdu_start_wmask_get_be(void)
{
return MPDU_START_WMASK;
}
/**
* hal_rx_msdu_end_wmask_get_be(): API to get the msdu_end_tlv word mask
*
* return: Word mask for MSDU end tlv
*/
static inline uint32_t hal_rx_msdu_end_wmask_get_be(void)
{
return MSDU_END_WMASK;
}
#endif
#ifdef RECEIVE_OFFLOAD #ifdef RECEIVE_OFFLOAD
static inline int static inline int
hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv, hal_rx_tlv_get_offload_info_be(uint8_t *rx_tlv,

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@@ -1015,6 +1015,8 @@ struct hal_hw_txrx_ops {
uint32_t (*hal_rx_mpdu_start_offset_get)(void); uint32_t (*hal_rx_mpdu_start_offset_get)(void);
uint32_t (*hal_rx_mpdu_end_offset_get)(void); uint32_t (*hal_rx_mpdu_end_offset_get)(void);
uint32_t (*hal_rx_pkt_tlv_offset_get)(void); uint32_t (*hal_rx_pkt_tlv_offset_get)(void);
uint32_t (*hal_rx_msdu_end_wmask_get)(void);
uint32_t (*hal_rx_mpdu_start_wmask_get)(void);
void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst, void * (*hal_rx_flow_setup_fse)(uint8_t *rx_fst,
uint32_t table_offset, uint32_t table_offset,
uint8_t *rx_flow); uint8_t *rx_flow);

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@@ -2494,6 +2494,48 @@ uint32_t hal_rx_mpdu_end_offset_get(hal_soc_handle_t hal_soc_hdl)
return hal_soc->ops->hal_rx_mpdu_end_offset_get(); return hal_soc->ops->hal_rx_mpdu_end_offset_get();
} }
#ifdef CONFIG_WORD_BASED_TLV
/**
* hal_rx_mpdu_start_wmask_get(): Get the MPDU start word mask
*
* @hal_soc_hdl: HAL SOC handle
* return: mpdu_start_tlv word mask value
*/
static inline
uint32_t hal_rx_mpdu_start_wmask_get(hal_soc_handle_t hal_soc_hdl)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
if (!hal_soc || !hal_soc->ops) {
hal_err("hal handle is NULL");
QDF_BUG(0);
return 0;
}
return hal_soc->ops->hal_rx_mpdu_start_wmask_get();
}
/**
* hal_rx_msdu_end_wmask_get(): Get the MSDU END word mask
*
* @hal_soc_hdl: HAL SOC handle
* return: msdu_end_tlv word mask value
*/
static inline
uint32_t hal_rx_msdu_end_wmask_get(hal_soc_handle_t hal_soc_hdl)
{
struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
if (!hal_soc || !hal_soc->ops) {
hal_err("hal handle is NULL");
QDF_BUG(0);
return 0;
}
return hal_soc->ops->hal_rx_msdu_end_wmask_get();
}
#endif
/** /**
* hal_rx_attn_offset_get(): Get the ATTENTION offset from * hal_rx_attn_offset_get(): Get the ATTENTION offset from
* rx_pkt_tlvs structure * rx_pkt_tlvs structure

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@@ -2093,6 +2093,12 @@ static void hal_hw_txrx_ops_attach_qcn9224(struct hal_soc *hal_soc)
hal_tx_populate_bank_register_be; hal_tx_populate_bank_register_be;
hal_soc->ops->hal_tx_vdev_mcast_ctrl_set = hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
hal_tx_vdev_mcast_ctrl_set_be; hal_tx_vdev_mcast_ctrl_set_be;
#ifdef CONFIG_WORD_BASED_TLV
hal_soc->ops->hal_rx_mpdu_start_wmask_get =
hal_rx_mpdu_start_wmask_get_be;
hal_soc->ops->hal_rx_msdu_end_wmask_get =
hal_rx_msdu_end_wmask_get_be;
#endif
}; };
/** /**