samsung-sm8650/android_kernel_samsung_sm8650-modules
1
0
Bifurcation 0
Code Tickets Demandes d'ajout Actions Paquets Projets Publications Wiki Activité

msm: camera: csiphy: Add Hardware register support for Kailua

Parcourir la source 
Add new header version 2_1_2 to support CSIPHY hardware register
programming for Kailua align with version 6.0.

CRs-Fixed: 3048249
Change-Id: I59215d07247a2476ebb39f889fb90ecce4e17be0
Signed-off-by: Jigarkumar Zala <quic_jzala@quicinc.com>
Cette révision appartient à :
Jigarkumar Zala
2021-10-28 17:52:09 -07:00
révisé par Gerrit - the friendly Code Review server
Parent 8d2fe2dc4a
révision 6a520c5dfa
3 fichiers modifiés avec 802 ajouts et 0 suppressions
Télécharger le Fichier Patch Télécharger le Fichier des Différences Développer tous les fichiers Réduire tous les fichiers

19
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.c
Voir le fichier

@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include "cam_csiphy_soc.h"
@@ -15,6 +16,7 @@
#include "include/cam_csiphy_2_0_hwreg.h"
#include "include/cam_csiphy_2_1_0_hwreg.h"
#include "include/cam_csiphy_2_1_1_hwreg.h"
#include "include/cam_csiphy_2_1_2_hwreg.h"
#include "include/cam_csiphy_2_1_3_hwreg.h"
/* Clock divide factor for CPHY spec v1.0 */
@@ -508,6 +510,23 @@ int32_t cam_csiphy_parse_dt_info(struct platform_device *pdev,
csiphy_dev->clk_lane = 0;
csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_1_3;
csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_3;
} else if (of_device_is_compatible(soc_info->dev->of_node,
"qcom,csiphy-v2.1.2")) {
csiphy_dev->ctrl_reg->csiphy_2ph_reg = csiphy_2ph_v2_1_2_reg;
csiphy_dev->ctrl_reg->csiphy_2ph_combo_mode_reg = csiphy_2ph_v2_1_2_combo_mode_reg;
csiphy_dev->ctrl_reg->csiphy_3ph_reg = csiphy_3ph_v2_1_2_reg;
csiphy_dev->ctrl_reg->csiphy_2ph_3ph_mode_reg = NULL;
csiphy_dev->ctrl_reg->csiphy_irq_reg = csiphy_irq_reg_2_1_2;
csiphy_dev->ctrl_reg->csiphy_common_reg = csiphy_common_reg_2_1_2;
csiphy_dev->ctrl_reg->csiphy_reset_enter_regs = csiphy_reset_enter_reg_2_1_2;
csiphy_dev->ctrl_reg->csiphy_reset_exit_regs = csiphy_reset_exit_reg_2_1_2;
csiphy_dev->ctrl_reg->csiphy_reg = csiphy_v2_1_2;
csiphy_dev->ctrl_reg->getclockvoting = get_clk_voting_dynamic;
csiphy_dev->hw_version = CSIPHY_VERSION_V212;
csiphy_dev->is_divisor_32_comp = true;
csiphy_dev->clk_lane = 0;
csiphy_dev->ctrl_reg->data_rates_settings_table = &data_rate_delta_table_2_1_2;
csiphy_dev->ctrl_reg->csiphy_bist_reg = &bist_setting_2_1_2;
} else {
CAM_ERR(CAM_CSIPHY, "invalid hw version : 0x%x",
csiphy_dev->hw_version);

2
drivers/cam_sensor_module/cam_csiphy/cam_csiphy_soc.h
Voir le fichier

@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CSIPHY_SOC_H_
@@ -32,6 +33,7 @@
#define CSIPHY_VERSION_V201 0x201
#define CSIPHY_VERSION_V210 0x210
#define CSIPHY_VERSION_V211 0x211
#define CSIPHY_VERSION_V212 0x212
#define CSIPHY_VERSION_V213 0x213
/**

781
drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_2_1_2_hwreg.h Fichier normal
Voir le fichier

@@ -0,0 +1,781 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _CAM_CSIPHY_2_1_2_HWREG_H_
#define _CAM_CSIPHY_2_1_2_HWREG_H_
#include "../cam_csiphy_dev.h"
struct cam_csiphy_aon_sel_params_t aon_cam_select_params_2_1_2 = {
.aon_cam_sel_offset = 0x01E0,
.cam_sel_mask = BIT(0),
.mclk_sel_mask = BIT(8),
};
struct cam_cphy_dphy_status_reg_params_t status_regs_2_1_2 = {
.csiphy_3ph_status0_offset = 0x0340,
.csiphy_2ph_status0_offset = 0x00C0,
.cphy_lane_status = {0x0358, 0x0758, 0x0B58},
.csiphy_3ph_status_size = 24,
.csiphy_2ph_status_size = 20,
};
struct csiphy_reg_parms_t csiphy_v2_1_2 = {
.mipi_csiphy_interrupt_status0_addr = 0x10B0,
.status_reg_params = &status_regs_2_1_2,
.size_offset_betn_lanes = 0x400,
.mipi_csiphy_interrupt_clear0_addr = 0x1058,
.mipi_csiphy_glbl_irq_cmd_addr = 0x1028,
.csiphy_common_array_size = 3,
.csiphy_reset_enter_array_size = 2,
.csiphy_reset_exit_array_size = 3,
.csiphy_2ph_config_array_size = 23,
.csiphy_3ph_config_array_size = 28,
.csiphy_2ph_clock_lane = 0x1,
.csiphy_2ph_combo_ck_ln = 0x10,
.csiphy_interrupt_status_size = 11,
.csiphy_num_common_status_regs = 20,
.aon_sel_params = &aon_cam_select_params_2_1_2,
};
struct csiphy_reg_t csiphy_common_reg_2_1_2[] = {
{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
{0x101C, 0x7A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1018, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
};
struct csiphy_reg_t csiphy_reset_enter_reg_2_1_2[] = {
{0x1014, 0x00, 0x00, CSIPHY_LANE_ENABLE},
{0x1000, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},
};
struct csiphy_reg_t csiphy_reset_exit_reg_2_1_2[] = {
{0x1000, 0x02, 0x00, CSIPHY_2PH_REGS},
{0x1000, 0x00, 0x00, CSIPHY_2PH_COMBO_REGS},
{0x1000, 0x0E, 0xBE8, CSIPHY_3PH_REGS},
};
struct csiphy_reg_t csiphy_irq_reg_2_1_2[] = {
{0x102c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1030, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1034, 0xfb, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1038, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x103c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1040, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1044, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1048, 0xef, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x104c, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1050, 0xff, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x1054, 0xff, 0x64, CSIPHY_DEFAULT_PARAMS},
};
struct csiphy_reg_t csiphy_2ph_v2_1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{
{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
},
{
{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E94, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
},
{
{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
},
{
{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0828, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x080C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
},
{
{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C28, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0C00, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C0C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0C38, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C94, 0xD7, 0x00, CSIPHY_SKEW_CAL},
{0x0C5C, 0x00, 0x00, CSIPHY_SKEW_CAL},
{0x0C60, 0xBD, 0x00, CSIPHY_SKEW_CAL},
{0x0C64, 0x7F, 0x00, CSIPHY_SKEW_CAL},
},
};
struct csiphy_reg_t
csiphy_2ph_v2_1_2_combo_mode_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{
{0x0094, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0090, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0098, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0094, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0030, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0028, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0000, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x000C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0038, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x002C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0034, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x001C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0014, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x003C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0020, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0008, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0010, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0094, 0xD7, 0x00, CSIPHY_SKEW_CAL},
{0x005C, 0x00, 0x00, CSIPHY_SKEW_CAL},
{0x0060, 0xBD, 0x00, CSIPHY_SKEW_CAL},
{0x0064, 0x7F, 0x00, CSIPHY_SKEW_CAL},
},
{
{0x0E94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0EA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0E30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E28, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0E10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E94, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0E5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0E60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0E64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
},
{
{0x0494, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x04A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0490, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0498, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0494, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0430, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0428, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0400, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x040C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0438, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x042C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0434, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x041C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0414, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x043C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0404, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0420, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0408, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0410, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0494, 0xD7, 0x00, CSIPHY_SKEW_CAL},
{0x045C, 0x00, 0x00, CSIPHY_SKEW_CAL},
{0x0460, 0xBD, 0x00, CSIPHY_SKEW_CAL},
{0x0464, 0x7F, 0x00, CSIPHY_SKEW_CAL},
},
{
{0x0894, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x08A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0890, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0898, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0894, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0830, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0800, 0x8E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x080C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0838, 0xFE, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0828, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x082C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0834, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x081C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0814, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x083C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0804, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0820, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0808, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0810, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0894, 0xD7, 0x00, CSIPHY_SKEW_CAL},
{0x085C, 0x00, 0x00, CSIPHY_SKEW_CAL},
{0x0860, 0xBD, 0x00, CSIPHY_SKEW_CAL},
{0x0864, 0x7F, 0x00, CSIPHY_SKEW_CAL},
},
{
{0x0C94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0CA0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C90, 0x0f, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x0C30, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C00, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C0C, 0xFF, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C38, 0x1F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C28, 0x0E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C2C, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C34, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C1C, 0x0A, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C14, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C3C, 0xB8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C04, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C20, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C08, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0C10, 0x52, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0C94, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0C5C, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0C60, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x0C64, 0x00, 0x00, CSIPHY_DNP_PARAMS},
},
};
struct csiphy_reg_t csiphy_3ph_v2_1_2_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = {
{
{0x0294, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x02F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x02F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x02FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x02F0, 0xEF, 0x03, CSIPHY_DEFAULT_PARAMS},
{0x0204, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0208, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
{0x0210, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* cphy_sync_Preamble_post_data_ln0 */
{0x02E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x02E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x02EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0218, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x021C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0220, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0224, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0228, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x022C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* End of reg set for cphy_sync_preamble_post */
{0x0264, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0244, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0310, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x02BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0254, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x025C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0240, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0260, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0284, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0290, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x0694, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x06F4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x06F8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x06FC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x06F0, 0xEF, 0x03, CSIPHY_DEFAULT_PARAMS},
{0x0604, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x060C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0608, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
{0x0610, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* cphy_sync_Preamble_post_data_ln1 */
{0x06E4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x06E8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x06EC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0618, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x061C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0620, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0624, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0628, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x062C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* End of reg set for cphy_sync_preamble_post */
{0x0664, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0644, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0710, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x06BC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0654, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x065C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0640, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0660, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0684, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0690, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
},
{
{0x0A94, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AF4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AF8, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AFC, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AF0, 0xEF, 0x03, CSIPHY_DEFAULT_PARAMS},
{0x0A04, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A0C, 0x10, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x0A08, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
{0x0A10, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* cphy_sync_Preamble_post_data_ln2 */
{0x0AE4, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AE8, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0AEC, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A18, 0x3E, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A1C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A20, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A24, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A28, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A2C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* End of reg set for cphy_sync_preamble_post */
{0x0A64, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A44, 0xB2, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0B10, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0ABC, 0xD0, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A54, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A5C, 0x04, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A40, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A60, 0xA8, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A90, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
},
};
struct csiphy_reg_t bist_arr_2_1_2[] = {
/* 3Phase BIST CONFIGURATION REG SET */
{0x0230, 0x94, 0x00, CSIPHY_3PH_REGS},
{0x0234, 0x31, 0x00, CSIPHY_3PH_REGS},
{0x0238, 0x60, 0x00, CSIPHY_3PH_REGS},
{0x023C, 0xA6, 0x00, CSIPHY_3PH_REGS},
{0x0258, 0x10, 0x00, CSIPHY_3PH_REGS},
{0x02C8, 0xAA, 0x00, CSIPHY_3PH_REGS},
{0x02D0, 0xAA, 0x00, CSIPHY_3PH_REGS},
{0x02D4, 0x64, 0x00, CSIPHY_3PH_REGS},
{0x02D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
{0x0244, 0xB1, 0x00, CSIPHY_3PH_REGS},
{0x0240, 0x85, 0x00, CSIPHY_3PH_REGS},
{0x0630, 0x94, 0x00, CSIPHY_3PH_REGS},
{0x0634, 0x31, 0x00, CSIPHY_3PH_REGS},
{0x0638, 0x60, 0x00, CSIPHY_3PH_REGS},
{0x063C, 0xA6, 0x00, CSIPHY_3PH_REGS},
{0x0658, 0x10, 0x00, CSIPHY_3PH_REGS},
{0x06C8, 0xAA, 0x00, CSIPHY_3PH_REGS},
{0x06D0, 0xAA, 0x00, CSIPHY_3PH_REGS},
{0x06D4, 0x64, 0x00, CSIPHY_3PH_REGS},
{0x06D8, 0x3E, 0x00, CSIPHY_3PH_REGS},
{0x0644, 0xB1, 0x00, CSIPHY_3PH_REGS},
{0x0640, 0x85, 0x00, CSIPHY_3PH_REGS},
{0x0A30, 0x94, 0x00, CSIPHY_3PH_REGS},
{0x0A34, 0x31, 0x00, CSIPHY_3PH_REGS},
{0x0A38, 0x60, 0x00, CSIPHY_3PH_REGS},
{0x0A3C, 0xA6, 0x00, CSIPHY_3PH_REGS},
{0x0A58, 0x10, 0x00, CSIPHY_3PH_REGS},
{0x0AC8, 0xAA, 0x00, CSIPHY_3PH_REGS},
{0x0AD0, 0xAA, 0x00, CSIPHY_3PH_REGS},
{0x0AD4, 0x64, 0x00, CSIPHY_3PH_REGS},
{0x0AD8, 0x3E, 0x00, CSIPHY_3PH_REGS},
{0x0A44, 0xB1, 0x00, CSIPHY_3PH_REGS},
{0x0A40, 0x85, 0x00, CSIPHY_3PH_REGS},
/* For Continuous BIST set 0x00
* For Counting BIST set upto 0xFFFF
*/
{0x0248, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x024C, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x0648, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x064C, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x0A48, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x0A4C, 0x00, 0x00, CSIPHY_3PH_REGS},
/* End of setup BIST */
};
struct csiphy_reg_t bist_status_arr_2_1_2[] = {
{0x0344, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x0744, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x0B44, 0x00, 0x00, CSIPHY_3PH_REGS},
{0x00C0, 0x00, 0x00, CSIPHY_2PH_REGS},
{0x04C0, 0x00, 0x00, CSIPHY_2PH_REGS},
{0x08C0, 0x00, 0x00, CSIPHY_2PH_REGS},
{0x0CC0, 0x00, 0x00, CSIPHY_2PH_REGS},
};
struct bist_reg_settings_t bist_setting_2_1_2 = {
.error_status_val_3ph = 0x10,
.error_status_val_2ph = 0x10,
.set_status_update_3ph_base_offset = 0x0240,
.set_status_update_2ph_base_offset = 0x0050,
.bist_status_3ph_base_offset = 0x0344,
.bist_status_2ph_base_offset = 0x00C0,
.bist_sensor_data_3ph_status_base_offset = 0x0340,
.bist_counter_3ph_base_offset = 0x0348,
.bist_counter_2ph_base_offset = 0x00C8,
.number_of_counters = 2,
.num_data_settings = ARRAY_SIZE(bist_arr_2_1_2),
.bist_arry = bist_arr_2_1_0,
.num_status_reg = ARRAY_SIZE(bist_status_arr_2_1_2),
.bist_status_arr = bist_status_arr_2_1_2,
};
struct data_rate_settings_t data_rate_delta_table_2_1_2 = {
.num_data_rate_settings = 4,
.data_rate_settings = {
{
/* ((1.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 3420000000,
.data_rate_reg_array_size = 12,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive*/
{0x020C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
/* AFE settings */
{0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x060C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x09, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x0A0C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x09, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((2.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 5700000000,
.data_rate_reg_array_size = 12,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x020C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x060C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x0A0C, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((4.5 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 10260000000,
.data_rate_reg_array_size = 12,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x020C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x060C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x0A0C, 0x1B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
{
/* ((6 GSpS) * (10^9) * (2.28 bits/symbol)) rounded value*/
.bandwidth = 13680000000,
.data_rate_reg_array_size = 12,
.per_lane_info = {
{
.lane_identifier = CPHY_LANE_0,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0268, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0278, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0288, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x028C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x026C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0270, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0274, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x020C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0214, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_1,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0668, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0678, 0x07, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0688, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x068C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x066C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0670, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0674, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x060C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0614, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DNP_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DNP_PARAMS},
},
},
{
.lane_identifier = CPHY_LANE_2,
.csiphy_data_rate_regs = {
/* AFE Settings */
{0x0A68, 0xF1, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A78, 0x14, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A88, 0xA4, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A8C, 0x85, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A6C, 0x2B, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A70, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A74, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},
/* Datarate Sensitive */
{0x0A0C, 0x19, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0A14, 0x00, 0x0A, CSIPHY_DEFAULT_PARAMS},
/* Common Current Gain Sensitive */
{0x1084, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x108C, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS},
},
},
},
},
},
};
#endif /* _CAM_CSIPHY_2_1_2_HWREG_H_ */