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@@ -127,6 +127,7 @@
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#define CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG 17
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#define CAM_ISP_GENERIC_BLOB_TYPE_INIT_CONFIG 18
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#define CAM_ISP_GENERIC_BLOB_TYPE_RDI_LCR_CONFIG 19
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+#define CAM_ISP_GENERIC_BLOB_TYPE_SFE_FCG_CFG 20
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#define CAM_ISP_GENERIC_BLOB_TYPE_SFE_CLOCK_CONFIG 21
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#define CAM_ISP_GENERIC_BLOB_TYPE_SFE_CORE_CONFIG 22
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#define CAM_ISP_GENERIC_BLOB_TYPE_SFE_OUT_CONFIG 23
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@@ -139,6 +140,7 @@
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#define CAM_ISP_GENERIC_BLOB_TYPE_NFI_MODE_SWITCH 30
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#define CAM_ISP_GENERIC_BLOB_TYPE_IRQ_COMP_CFG 31
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#define CAM_ISP_GENERIC_BLOB_TYPE_VFE_OUT_CONFIG_V2 32
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+#define CAM_ISP_GENERIC_BLOB_TYPE_IFE_FCG_CFG 33
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#define CAM_ISP_VC_DT_CFG 4
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@@ -204,6 +206,20 @@
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#define CAM_ISP_PARAM_CORE_CFG_HDR_MUX_SEL BIT(0)
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#define CAM_ISP_PARAM_CORE_CFG_PP_FORMAT BIT(16)
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+/* Indicate which module is configured for FCG */
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+#define CAM_ISP_FCG_ENABLE_PHASE BIT(0)
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+#define CAM_ISP_FCG_ENABLE_STATS BIT(1)
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+
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+/*
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+ * Indicate which channel is configured for FCG
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+ * For SFE, channel 1/2 are used on demand
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+ * For IFE, treat it as channel 0
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+ * For TFE, use Multi Context Mask to indicate the path
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+ */
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+#define CAM_ISP_FCG_MASK_CH0 0x1
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+#define CAM_ISP_FCG_MASK_CH1 0x2
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+#define CAM_ISP_FCG_MASK_CH2 0x4
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+
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/**
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* Decode format1 Support for multi VCDT use case.
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* Format type is packed in 8 bits. BIT(0-7) is
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@@ -974,6 +990,89 @@ struct cam_isp_sfe_init_scratch_buf_config {
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struct cam_isp_sfe_scratch_buf_info port_scratch_cfg[1];
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};
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+/**
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+ * struct cam_isp_predict_fcg_config - FCG config in a single prediction
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+ *
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+ * @version: Version Info
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+ * @phase_index_g: Starting index of LUT for G channel in phase
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+ * @phase_index_r: Starting index of LUT for R channel in phase
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+ * @phase_index_b: Starting index of LUT for B channel in phase
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+ * @stats_index_g: Starting index of LUT for G channel in stats
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+ * @stats_index_r: Starting index of LUT for R channel in stats
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+ * @stats_index_b: Starting index of LUT for B channel in stats
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+ * @num_valid_params: Number of valid params being used
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+ * @valid_param_mask: Indicate the exact params being used
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+ * @params: Params for future change
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+ */
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+struct cam_isp_predict_fcg_config {
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+ __u32 version;
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+ __u32 phase_index_g;
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+ __u32 phase_index_r;
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+ __u32 phase_index_b;
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+ __u32 stats_index_g;
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+ __u32 stats_index_r;
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+ __u32 stats_index_b;
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+ __u32 num_valid_params;
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+ __u32 valid_param_mask;
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+ __u32 params[5];
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+};
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+
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+/**
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+ * struct cam_isp_ch_ctx_fcg_config - FCG config in a single channel for SFE/IFE
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+ * or in a single context in TFE
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+ *
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+ * @version: Version Info
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+ * @fcg_ch_ctx_id: Index of the channel to be configured that FCG
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+ * blocks reside on. If one wants to config FCG
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+ * block for IFE/SFE, CAM_ISP_FCG_MASK_CH0/1/2 is
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+ * used. If one wants to config FCG block for TFE,
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+ * multi context mask is used.
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+ * @fcg_enable_mask: Indicate which module will be enabled for
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+ * FCG. For example, if one wants to config
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+ * SFE FCG STATS module, CAM_ISP_FCG_ENABLE_STATS
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+ * will be set in mask
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+ * @num_valid_params: Number of valid params being used
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+ * @valid_param_mask: Indicate the exact params being used
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+ * @params: Params for future change
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+ * @predicted_fcg_configs: Pointer to fcg config for each prediction of
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+ * the channel in serial order
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+ */
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+struct cam_isp_ch_ctx_fcg_config {
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+ __u32 version;
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+ __u32 fcg_ch_ctx_id;
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+ __u32 fcg_enable_mask;
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+ __u32 num_valid_params;
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+ __u32 valid_param_mask;
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+ __u32 params[5];
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+ struct cam_isp_predict_fcg_config predicted_fcg_configs[1];
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+};
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+
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+/**
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+ * struct cam_isp_generic_fcg_config - FCG config for a frame
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+ *
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+ * @version: Version info
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+ * @size: Size for the whole FCG configurations
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+ * @num_ch_ctx: Number of channels for fcg config in SFE/IFE
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+ * or number of contexts in TFE
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+ * @num_predictions: Number of predictions for each channel
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+ * in SFE/IFE or for each context in TFE
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+ * @num_valid_params: Number of valid params being used
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+ * @valid_param_mask: Indicate the exact params being used
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+ * @params: Params for future change
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+ * @ch_ctx_fcg_configs: Pointer to fcg config for each channel in
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+ * SFE/IFE or for each context in TFE
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+ */
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+struct cam_isp_generic_fcg_config {
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+ __u32 version;
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+ __u32 size;
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+ __u32 num_ch_ctx;
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+ __u32 num_predictions;
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+ __u32 num_valid_params;
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+ __u32 valid_params_mask;
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+ __u32 params[4];
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+ struct cam_isp_ch_ctx_fcg_config ch_ctx_fcg_configs[1];
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+};
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+
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/**
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* struct cam_isp_tpg_core_config - TPG core registers configuration
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*
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