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@@ -1135,6 +1135,7 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
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u8 dmic_ctl_shift = 0;
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u8 dmic_clk_shift = 0;
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u8 dmic_clk_mask = 0;
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+ u16 dmic2_left_en = 0;
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dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
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w->name, event);
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@@ -1150,6 +1151,7 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
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dmic_ctl_shift = 0x00;
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break;
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case 2:
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+ dmic2_left_en = WCD938X_DIGITAL_CDC_DMIC2_CTL;
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case 3:
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dmic_clk_cnt = &(wcd938x->dmic_2_3_clk_cnt);
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dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
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@@ -1191,6 +1193,9 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
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(0x01 << dmic_ctl_shift), 0x00);
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/* 250us sleep as per HW requirement */
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usleep_range(250, 260);
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+ if (dmic2_left_en)
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+ snd_soc_component_update_bits(component,
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+ dmic2_left_en, 0x80, 0x80);
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/* Setting DMIC clock rate to 2.4MHz */
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snd_soc_component_update_bits(component,
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dmic_clk_reg, dmic_clk_mask,
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@@ -1208,6 +1213,9 @@ static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
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WCD938X_DIGITAL_CDC_AMIC_CTL,
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(0x01 << dmic_ctl_shift),
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(0x01 << dmic_ctl_shift));
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+ if (dmic2_left_en)
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+ snd_soc_component_update_bits(component,
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+ dmic2_left_en, 0x80, 0x00);
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snd_soc_component_update_bits(component,
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dmic_clk_en_reg, 0x08, 0x00);
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break;
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qctecmdr