disp: msm: sde: align timing engine vsync based on panel vsync

This change adds logic to align timing engine vsync with panel
tear check if it is supported.

Change-Id: I3f881f392929589848c893f567822b21c0650000
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>

msm/msm_drv.h

@@ -679,6 +679,7 @@ struct msm_resource_caps_info {
  * @display_type:       Enum for type of display
  * @is_te_using_watchdog_timer:  Boolean to indicate watchdog TE is
  *				 used instead of panel TE in cmd mode panels
+ * @poms_align_vsync:   poms with vsync aligned
  * @roi_caps:           Region of interest capability info
  * @qsync_min_fps	Minimum fps supported by Qsync feature
  * @te_source		vsync source pin information
@@ -701,6 +702,7 @@ struct msm_display_info {
 
 	uint32_t display_type;
 	bool is_te_using_watchdog_timer;
+	bool poms_align_vsync;
 	struct msm_roi_caps roi_caps;
 
 	uint32_t qsync_min_fps;

msm/sde/sde_encoder.c

@@ -2582,6 +2582,7 @@ static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
 		phys->comp_ratio = comp_info->comp_ratio;
 		phys->wide_bus_en = sde_enc->mode_info.wide_bus_en;
 		phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
+		phys->poms_align_vsync = disp_info->poms_align_vsync;
 		if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
 			phys->dsc_extra_pclk_cycle_cnt =
 				comp_info->dsc_info.pclk_per_line;

msm/sde/sde_encoder_phys.h

@@ -271,6 +271,7 @@ struct sde_encoder_irq {
  * @dsc_extra_pclk_cycle_cnt: Extra pclk cycle count for DSC over DP
  * @dsc_extra_disp_width: Additional display width for DSC over DP
  * @wide_bus_en:	Wide-bus configuraiton
+ * @poms_align_vsync:   poms with vsync aligned
  * @enc_spinlock:	Virtual-Encoder-Wide Spin Lock for IRQ purposes
  * @enable_state:	Enable state tracking
  * @vblank_refcount:	Reference count of vblank request
@@ -317,6 +318,7 @@ struct sde_encoder_phys {
 	u32 dsc_extra_pclk_cycle_cnt;
 	u32 dsc_extra_disp_width;
 	bool wide_bus_en;
+	bool poms_align_vsync;
 	spinlock_t *enc_spinlock;
 	enum sde_enc_enable_state enable_state;
 	struct mutex *vblank_ctl_lock;

msm/sde/sde_encoder_phys_vid.c

@@ -88,6 +88,7 @@ static void drm_mode_to_intf_timing_params(
 					vid_enc->base.comp_ratio);
 	}
 
+	timing->poms_align_vsync = phys_enc->poms_align_vsync;
 	timing->height = mode->vdisplay;	/* active height */
 	timing->xres = timing->width;
 	timing->yres = timing->height;

msm/sde/sde_hw_catalog.c

@@ -2150,6 +2150,10 @@ static int sde_intf_parse_dt(struct device_node *np,
 
 			set_bit(SDE_INTF_TE, &intf->features);
 		}
+
+		if (SDE_HW_MAJOR(sde_cfg->hwversion) >=
+				SDE_HW_MAJOR(SDE_HW_VER_700))
+			set_bit(SDE_INTF_TE_ALIGN_VSYNC, &intf->features);
 	}
 
 end:

msm/sde/sde_hw_catalog.h

@@ -446,11 +446,13 @@ enum {
  * @SDE_INTF_INPUT_CTRL         Supports the setting of pp block from which
  *                              pixel data arrives to this INTF
  * @SDE_INTF_TE                 INTF block has TE configuration support
+ * @SDE_INTF_TE_ALIGN_VSYNC     INTF block has POMS Align vsync support
  * @SDE_INTF_MAX
  */
 enum {
 	SDE_INTF_INPUT_CTRL = 0x1,
 	SDE_INTF_TE,
+	SDE_INTF_TE_ALIGN_VSYNC,
 	SDE_INTF_MAX
 };
 

msm/sde/sde_hw_intf.c

@@ -309,6 +309,11 @@ static void sde_hw_intf_setup_timing_engine(struct sde_hw_intf *ctx,
 	if (p->wide_bus_en)
 		intf_cfg2 |= BIT(0);
 
+	/* Synchronize timing engine enable to TE */
+	if ((ctx->cap->features & BIT(SDE_INTF_TE_ALIGN_VSYNC))
+			&& p->poms_align_vsync)
+		intf_cfg2 |= BIT(16);
+
 	if (ctx->cfg.split_link_en)
 		SDE_REG_WRITE(c, INTF_REG_SPLIT_LINK, 0x3);
 

msm/sde/sde_hw_intf.h

@@ -37,6 +37,7 @@ struct intf_timing_params {
 	bool compression_en;
 	u32 extra_dto_cycles;	/* for DP only */
 	bool dsc_4hs_merge;	/* DSC 4HS merge */
+	bool poms_align_vsync;	/* poms with vsync aligned */
 };
 
 struct intf_prog_fetch {