samsung-sm8650/android_kernel_samsung_sm8650-modules
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fw-api: Add R53 Hardware header files

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Add version R53 header files for QCA6390
based products.
Change-Id: I43dc78694f5b316f80f260ad3e03592ad7fbb4a1
CRs-Fixed: 2333609
Этот коммит содержится в:
Venkata Sharath Chandra Manchala
2018-10-04 23:16:59 -07:00
коммит произвёл nshrivas
родитель 6281186840
Коммит 66794c2370
9 изменённых файлов: 71 добавлений и 87 удалений
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1
hw/qca6390/v1/HALhwio.h
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@@ -42,7 +42,6 @@
#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET
#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET
#define SEQ_WMAC_TOP_REG_MAC_RXDMA1_REG_OFFSET SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET
/* -----------------------------------------------------------------------
** Macros

4
hw/qca6390/v1/mac_tcl_reg_seq_hwiobase.h
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@@ -18,8 +18,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
//
// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 5/10/2018
// User Name:gunjans
// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 8/13/2018
// User Name:pparekh
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

44
hw/qca6390/v1/msmhwio.h
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@@ -1,44 +0,0 @@
/*
* Copyright (c) 2018 The Linux Foundation. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
* above copyright notice and this permission notice appear in all
* copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef MSMHWIO_H
#define MSMHWIO_H
/**
@file msmhwio.h
Deprecated public interface include file for accessing the HWIO macro
definitions.
The msmhwio.h file is the legacy public API interface to the HW I/O (HWIO)
register access definitions. See HALhwio.h and DDIHWIO.h for the new
interfaces.
*/
/*=========================================================================
Include Files
==========================================================================*/
/*
* Include main HWIO macros.
*/
#include "HALhwio.h"
#endif /* MSMHWIO_H */

4
hw/qca6390/v1/reo_reg_seq_hwiobase.h
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@@ -18,8 +18,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
//
// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 5/10/2018
// User Name:gunjans
// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 8/13/2018
// User Name:pparekh
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

18
hw/qca6390/v1/seq_hwio.h
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@@ -16,6 +16,24 @@
* PERFORMANCE OF THIS SOFTWARE.
*/
/*********************************************************************************
*
* DESCRIPTION
* - This is an extension of standard msmhwio.h to support relative addressing
* scheme used in SCALe auto-generated sequences.
* - The objective of this new addressing scheme is enable the same C function
* definition to be applicable to multiple baseances of the same block.
* - Such code reuse is not feasible with the standard HWIO macros that use a
* absolute addressing scheme.
* - Compared to the standard HWIO macros, the new macros defined here take an
* additional parameter 'baseance offset'. So are the C functions generated
* by SCALe Autoseq from .seq inputs.
* - As such, macros defined in this file must be used with 'seq_msmhwiobase.h',
* 'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq.
* - Macros defined in this file leverage the lower-level macros from the
* standard 'msmhwio.h', and the two sets of macros are compatible.
********************************************************************************/
#ifndef __SEQ_H__
#define __SEQ_H__

4
hw/qca6390/v1/wbm_reg_seq_hwiobase.h
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@@ -18,8 +18,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 5/10/2018
// User Name:gunjans
// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 8/13/2018
// User Name:pparekh
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//

77
hw/qca6390/v1/wcss_seq_hwiobase.h
Просмотреть файл

@@ -18,8 +18,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 5/10/2018
// User Name:gunjans
// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 8/13/2018
// User Name:pparekh
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//
@@ -44,7 +44,6 @@
#else
#endif
///////////////////////////////////////////////////////////////////////////////////////////////
// Instance Relative Offsets from Block wcss
///////////////////////////////////////////////////////////////////////////////////////////////
@@ -84,7 +83,11 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x005d0000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d4c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x005d5000
@@ -110,7 +113,7 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x005d7180
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x005d71c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x005d7280
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x005d7c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x005dc000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005de800
@@ -132,7 +135,6 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x005e2400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x005e2500
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x005e2580
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x005e25c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x005e26c0
@@ -152,7 +154,6 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x005ea400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x005ea500
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x005ea580
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x005ea5c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x005ea6c0
@@ -172,7 +173,7 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x005f2400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x005f2500
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x005f2500
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x005f2580
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x005f25c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x005f26c0
@@ -184,6 +185,7 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x005f28c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x005f2900
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x005f299c
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x005f2c00
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x005f8400
@@ -192,7 +194,6 @@
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9300
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x005fa400
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x005fa500
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x005fa580
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x005fa5c0
#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x005fa6c0
@@ -237,7 +238,11 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x007d0000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x007d4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x007d4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x007d4240
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x007d42c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x007d4300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x007d4400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x007d4480
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x007d4800
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x007d4c00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x007d5000
@@ -263,7 +268,7 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x007d7180
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x007d71c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x007d7280
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x007d7c00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x007d7c00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x007dc000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x007dc000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x007de800
@@ -285,7 +290,6 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x007e1300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x007e2000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x007e2400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x007e2500
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x007e2580
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x007e25c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x007e26c0
@@ -305,7 +309,6 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x007e9300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x007ea000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x007ea400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x007ea500
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x007ea580
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x007ea5c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x007ea6c0
@@ -325,7 +328,7 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x007f1300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x007f2000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x007f2400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x007f2500
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x007f2500
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x007f2580
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x007f25c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x007f26c0
@@ -337,6 +340,7 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x007f28c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x007f2900
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x007f299c
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x007f2c00
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x007f4000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x007f8000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x007f8400
@@ -345,7 +349,6 @@
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x007f9300
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x007fa000
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x007fa400
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x007fa500
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x007fa580
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x007fa5c0
#define SEQ_WCSS_PHYB_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x007fa6c0
@@ -541,7 +544,11 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x001d0000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x001d4240
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x001d42c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x001d4400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x001d4480
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x001d5000
@@ -567,7 +574,7 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x001d7180
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x001d71c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x001d7280
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x001d7c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x001de800
@@ -589,7 +596,6 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x001e2500
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x001e25c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x001e26c0
@@ -609,7 +615,6 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x001ea500
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x001ea5c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x001ea6c0
@@ -629,7 +634,7 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x001f2500
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x001f2500
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x001f25c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x001f26c0
@@ -641,6 +646,7 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x001f28c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x001f2900
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x001f299c
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x001f2c00
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400
@@ -649,7 +655,6 @@
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9300
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x001fa500
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x001fa5c0
#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x001fa6c0
@@ -681,7 +686,11 @@
#define SEQ_RFA_FROM_WSI_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x00010000
#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240
#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400
#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480
#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800
#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00014c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_OFFSET 0x00015000
@@ -707,7 +716,7 @@
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00017180
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000171c0
#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00017280
#define SEQ_RFA_FROM_WSI_RFA_CMN_DRM_REG_OFFSET 0x00017c00
#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00
#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TOP_OFFSET 0x0001c000
#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001e800
@@ -729,7 +738,6 @@
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00022000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00022400
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x00022500
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00022580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x000225c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x000226c0
@@ -749,7 +757,6 @@
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0002a400
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x0002a500
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0002a580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x0002a5c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x0002a6c0
@@ -769,7 +776,7 @@
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00032000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00032400
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x00032500
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_OFFSET 0x00032500
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00032580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x000325c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x000326c0
@@ -781,6 +788,7 @@
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x000328c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x00032900
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x0003299c
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_CAL_CORE_OFFSET 0x00032c00
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00034000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00038000
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00038400
@@ -789,7 +797,6 @@
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039300
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0003a000
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0003a400
#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x0003a500
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0003a580
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x0003a5c0
#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x0003a6c0
@@ -818,7 +825,11 @@
///////////////////////////////////////////////////////////////////////////////////////////////
#define SEQ_RFA_CMN_AON_OFFSET 0x00000000
#define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240
#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0
#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300
#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400
#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480
#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800
#define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00000c00
#define SEQ_RFA_CMN_BBPLL_OFFSET 0x00001000
@@ -844,7 +855,7 @@
#define SEQ_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00003180
#define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000031c0
#define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00003280
#define SEQ_RFA_CMN_DRM_REG_OFFSET 0x00003c00
#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00
///////////////////////////////////////////////////////////////////////////////////////////////
@@ -876,7 +887,6 @@
#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300
#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00002000
#define SEQ_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x00002400
#define SEQ_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x00002500
#define SEQ_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x00002580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x000025c0
#define SEQ_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x000026c0
@@ -896,7 +906,6 @@
#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300
#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000
#define SEQ_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x0000a400
#define SEQ_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x0000a500
#define SEQ_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x0000a580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x0000a5c0
#define SEQ_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x0000a6c0
@@ -916,7 +925,7 @@
#define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011300
#define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00012000
#define SEQ_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x00012400
#define SEQ_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x00012500
#define SEQ_RFA_WL_RBIST_RX_OFFSET 0x00012500
#define SEQ_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x00012580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x000125c0
#define SEQ_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x000126c0
@@ -928,6 +937,7 @@
#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x000128c0
#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x00012900
#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x0001299c
#define SEQ_RFA_WL_WL_CAL_CORE_OFFSET 0x00012c00
#define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00014000
#define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00018000
#define SEQ_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x00018400
@@ -936,7 +946,6 @@
#define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019300
#define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0001a000
#define SEQ_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x0001a400
#define SEQ_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x0001a500
#define SEQ_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x0001a580
#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x0001a5c0
#define SEQ_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x0001a6c0
@@ -986,7 +995,11 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x001d0000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_OFFSET 0x001d4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x001d4240
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x001d42c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x001d4300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x001d4400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x001d4480
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x001d4800
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x001d4c00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x001d5000
@@ -1012,7 +1025,7 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x001d7180
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x001d71c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x001d7280
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_DRM_REG_OFFSET 0x001d7c00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x001d7c00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_TOP_OFFSET 0x001dc000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x001de800
@@ -1034,7 +1047,6 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x001e1300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x001e2000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH0_OFFSET 0x001e2400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH0_OFFSET 0x001e2500
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH0_OFFSET 0x001e2580
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH0_OFFSET 0x001e25c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH0_OFFSET 0x001e26c0
@@ -1054,7 +1066,6 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x001e9300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x001ea000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH0_OFFSET 0x001ea400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH0_OFFSET 0x001ea500
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH0_OFFSET 0x001ea580
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH0_OFFSET 0x001ea5c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH0_OFFSET 0x001ea6c0
@@ -1074,7 +1085,7 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x001f1300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x001f2000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_2G_CH1_OFFSET 0x001f2400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_2G_CH1_OFFSET 0x001f2500
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_OFFSET 0x001f2500
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_2G_CH1_OFFSET 0x001f2580
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_2G_CH1_OFFSET 0x001f25c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_2G_CH1_OFFSET 0x001f26c0
@@ -1086,6 +1097,7 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_2G_CH1_OFFSET 0x001f28c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_2G_CH1_OFFSET 0x001f2900
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_2G_CH1_OFFSET 0x001f299c
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_CAL_CORE_OFFSET 0x001f2c00
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x001f4000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x001f8000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_RXBB_5G_CH1_OFFSET 0x001f8400
@@ -1094,7 +1106,6 @@
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x001f9300
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x001fa000
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_TX_5G_CH1_OFFSET 0x001fa400
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_RBIST_RX_5G_CH1_OFFSET 0x001fa500
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_5G_CH1_OFFSET 0x001fa580
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_5G_CH1_OFFSET 0x001fa5c0
#define SEQ_WFAX_TOP_B_WFAX_IRON2G_B_REG_MAP_RFA_WL_WL_DAC_MISC_5G_CH1_OFFSET 0x001fa6c0

2
hw/qca6390/v1/wcss_version.h
Просмотреть файл

@@ -15,4 +15,4 @@
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
* PERFORMANCE OF THIS SOFTWARE.
*/
#define WCSS_VERSION 1043
#define WCSS_VERSION 1053

4
hw/qca6390/v1/wfss_ce_reg_seq_hwiobase.h
Просмотреть файл

@@ -18,8 +18,8 @@
///////////////////////////////////////////////////////////////////////////////////////////////
//
// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 5/10/2018
// User Name:gunjans
// wfss_ce_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 8/13/2018
// User Name:pparekh
//
// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE.
//