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disp: msm: dsi: Add support for C-PHY dynamic clock switch

Telusuri Sumber 
This change adds support for C-PHY dynamic clock switch feature.
Also add support for phy ver 4.0 C-PHY timing parameters calculation
to be used for clock switch.

Change-Id: I8292860fd8c93a7ba7988ec8c44ea9683f45b6e6
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This commit is contained in:
Harigovindan P
2020-05-06 15:31:55 +05:30
committed by Steve Cohen
orang tua d8ffbf3d39
melakukan 662ac3ab89
8 mengubah file dengan 366 tambahan dan 74 penghapusan
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22
msm/dsi/dsi_phy_timing_calc.h
Melihat File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.
* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
*/
#ifndef _DSI_PHY_TIMING_CALC_H_
@@ -81,7 +81,8 @@ struct phy_clk_params {
* Various Ops needed for auto-calculation of DSI PHY timing parameters.
*/
struct phy_timing_ops {
void (*get_default_phy_params)(struct phy_clk_params *params);
void (*get_default_phy_params)(struct phy_clk_params *params,
u32 phy_type);
int32_t (*calc_clk_zero)(s64 rec_temp1, s64 mult);
@@ -96,14 +97,15 @@ struct phy_timing_ops {
struct phy_timing_desc *desc);
void (*update_timing_params)(struct dsi_phy_per_lane_cfgs *timing,
struct phy_timing_desc *desc);
struct phy_timing_desc *desc, u32 phy_type);
};
#define roundup64(x, y) \
({ u64 _tmp = (x)+(y)-1; do_div(_tmp, y); _tmp * y; })
/* DSI PHY timing functions for 14nm */
void dsi_phy_hw_v2_0_get_default_phy_params(struct phy_clk_params *params);
void dsi_phy_hw_v2_0_get_default_phy_params(struct phy_clk_params *params,
u32 phy_type);
int32_t dsi_phy_hw_v2_0_calc_clk_zero(s64 rec_temp1, s64 mult);
@@ -118,10 +120,11 @@ void dsi_phy_hw_v2_0_calc_hs_trail(struct phy_clk_params *clk_params,
struct phy_timing_desc *desc);
void dsi_phy_hw_v2_0_update_timing_params(struct dsi_phy_per_lane_cfgs *timing,
struct phy_timing_desc *desc);
struct phy_timing_desc *desc, u32 phy_type);
/* DSI PHY timing functions for 10nm */
void dsi_phy_hw_v3_0_get_default_phy_params(struct phy_clk_params *params);
void dsi_phy_hw_v3_0_get_default_phy_params(struct phy_clk_params *params,
u32 phy_type);
int32_t dsi_phy_hw_v3_0_calc_clk_zero(s64 rec_temp1, s64 mult);
@@ -136,10 +139,11 @@ void dsi_phy_hw_v3_0_calc_hs_trail(struct phy_clk_params *clk_params,
struct phy_timing_desc *desc);
void dsi_phy_hw_v3_0_update_timing_params(struct dsi_phy_per_lane_cfgs *timing,
struct phy_timing_desc *desc);
struct phy_timing_desc *desc, u32 phy_type);
/* DSI PHY timing functions for 7nm */
void dsi_phy_hw_v4_0_get_default_phy_params(struct phy_clk_params *params);
void dsi_phy_hw_v4_0_get_default_phy_params(struct phy_clk_params *params,
u32 phy_type);
int32_t dsi_phy_hw_v4_0_calc_clk_zero(s64 rec_temp1, s64 mult);
@@ -154,6 +158,6 @@ void dsi_phy_hw_v4_0_calc_hs_trail(struct phy_clk_params *clk_params,
struct phy_timing_desc *desc);
void dsi_phy_hw_v4_0_update_timing_params(struct dsi_phy_per_lane_cfgs *timing,
struct phy_timing_desc *desc);
struct phy_timing_desc *desc, u32 phy_type);
#endif /* _DSI_PHY_TIMING_CALC_H_ */