samsung-sm8650/android_kernel_samsung_sm8650-modules
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video: driver: fix some checker err

Parcourir la source 
Fix some checker err.

Change-Id: I6704727abf49c8c55ac9c213dec180c93928961f
Signed-off-by: Anshul Agarwal <quic_anshagar@quicinc.com>
Cette révision appartient à :
Anshul Agarwal
2023-06-08 10:55:16 +05:30
Parent be36c9f71e
révision 65d28b3cab
7 fichiers modifiés avec 66 ajouts et 52 suppressions
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16
driver/variant/iris2/inc/hfi_buffer_iris2.h
Voir le fichier

@@ -129,7 +129,7 @@ typedef HFI_U32 HFI_BOOL;
#define HFI_YUV420_TP10_CALC_Y_STRIDE(stride, frame_width, stride_multiple) \
do { \
stride = HFI_ALIGN(frame_width, 192); \
stride = HFI_ALIGN(stride * 4 / 3, stride_multiple) \
stride = HFI_ALIGN(stride * 4 / 3, stride_multiple); \
} while (0)
#define HFI_YUV420_TP10_CALC_Y_BUFHEIGHT(buf_height, frame_height, \
@@ -386,7 +386,9 @@ typedef HFI_U32 HFI_BOOL;
BUFFER_ALIGNMENT_32_BYTES); \
_size = MIN((((_height + 15) >> 4) * 48), H264D_MAX_SLICE) * \
SIZE_H264D_VPP_CMD_PER_BUF; \
if (_size > VPP_CMD_MAX_SIZE) { _size = VPP_CMD_MAX_SIZE; } \
if (_size > VPP_CMD_MAX_SIZE) { \
_size = VPP_CMD_MAX_SIZE; \
} \
} while (0)
#define HFI_BUFFER_COMV_H264D(coMV_size, frame_width, \
@@ -785,8 +787,8 @@ typedef HFI_U32 HFI_BOOL;
} while (0)
#define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO 1 / 2
#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO 3 / 2
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO (1 / 2)
#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2)
#define HFI_BUFFER_BIN_VP9D(_size, frame_width, frame_height, \
is_interlaced, num_vpp_pipes) \
@@ -820,14 +822,14 @@ typedef HFI_U32 HFI_BOOL;
#define CCE_TILE_OFFSET_SIZE HFI_ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
#define HFI_BUFFER_PERSIST_VP9D(_size) \
_size = HFI_ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, \
(_size = HFI_ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(HFI_IRIS2_VP9D_COMV_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(MAX_SUPERFRAME_HEADER_LEN, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(VP9_UDC_HEADER_BUF_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(VP9_NUM_FRAME_INFO_BUF * \
CCE_TILE_OFFSET_SIZE, VENUS_DMA_ALIGNMENT) + \
HFI_ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE, \
VENUS_DMA_ALIGNMENT) + HDR10_HIST_EXTRADATA_SIZE
VENUS_DMA_ALIGNMENT) + HDR10_HIST_EXTRADATA_SIZE)
#define HFI_BUFFER_LINE_MP2D(_size, frame_width, frame_height, \
_yuv_bufcount_min, is_opb, num_vpp_pipes) \
@@ -860,7 +862,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
#define QMATRIX_SIZE (sizeof(HFI_U32) * 128 + 256)
#define MP2D_QPDUMP_SIZE 115200
#define HFI_BUFFER_PERSIST_MP2D(_size) \
_size = QMATRIX_SIZE + MP2D_QPDUMP_SIZE;
(_size = QMATRIX_SIZE + MP2D_QPDUMP_SIZE;)
#define HFI_BUFFER_BITSTREAM_ENC(size, frame_width, frame_height, \
rc_type, is_ten_bit) \

38
driver/variant/iris3/inc/hfi_buffer_iris3.h
Voir le fichier

@@ -65,7 +65,7 @@ typedef HFI_U32 HFI_BOOL;
min_buf_height_multiple))
#define HFI_NV12_IL_CALC_UV_STRIDE(stride, frame_width, stride_multiple) \
stride = HFI_ALIGN(frame_width, stride_multiple)
(stride = HFI_ALIGN(frame_width, stride_multiple))
#define HFI_NV12_IL_CALC_UV_BUFHEIGHT(buf_height, frame_height, \
min_buf_height_multiple) (buf_height = HFI_ALIGN(((frame_height + 1) \
@@ -127,8 +127,10 @@ typedef HFI_U32 HFI_BOOL;
} while (0)
#define HFI_YUV420_TP10_CALC_Y_STRIDE(stride, frame_width, stride_multiple) \
stride = HFI_ALIGN(frame_width, 192); \
stride = HFI_ALIGN(stride * 4 / 3, stride_multiple)
do { \
stride = HFI_ALIGN(frame_width, 192); \
stride = HFI_ALIGN(stride * 4 / 3, stride_multiple); \
} while (0)
#define HFI_YUV420_TP10_CALC_Y_BUFHEIGHT(buf_height, frame_height, \
min_buf_height_multiple) \
@@ -147,9 +149,11 @@ typedef HFI_U32 HFI_BOOL;
#define HFI_YUV420_TP10_CALC_BUF_SIZE(buf_size, y_buf_size, y_stride,\
y_buf_height, uv_buf_size, uv_stride, uv_buf_height) \
y_buf_size = (y_stride * y_buf_height); \
uv_buf_size = (uv_stride * uv_buf_height); \
buf_size = y_buf_size + uv_buf_size
do { \
y_buf_size = (y_stride * y_buf_height); \
uv_buf_size = (uv_stride * uv_buf_height); \
buf_size = y_buf_size + uv_buf_size \
} while (0)
#define HFI_YUV420_TP10_UBWC_CALC_Y_BUF_SIZE(y_buf_size, y_stride, \
y_buf_height) \
@@ -382,7 +386,9 @@ typedef HFI_U32 HFI_BOOL;
BUFFER_ALIGNMENT_32_BYTES); \
_size = MIN((((_height + 15) >> 4) * 48), H264D_MAX_SLICE) * \
SIZE_H264D_VPP_CMD_PER_BUF; \
if (_size > VPP_CMD_MAX_SIZE) { _size = VPP_CMD_MAX_SIZE; } \
if (_size > VPP_CMD_MAX_SIZE) { \
_size = VPP_CMD_MAX_SIZE; \
} \
} while (0)
#define HFI_BUFFER_COMV_H264D(coMV_size, frame_width, \
@@ -507,11 +513,11 @@ typedef HFI_U32 HFI_BOOL;
#define H264_DISPLAY_BUF_SIZE (3328)
#define SIZE_DOLBY_RPU_METADATA (41 * 1024)
#define HFI_BUFFER_PERSIST_H264D(_size, rpu_enabled) \
_size = HFI_ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + \
(_size = HFI_ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + \
H264_DISPLAY_BUF_SIZE * H264_NUM_FRM_INFO + \
NUM_HW_PIC_BUF * SIZE_SEI_USERDATA + \
rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), \
VENUS_DMA_ALIGNMENT)
VENUS_DMA_ALIGNMENT))
#define LCU_MAX_SIZE_PELS 64
#define LCU_MIN_SIZE_PELS 16
@@ -700,11 +706,11 @@ typedef HFI_U32 HFI_BOOL;
#define H265_NUM_FRM_INFO (48)
#define H265_DISPLAY_BUF_SIZE (3072)
#define HFI_BUFFER_PERSIST_H265D(_size, rpu_enabled) \
_size = HFI_ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + \
(_size = HFI_ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + \
H265_NUM_FRM_INFO * H265_DISPLAY_BUF_SIZE + \
H265_NUM_TILE * sizeof(HFI_U32) + NUM_HW_PIC_BUF * SIZE_SEI_USERDATA + \
rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA),\
VENUS_DMA_ALIGNMENT)
VENUS_DMA_ALIGNMENT))
#define SIZE_VPXD_LB_FE_LEFT_CTRL(frame_width, frame_height) \
MAX(((frame_height + 15) >> 4) * \
@@ -781,8 +787,8 @@ typedef HFI_U32 HFI_BOOL;
} while (0)
#define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO 1 / 2
#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO 3 / 2
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO (1 / 2)
#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2)
#define HFI_BUFFER_BIN_VP9D(_size, frame_width, frame_height, \
is_interlaced, num_vpp_pipes) \
@@ -816,14 +822,14 @@ typedef HFI_U32 HFI_BOOL;
#define CCE_TILE_OFFSET_SIZE HFI_ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
#define HFI_BUFFER_PERSIST_VP9D(_size) \
_size = HFI_ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, \
(_size = HFI_ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(HFI_IRIS3_VP9D_COMV_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(MAX_SUPERFRAME_HEADER_LEN, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(VP9_UDC_HEADER_BUF_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(VP9_NUM_FRAME_INFO_BUF * \
CCE_TILE_OFFSET_SIZE, VENUS_DMA_ALIGNMENT) + \
HFI_ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE, \
VENUS_DMA_ALIGNMENT) + HDR10_HIST_EXTRADATA_SIZE
VENUS_DMA_ALIGNMENT) + HDR10_HIST_EXTRADATA_SIZE)
#define HFI_BUFFER_LINE_MP2D(_size, frame_width, frame_height, \
_yuv_bufcount_min, is_opb, num_vpp_pipes) \
@@ -856,7 +862,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
#define QMATRIX_SIZE (sizeof(HFI_U32) * 128 + 256)
#define MP2D_QPDUMP_SIZE 115200
#define HFI_BUFFER_PERSIST_MP2D(_size) \
_size = QMATRIX_SIZE + MP2D_QPDUMP_SIZE;
(_size = QMATRIX_SIZE + MP2D_QPDUMP_SIZE;)
#define AV1D_LCU_MAX_SIZE_PELS 128
#define AV1D_LCU_MIN_SIZE_PELS 64

2
driver/variant/iris3/src/msm_vidc_clock_iris3.c
Voir le fichier

@@ -17,7 +17,7 @@ static u32 calculate_number_mbs_kalama(u32 width, u32 height, u32 lcu_size)
return mbs_width * mbs_height * (lcu_size / 16) * (lcu_size / 16);
}
static int initialize_encoder_complexity_table()
static int initialize_encoder_complexity_table(void)
{
/* Beging Calculate Encoder GOP Complexity Table and HW Floor numbers */
codec_encoder_gop_complexity_table_fp

38
driver/variant/iris33/inc/hfi_buffer_iris33.h
Voir le fichier

@@ -65,7 +65,7 @@ typedef HFI_U32 HFI_BOOL;
min_buf_height_multiple))
#define HFI_NV12_IL_CALC_UV_STRIDE(stride, frame_width, stride_multiple) \
stride = HFI_ALIGN(frame_width, stride_multiple)
(stride = HFI_ALIGN(frame_width, stride_multiple))
#define HFI_NV12_IL_CALC_UV_BUFHEIGHT(buf_height, frame_height, \
min_buf_height_multiple) (buf_height = HFI_ALIGN(((frame_height + 1) \
@@ -127,8 +127,10 @@ typedef HFI_U32 HFI_BOOL;
} while (0)
#define HFI_YUV420_TP10_CALC_Y_STRIDE(stride, frame_width, stride_multiple) \
stride = HFI_ALIGN(frame_width, 192); \
stride = HFI_ALIGN(stride * 4 / 3, stride_multiple)
do { \
stride = HFI_ALIGN(frame_width, 192); \
stride = HFI_ALIGN(stride * 4 / 3, stride_multiple); \
} while (0)
#define HFI_YUV420_TP10_CALC_Y_BUFHEIGHT(buf_height, frame_height, \
min_buf_height_multiple) \
@@ -147,9 +149,11 @@ typedef HFI_U32 HFI_BOOL;
#define HFI_YUV420_TP10_CALC_BUF_SIZE(buf_size, y_buf_size, y_stride,\
y_buf_height, uv_buf_size, uv_stride, uv_buf_height) \
y_buf_size = (y_stride * y_buf_height); \
uv_buf_size = (uv_stride * uv_buf_height); \
buf_size = y_buf_size + uv_buf_size
do { \
y_buf_size = (y_stride * y_buf_height); \
uv_buf_size = (uv_stride * uv_buf_height); \
buf_size = y_buf_size + uv_buf_size \
} while (0)
#define HFI_YUV420_TP10_UBWC_CALC_Y_BUF_SIZE(y_buf_size, y_stride, \
y_buf_height) \
@@ -382,7 +386,9 @@ typedef HFI_U32 HFI_BOOL;
BUFFER_ALIGNMENT_32_BYTES); \
_size = MIN((((_height + 15) >> 4) * 48), H264D_MAX_SLICE) * \
SIZE_H264D_VPP_CMD_PER_BUF; \
if (_size > VPP_CMD_MAX_SIZE) { _size = VPP_CMD_MAX_SIZE; } \
if (_size > VPP_CMD_MAX_SIZE) { \
_size = VPP_CMD_MAX_SIZE; \
} \
} while (0)
#define HFI_BUFFER_COMV_H264D(coMV_size, frame_width, \
@@ -507,11 +513,11 @@ typedef HFI_U32 HFI_BOOL;
#define H264_DISPLAY_BUF_SIZE (3328)
#define SIZE_DOLBY_RPU_METADATA (41 * 1024)
#define HFI_BUFFER_PERSIST_H264D(_size, rpu_enabled) \
_size = HFI_ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + \
(_size = HFI_ALIGN((SIZE_SLIST_BUF_H264 * NUM_SLIST_BUF_H264 + \
H264_DISPLAY_BUF_SIZE * H264_NUM_FRM_INFO + \
NUM_HW_PIC_BUF * SIZE_SEI_USERDATA + \
rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA), \
VENUS_DMA_ALIGNMENT)
VENUS_DMA_ALIGNMENT))
#define LCU_MAX_SIZE_PELS 64
#define LCU_MIN_SIZE_PELS 16
@@ -700,11 +706,11 @@ typedef HFI_U32 HFI_BOOL;
#define H265_NUM_FRM_INFO (48)
#define H265_DISPLAY_BUF_SIZE (3072)
#define HFI_BUFFER_PERSIST_H265D(_size, rpu_enabled) \
_size = HFI_ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + \
(_size = HFI_ALIGN((SIZE_SLIST_BUF_H265 * NUM_SLIST_BUF_H265 + \
H265_NUM_FRM_INFO * H265_DISPLAY_BUF_SIZE + \
H265_NUM_TILE * sizeof(HFI_U32) + NUM_HW_PIC_BUF * SIZE_SEI_USERDATA + \
rpu_enabled * NUM_HW_PIC_BUF * SIZE_DOLBY_RPU_METADATA),\
VENUS_DMA_ALIGNMENT)
VENUS_DMA_ALIGNMENT))
#define SIZE_VPXD_LB_FE_LEFT_CTRL(frame_width, frame_height) \
MAX(((frame_height + 15) >> 4) * \
@@ -781,8 +787,8 @@ typedef HFI_U32 HFI_BOOL;
} while (0)
#define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO 1 / 2
#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO 3 / 2
#define VPX_DECODER_FRAME_BIN_HDR_BUDGET_RATIO (1 / 2)
#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2)
#define HFI_BUFFER_BIN_VP9D(_size, frame_width, frame_height, \
is_interlaced, num_vpp_pipes) \
@@ -816,14 +822,14 @@ typedef HFI_U32 HFI_BOOL;
#define CCE_TILE_OFFSET_SIZE HFI_ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
#define HFI_BUFFER_PERSIST_VP9D(_size) \
_size = HFI_ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, \
(_size = HFI_ALIGN(VP9_NUM_PROBABILITY_TABLE_BUF * VP9_PROB_TABLE_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(HFI_IRIS3_VP9D_COMV_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(MAX_SUPERFRAME_HEADER_LEN, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(VP9_UDC_HEADER_BUF_SIZE, \
VENUS_DMA_ALIGNMENT) + HFI_ALIGN(VP9_NUM_FRAME_INFO_BUF * \
CCE_TILE_OFFSET_SIZE, VENUS_DMA_ALIGNMENT) + \
HFI_ALIGN(VP9_NUM_FRAME_INFO_BUF * VP9_FRAME_INFO_BUF_SIZE, \
VENUS_DMA_ALIGNMENT) + HDR10_HIST_EXTRADATA_SIZE
VENUS_DMA_ALIGNMENT) + HDR10_HIST_EXTRADATA_SIZE)
#define HFI_BUFFER_LINE_MP2D(_size, frame_width, frame_height, \
_yuv_bufcount_min, is_opb, num_vpp_pipes) \
@@ -856,7 +862,7 @@ _yuv_bufcount_min, is_opb, num_vpp_pipes) \
#define QMATRIX_SIZE (sizeof(HFI_U32) * 128 + 256)
#define MP2D_QPDUMP_SIZE 115200
#define HFI_BUFFER_PERSIST_MP2D(_size) \
_size = QMATRIX_SIZE + MP2D_QPDUMP_SIZE;
(_size = QMATRIX_SIZE + MP2D_QPDUMP_SIZE;)
#define AV1D_LCU_MAX_SIZE_PELS 128
#define AV1D_LCU_MIN_SIZE_PELS 64

19
driver/variant/iris33/src/msm_vidc_iris33.c
Voir le fichier

@@ -536,15 +536,16 @@ skip_video_xo_reset:
if (rc)
return rc;
/* remove retain mem and retain peripheral */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
if (rc)
d_vpr_e("%s: set noretain peripheral failed\n", __func__);
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_MEM);
if (rc)
d_vpr_e("%s: set noretain mem failed\n", __func__);
/* remove retain mem and retain peripheral */
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_PERIPH);
if (rc)
d_vpr_e("%s: set noretain peripheral failed\n", __func__);
rc = call_res_op(core, clk_set_flag, core,
"video_cc_mvs0c_clk", MSM_VIDC_CLKFLAG_NORETAIN_MEM);
if (rc)
d_vpr_e("%s: set noretain mem failed\n", __func__);
/* Turn off MVP MVS0C core clock */
rc = call_res_op(core, clk_disable, core, "video_cc_mvs0c_clk");

2
driver/vidc/inc/msm_venc.h
Voir le fichier

@@ -24,7 +24,7 @@ int msm_venc_g_fmt(struct msm_vidc_inst *inst, struct v4l2_format *f);
int msm_venc_s_selection(struct msm_vidc_inst *inst, struct v4l2_selection *s);
int msm_venc_g_selection(struct msm_vidc_inst *inst, struct v4l2_selection *s);
int msm_venc_s_param(struct msm_vidc_inst *inst,
struct v4l2_streamparm *s_parm);
struct v4l2_streamparm *s_parm);
int msm_venc_g_param(struct msm_vidc_inst *inst,
struct v4l2_streamparm *s_parm);
int msm_venc_subscribe_event(struct msm_vidc_inst *inst,

3
driver/vidc/src/msm_vidc_memory_ext.c
Voir le fichier

@@ -165,8 +165,7 @@ static int msm_vidc_memory_alloc_ext(struct msm_vidc_core *core, struct msm_vidc
goto error;
}
if (mem->secure && mem->type == MSM_VIDC_BUF_BIN)
{
if (mem->secure && mem->type == MSM_VIDC_BUF_BIN) {
vmids[0] = VMID_CP_BITSTREAM;
perms[0] = PERM_READ | PERM_WRITE;