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@@ -24,7 +24,12 @@
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#define LANE_MASK_2PH 0x1F
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#define LANE_MASK_3PH 0x7
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+/* Size of CPAS_SEC_LANE_CP_CTRL register mask */
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#define SEC_LANE_CP_REG_LEN 32
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+/*
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+ * PHY index at which CPAS_SEC_LANE_CP_CTRL register mask
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+ * changes depending on PHY HW version
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+ */
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#define MAX_PHY_MSK_PER_REG 4
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/* Mask to enable skew calibration registers */
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@@ -111,19 +116,24 @@ static int32_t cam_csiphy_update_secure_info(
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lane_assign >>= 4;
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}
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- if ((csiphy_dev->hw_version == CSIPHY_VERSION_V201) ||
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- (csiphy_dev->hw_version == CSIPHY_VERSION_V125)) {
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- phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES +
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- CAM_CSIPHY_MAX_CPHY_LANES + 1;
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- } else if (csiphy_dev->hw_version == CSIPHY_VERSION_V121) {
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+ switch (csiphy_dev->hw_version) {
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+ case CSIPHY_VERSION_V201:
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+ case CSIPHY_VERSION_V125:
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phy_mask_len =
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- (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) ?
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- (CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES)
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- : (CAM_CSIPHY_MAX_DPHY_LANES +
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- CAM_CSIPHY_MAX_CPHY_LANES + 1);
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- } else {
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- phy_mask_len = CAM_CSIPHY_MAX_DPHY_LANES +
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- CAM_CSIPHY_MAX_CPHY_LANES;
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+ CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES + 1;
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+ break;
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+ case CSIPHY_VERSION_V121:
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+ case CSIPHY_VERSION_V123:
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+ case CSIPHY_VERSION_V124:
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+ phy_mask_len =
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+ (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) ?
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+ (CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES) :
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+ (CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES + 1);
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+ break;
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+ default:
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+ phy_mask_len =
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+ CAM_CSIPHY_MAX_DPHY_LANES + CAM_CSIPHY_MAX_CPHY_LANES;
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+ break;
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}
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if (csiphy_dev->soc_info.index < MAX_PHY_MSK_PER_REG) {
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