msm: camera: cpas: add camera cesta VCD level dump

This change will help to give information on  camera cesta current clk
operating level.

CRs-Fixed: 3327242
Change-Id: I0422d557985b1044fcd9bab2ce201b8c21e4e295
Signed-off-by: Soumen Ghosh <[email protected]>

drivers/cam_cpas/cam_cpas_hw.c

@@ -2419,7 +2419,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args,
 		if (rc)
 			goto remove_ahb_vote;
 
-		atomic_set(&cpas_core->irq_count, 1);
+		atomic_set(&cpas_core->soc_access_count, 1);
 
 		count = cam_soc_util_regulators_enabled(&cpas_hw->soc_info);
 		if (count > 0)
@@ -2428,7 +2428,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args,
 		rc = cam_cpas_soc_enable_resources(&cpas_hw->soc_info,
 			applied_level);
 		if (rc) {
-			atomic_set(&cpas_core->irq_count, 0);
+			atomic_set(&cpas_core->soc_access_count, 0);
 			CAM_ERR(CAM_CPAS, "enable_resorce failed, rc=%d", rc);
 			goto remove_ahb_vote;
 		}
@@ -2454,7 +2454,7 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args,
 		if (cpas_core->internal_ops.power_on) {
 			rc = cpas_core->internal_ops.power_on(cpas_hw);
 			if (rc) {
-				atomic_set(&cpas_core->irq_count, 0);
+				atomic_set(&cpas_core->soc_access_count, 0);
 				cam_cpas_soc_disable_resources(
 					&cpas_hw->soc_info, true, true);
 				CAM_ERR(CAM_CPAS,
@@ -2463,7 +2463,8 @@ static int cam_cpas_hw_start(void *hw_priv, void *start_args,
 				goto remove_ahb_vote;
 			}
 		}
-		CAM_DBG(CAM_CPAS, "irq_count=%d\n", atomic_read(&cpas_core->irq_count));
+		CAM_DBG(CAM_CPAS, "soc_access_count=%d\n",
+			atomic_read(&cpas_core->soc_access_count));
 
 		if (soc_private->enable_smart_qos)
 			cam_cpas_reset_niu_priorities(cpas_hw);
@@ -2511,9 +2512,9 @@ error:
 	return rc;
 }
 
-static int _check_irq_count(struct cam_cpas *cpas_core)
+static int _check_soc_access_count(struct cam_cpas *cpas_core)
 {
-	return (atomic_read(&cpas_core->irq_count) > 0) ? 0 : 1;
+	return (atomic_read(&cpas_core->soc_access_count) > 0) ? 0 : 1;
 }
 
 static int cam_cpas_util_validate_stop_bw(struct cam_cpas_private_soc *soc_private,
@@ -2659,12 +2660,12 @@ static int cam_cpas_hw_stop(void *hw_priv, void *stop_args,
 		}
 
 		/* Wait for any IRQs still being handled */
-		atomic_dec(&cpas_core->irq_count);
-		result = wait_event_timeout(cpas_core->irq_count_wq,
-			_check_irq_count(cpas_core), HZ);
+		atomic_dec(&cpas_core->soc_access_count);
+		result = wait_event_timeout(cpas_core->soc_access_count_wq,
+			_check_soc_access_count(cpas_core), HZ);
 		if (result == 0) {
-			CAM_ERR(CAM_CPAS, "Wait failed: irq_count=%d",
-				atomic_read(&cpas_core->irq_count));
+			CAM_ERR(CAM_CPAS, "Wait failed: soc_access_count=%d",
+				atomic_read(&cpas_core->soc_access_count));
 		}
 
 		/* try again incase camnoc is still not idle */
@@ -2683,8 +2684,8 @@ static int cam_cpas_hw_stop(void *hw_priv, void *stop_args,
 			CAM_ERR(CAM_CPAS, "disable_resorce failed, rc=%d", rc);
 			goto done;
 		}
-		CAM_DBG(CAM_CPAS, "Disabled all the resources: irq_count=%d",
-			atomic_read(&cpas_core->irq_count));
+		CAM_DBG(CAM_CPAS, "Disabled all the resources: soc_access_count=%d",
+			atomic_read(&cpas_core->soc_access_count));
 
 		count = cam_soc_util_regulators_enabled(&cpas_hw->soc_info);
 		if (count > 0)
@@ -2903,6 +2904,8 @@ static int cam_cpas_log_vote(struct cam_hw_info *cpas_hw, bool ddr_only)
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
 	uint32_t i;
 	struct cam_hw_soc_info *soc_info = &cpas_hw->soc_info;
+	struct cam_camnoc_info *camnoc_info =
+		(struct cam_camnoc_info *) cpas_core->camnoc_info;
 
 	if ((cpas_core->streamon_clients > 0) && soc_private->enable_smart_qos && !ddr_only)
 		cam_cpas_print_smart_qos_priority(cpas_hw);
@@ -2951,6 +2954,46 @@ static int cam_cpas_log_vote(struct cam_hw_info *cpas_hw, bool ddr_only)
 		}
 	}
 
+	if ((cpas_core->streamon_clients > 0) &&
+		cpas_core->regbase_index[CAM_CPAS_REG_CESTA] != -1) {
+		int reg_base_index =
+			cpas_core->regbase_index[CAM_CPAS_REG_CESTA];
+		void __iomem *cesta_base =
+			soc_info->reg_map[reg_base_index].mem_base;
+		uint32_t vcd_base_inc =
+			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
+		uint32_t num_vcds =
+			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.num_vcds;
+		uint32_t vcd_curr_lvl_base =
+			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.reg_offset;
+		uint32_t cesta_vcd_curr_perfol_offset, cesta_vcd_curr_perfol_val;
+
+		if (!atomic_inc_not_zero(&cpas_core->soc_access_count))
+			goto skip_vcd_dump;
+
+		for (i = 0; i <= num_vcds; i++) {
+			if (i == camnoc_info->cesta_info->vcd_info[i].index) {
+				cesta_vcd_curr_perfol_offset = vcd_curr_lvl_base +
+					(vcd_base_inc * i);
+				cesta_vcd_curr_perfol_val =
+					cam_io_r_mb(cesta_base + cesta_vcd_curr_perfol_offset);
+				CAM_INFO(CAM_CPAS,
+					"i=%d, VCD[index=%d, type=%d, name=%s] [offset=0x%x, value=0x%x]",
+					i, camnoc_info->cesta_info->vcd_info[i].index,
+					camnoc_info->cesta_info->vcd_info[i].type,
+					camnoc_info->cesta_info->vcd_info[i].clk,
+					cesta_vcd_curr_perfol_offset,
+					cesta_vcd_curr_perfol_val);
+			} else {
+				CAM_WARN(CAM_CPAS, "cesta vcd index out of range");
+			}
+		}
+
+		atomic_dec(&cpas_core->soc_access_count);
+		wake_up(&cpas_core->soc_access_count_wq);
+	}
+
+skip_vcd_dump:
 	if (ddr_only)
 		return 0;
 
@@ -3110,6 +3153,39 @@ static void cam_cpas_update_monitor_array(struct cam_hw_info *cpas_hw,
 			entry->be_mnoc);
 	}
 
+	if ((cpas_core->streamon_clients > 0) &&
+		cpas_core->regbase_index[CAM_CPAS_REG_CESTA] != -1) {
+		int reg_base_index =
+			cpas_core->regbase_index[CAM_CPAS_REG_CESTA];
+		void __iomem *cesta_base =
+			soc_info->reg_map[reg_base_index].mem_base;
+		uint32_t vcd_base_inc =
+			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
+		uint32_t num_vcds =
+			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.num_vcds;
+		uint32_t vcd_curr_lvl_base =
+			camnoc_info->cesta_info->cesta_reg_info->vcd_currol.reg_offset;
+		uint32_t cesta_vcd_curr_perfol_offset, cesta_vcd_curr_perfol_val;
+
+		if (atomic_inc_not_zero(&cpas_core->soc_access_count)) {
+			for (i = 0; i <= num_vcds; i++) {
+				if (i == camnoc_info->cesta_info->vcd_info[i].index) {
+					cesta_vcd_curr_perfol_offset = vcd_curr_lvl_base +
+						(vcd_base_inc * i);
+					cesta_vcd_curr_perfol_val =
+						cam_io_r_mb(cesta_base +
+						cesta_vcd_curr_perfol_offset);
+					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[i].index =
+						camnoc_info->cesta_info->vcd_info[i].index;
+					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[i]
+						.reg_value = cesta_vcd_curr_perfol_val;
+				}
+			}
+			atomic_dec(&cpas_core->soc_access_count);
+			wake_up(&cpas_core->soc_access_count_wq);
+		}
+	}
+
 	for (i = 0; i < camnoc_info->specific_size; i++) {
 		if ((!camnoc_info->specific[i].enable) ||
 			(!camnoc_info->specific[i].maxwr_low.enable))
@@ -3153,7 +3229,7 @@ static void cam_cpas_dump_monitor_array(
 	struct cam_cpas *cpas_core = (struct cam_cpas *) cpas_hw->core_info;
 	struct cam_cpas_private_soc *soc_private =
 		(struct cam_cpas_private_soc *) cpas_hw->soc_info.soc_private;
-	int i = 0, j = 0;
+	int i = 0, j = 0, k = 0;
 	int64_t state_head = 0;
 	uint32_t index, num_entries, oldest_entry;
 	uint64_t ms, hrs, min, sec;
@@ -3161,6 +3237,9 @@ static void cam_cpas_dump_monitor_array(
 	struct timespec64 curr_timestamp;
 	char log_buf[CAM_CPAS_LOG_BUF_LEN];
 	size_t len;
+	uint8_t vcd_index;
+	struct cam_camnoc_info *camnoc_info =
+		(struct cam_camnoc_info *) cpas_core->camnoc_info;
 
 	if (!cpas_core->full_state_dump)
 		return;
@@ -3235,6 +3314,30 @@ static void cam_cpas_dump_monitor_array(
 				entry->be_ddr, entry->be_mnoc, entry->be_shub);
 		}
 
+		if (cpas_core->regbase_index[CAM_CPAS_REG_CESTA] != -1) {
+			uint32_t vcd_base_inc =
+				camnoc_info->cesta_info->cesta_reg_info->vcd_currol.vcd_base_inc;
+			uint32_t vcd_curr_lvl_base =
+				camnoc_info->cesta_info->cesta_reg_info->vcd_currol.reg_offset;
+			uint32_t reg_offset;
+			uint32_t num_vcds =
+				camnoc_info->cesta_info->cesta_reg_info->vcd_currol.num_vcds;
+
+			for (k = 0; k <= num_vcds; k++) {
+				reg_offset = vcd_curr_lvl_base + (vcd_base_inc * i);
+				vcd_index =
+					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[k].index;
+				CAM_INFO(CAM_CPAS,
+					"VCD[index=%d, type=%d, name=%s] [offset=0x%x, value=0x%x]",
+					vcd_index,
+					camnoc_info->cesta_info->vcd_info[vcd_index].type,
+					camnoc_info->cesta_info->vcd_info[vcd_index].clk,
+					reg_offset,
+					entry->vcd_reg_debug_info.vcd_curr_lvl_debug_info[k]
+					.reg_value);
+			}
+		}
+
 		for (j = 0; j < entry->num_camnoc_lvl_regs; j++) {
 			len += scnprintf((log_buf + len),
 				(CAM_CPAS_LOG_BUF_LEN - len), " %s:[%d %d]",
@@ -3992,8 +4095,8 @@ int cam_cpas_hw_probe(struct platform_device *pdev,
 	soc_private = (struct cam_cpas_private_soc *)
 		cpas_hw->soc_info.soc_private;
 	cpas_core->num_clients = soc_private->num_clients;
-	atomic_set(&cpas_core->irq_count, 0);
-	init_waitqueue_head(&cpas_core->irq_count_wq);
+	atomic_set(&cpas_core->soc_access_count, 0);
+	init_waitqueue_head(&cpas_core->soc_access_count_wq);
 
 	if (internal_ops->setup_regbase) {
 		rc = internal_ops->setup_regbase(&cpas_hw->soc_info,

drivers/cam_cpas/cam_cpas_hw.h

@@ -58,6 +58,7 @@
 #define CAM_CPAS_INC_MONITOR_HEAD(head, ret) \
 	div_u64_rem(atomic64_add_return(1, head),\
 	CAM_CPAS_MONITOR_MAX_ENTRIES, (ret))
+#define CAM_CPAS_MAX_CESTA_VCD_NUM 9
 
 /**
  * enum cam_cpas_access_type - Enum for Register access type
@@ -265,6 +266,23 @@ struct cam_cpas_axi_port_debug_info {
 	bool is_drv_started;
 };
 
+struct cam_cpas_cesta_vcd_curr_lvl_debug_info {
+	uint8_t index;
+	uint32_t reg_value;
+};
+
+/**
+ * struct cam_cpas_cesta_vcd_reg_debug_info : to hold all cesta register information
+ *
+ * @vcd_currol: vcd control reg info
+ *
+ */
+struct cam_cpas_cesta_vcd_reg_debug_info {
+	struct cam_cpas_cesta_vcd_curr_lvl_debug_info
+		vcd_curr_lvl_debug_info[CAM_CPAS_MAX_CESTA_VCD_NUM];
+};
+
+
 /**
  * struct cam_cpas_monitor : CPAS monitor array
  *
@@ -290,6 +308,7 @@ struct cam_cpas_axi_port_debug_info {
  * @camnoc_fill_level: Camnoc fill level register info
  * @rt_wr_niu_pri_lut_low: priority lut low values of RT Wr NIUs
  * @rt_wr_niu_pri_lut_high: priority lut high values of RT Wr NIUs
+ * @vcd_reg_debug_info: vcd reg debug information
  */
 struct cam_cpas_monitor {
 	struct timespec64   timestamp;
@@ -308,6 +327,7 @@ struct cam_cpas_monitor {
 	uint32_t            camnoc_fill_level[CAM_CAMNOC_FILL_LVL_REG_INFO_MAX];
 	uint32_t            rt_wr_niu_pri_lut_low[CAM_CPAS_MAX_RT_WR_NIU_NODES];
 	uint32_t            rt_wr_niu_pri_lut_high[CAM_CPAS_MAX_RT_WR_NIU_NODES];
+	struct cam_cpas_cesta_vcd_reg_debug_info vcd_reg_debug_info;
 };
 
 /**
@@ -331,8 +351,9 @@ struct cam_cpas_monitor {
  * @camnoc_axi_port: CAMNOC AXI port info for a specific camnoc axi index
  * @internal_ops: CPAS HW internal ops
  * @work_queue: Work queue handle
- * @irq_count: atomic irq count
- * @irq_count_wq: wait variable to ensure all irq's are handled
+ * @soc_access_count: atomic soc_access_count count
+ * @soc_access_count_wq: wait variable to ensure CPAS is not stop,
+ *						 while accessing hw through CPAS
  * @dentry: debugfs file entry
  * @ahb_bus_scaling_disable: ahb scaling based on src clk corner for bus
  * @applied_camnoc_axi_rate: applied camnoc axi clock rate through sw, hw clients
@@ -364,8 +385,8 @@ struct cam_cpas {
 	struct cam_cpas_axi_port camnoc_axi_port[CAM_CPAS_MAX_AXI_PORTS];
 	struct cam_cpas_internal_ops internal_ops;
 	struct workqueue_struct *work_queue;
-	atomic_t irq_count;
-	wait_queue_head_t irq_count_wq;
+	atomic_t soc_access_count;
+	wait_queue_head_t soc_access_count_wq;
 	struct dentry *dentry;
 	bool ahb_bus_scaling_disable;
 	struct cam_soc_util_clk_rates applied_camnoc_axi_rate;

drivers/cam_cpas/cpas_top/cam_cpastop_hw.c

@@ -402,6 +402,19 @@ static int cam_cpastop_setup_regbase_indices(struct cam_hw_soc_info *soc_info,
 		regbase_index[CAM_CPAS_REG_RPMH] = -1;
 	}
 
+	/* optional - cesta register map */
+	rc = cam_common_util_get_string_index(soc_info->mem_block_name,
+		soc_info->num_mem_block, "cam_cesta", &index);
+	if ((rc == 0) && (index < num_reg_map)) {
+		regbase_index[CAM_CPAS_REG_CESTA] = index;
+		CAM_DBG(CAM_CPAS, "regbase found for cesta, rc=%d, %d %d",
+			rc, index, num_reg_map);
+	} else {
+		CAM_DBG(CAM_CPAS, "regbase not found for cesta, rc=%d, %d %d",
+			rc, index, num_reg_map);
+		regbase_index[CAM_CPAS_REG_CESTA] = -1;
+	}
+
 	return 0;
 }
 
@@ -672,7 +685,7 @@ static void cam_cpastop_work(struct work_struct *work)
 	cpas_core = (struct cam_cpas *) cpas_hw->core_info;
 	soc_info = &cpas_hw->soc_info;
 
-	if (!atomic_inc_not_zero(&cpas_core->irq_count)) {
+	if (!atomic_inc_not_zero(&cpas_core->soc_access_count)) {
 		CAM_ERR(CAM_CPAS, "CPAS off");
 		return;
 	}
@@ -725,9 +738,9 @@ static void cam_cpastop_work(struct work_struct *work)
 				~camnoc_info->irq_err[i].sbm_port;
 		}
 	}
-	atomic_dec(&cpas_core->irq_count);
-	wake_up(&cpas_core->irq_count_wq);
-	CAM_DBG(CAM_CPAS, "irq_count=%d\n", atomic_read(&cpas_core->irq_count));
+	atomic_dec(&cpas_core->soc_access_count);
+	wake_up(&cpas_core->soc_access_count_wq);
+	CAM_DBG(CAM_CPAS, "soc_access_count=%d\n", atomic_read(&cpas_core->soc_access_count));
 
 	if (payload->irq_status)
 		CAM_ERR(CAM_CPAS, "IRQ not handled irq_status=0x%x",
@@ -745,7 +758,7 @@ static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data)
 	struct cam_cpas_work_payload *payload;
 	struct cam_cpas_irq_data irq_data;
 
-	if (!atomic_inc_not_zero(&cpas_core->irq_count)) {
+	if (!atomic_inc_not_zero(&cpas_core->soc_access_count)) {
 		CAM_ERR(CAM_CPAS, "CPAS off");
 		return IRQ_HANDLED;
 	}
@@ -805,8 +818,8 @@ static irqreturn_t cam_cpastop_handle_irq(int irq_num, void *data)
 	queue_work(cpas_core->work_queue, &payload->work);
 
 done:
-	atomic_dec(&cpas_core->irq_count);
-	wake_up(&cpas_core->irq_count_wq);
+	atomic_dec(&cpas_core->soc_access_count);
+	wake_up(&cpas_core->soc_access_count_wq);
 
 	return IRQ_HANDLED;
 }

drivers/cam_cpas/cpas_top/cam_cpastop_hw.h

@@ -347,6 +347,70 @@ struct cam_cpas_test_irq_info {
 	uint32_t sbm_clear_mask;
 };
 
+/**
+ * struct cam_cpas_cesta_crm_type : CESTA crm type information
+ *
+ * @CAM_CESTA_CRMB: CRM for bandwidth
+ * @CAM_CESTA_CRMC: CRM for clocks
+ *
+ */
+enum cam_cpas_cesta_crm_type {
+	CAM_CESTA_CRMB = 0,
+	CAM_CESTA_CRMC,
+};
+
+/**
+ * struct cam_vcd_info : cpas vcd(virtual clk domain) information
+ *
+ * @vcd_index: vcd number of each clk
+ * @type: type of clk domain CESTA_CRMB, CESTA_CRMC
+ * @clk_name: name of each vcd clk, exmp: cam_cc_ife_0_clk_src
+ *
+ */
+struct cam_cpas_vcd_info {
+	uint8_t index;
+	enum cam_cpas_cesta_crm_type type;
+	const char *clk;
+};
+
+/**
+ * struct cam_cpas_cesta_vcd_curr_lvl : cesta vcd operating level information
+ *
+ * @reg_offset: register offset
+ * @vcd_base_inc: each vcd base addr offset
+ * @num_vcds: number of vcds
+ *
+ */
+struct cam_cpas_cesta_vcd_curr_lvl {
+	uint32_t reg_offset;
+	uint32_t vcd_base_inc;
+	uint8_t num_vcds;
+};
+
+/**
+ * struct cam_cpas_cesta_vcd_reg_info : to hold all cesta register information
+ *
+ * @vcd_currol: vcd current perf level reg info
+ *
+ */
+struct cam_cpas_cesta_vcd_reg_info {
+	struct cam_cpas_cesta_vcd_curr_lvl vcd_currol;
+};
+
+/**
+ * struct cam_cpas_cesta_info : to hold all cesta register information
+ *
+ * @vcd_info: vcd info
+ * @num_vcds: number of vcds
+ * @cesta_reg_info: cesta vcds reg info
+ *
+ */
+struct cam_cpas_cesta_info {
+	struct cam_cpas_vcd_info *vcd_info;
+	int num_vcds;
+	struct cam_cpas_cesta_vcd_reg_info *cesta_reg_info;
+};
+
 /**
  * struct cam_camnoc_info : Overall CAMNOC settings info
  *
@@ -358,6 +422,7 @@ struct cam_cpas_test_irq_info {
  * @err_logger: Pointer to CAMNOC IRQ Error logger read registers
  * @errata_wa_list: HW Errata workaround info
  * @test_irq_info: CAMNOC Test IRQ info
+ * @cesta_info: cpas cesta reg info
  *
  */
 struct cam_camnoc_info {
@@ -369,6 +434,7 @@ struct cam_camnoc_info {
 	struct cam_camnoc_err_logger_info *err_logger;
 	struct cam_cpas_hw_errata_wa_list *errata_wa_list;
 	struct cam_cpas_test_irq_info test_irq_info;
+	struct cam_cpas_cesta_info *cesta_info;
 };
 
 /**

drivers/cam_cpas/cpas_top/cpastop_v880_100.h

@@ -1275,6 +1275,51 @@ static struct cam_cpas_hw_errata_wa_list cam880_cpas100_errata_wa_list = {
 	},
 };
 
+static struct cam_cpas_cesta_vcd_reg_info cam_cpas_v880_100_cesta_reg_info = {
+	.vcd_currol = {
+		.reg_offset = 0x300c,
+		.vcd_base_inc = 0x200,
+		.num_vcds = 8,
+	},
+
+};
+
+static struct cam_cpas_vcd_info cam_v880_100_vcd_info[] = {
+	{
+		.index = 0, .type = CAM_CESTA_CRMC, .clk = "cam_cc_ife_0_clk_src",
+	},
+	{
+		.index = 1, .type = CAM_CESTA_CRMC, .clk = "cam_cc_ife_1_clk_src",
+	},
+	{
+		.index = 2, .type = CAM_CESTA_CRMC, .clk = "cam_cc_ife_2_clk_src",
+	},
+	{
+		.index = 3, .type = CAM_CESTA_CRMC, .clk = "cam_cc_sfe_0_clk_src",
+	},
+	{
+		.index = 4, .type = CAM_CESTA_CRMC, .clk = "cam_cc_sfe_1_clk_src",
+	},
+	{
+		.index = 5, .type = CAM_CESTA_CRMC, .clk = "cam_cc_sfe_2_clk_src",
+	},
+	{
+		.index = 6, .type = CAM_CESTA_CRMC, .clk = "cam_cc_csid_clk_src",
+	},
+	{
+		.index = 7, .type = CAM_CESTA_CRMC, .clk = "cam_cc_cphy_rx_clk_src",
+	},
+	{
+		.index = 8, .type = CAM_CESTA_CRMB, .clk = "cam_cc_camnoc_axi_rt_clk_src",
+	},
+};
+
+static struct cam_cpas_cesta_info cam_v880_cesta_info = {
+	 .vcd_info = &cam_v880_100_vcd_info[0],
+	 .num_vcds = ARRAY_SIZE(cam_v880_100_vcd_info),
+	 .cesta_reg_info = &cam_cpas_v880_100_cesta_reg_info,
+};
+
 static struct cam_camnoc_info cam880_cpas100_camnoc_info = {
 	.specific = &cam_cpas_v880_100_camnoc_specific[0],
 	.specific_size = ARRAY_SIZE(cam_cpas_v880_100_camnoc_specific),
@@ -1286,7 +1331,8 @@ static struct cam_camnoc_info cam880_cpas100_camnoc_info = {
 	.test_irq_info = {
 		.sbm_enable_mask = 0x80,
 		.sbm_clear_mask = 0x4,
-	}
+	},
+	.cesta_info = &cam_v880_cesta_info,
 };
 
 static struct cam_cpas_camnoc_qchannel cam880_cpas100_qchannel_info = {

drivers/cam_cpas/include/cam_cpas_api.h

@@ -50,6 +50,7 @@ enum cam_cpas_reg_base {
 	CAM_CPAS_REG_CAMNOC,
 	CAM_CPAS_REG_CAMSS,
 	CAM_CPAS_REG_RPMH,
+	CAM_CPAS_REG_CESTA,
 	CAM_CPAS_REG_MAX
 };