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qcacmn: Parse 64-bit TLVs in monitor status ring for WCN7850

In WCN7850, the tlv header width is 64-bit and the tlv header
start is 8-byte aligned inside the monitor status ring desc.

Add changes to parse the monitor status ring TLV according
to the TLV header width.

Change-Id: I19860b871abbc3037174b9d0ae5ed6e52b1eb736
CRs-Fixed: 3084443
Este cometimento está contido em:
Rakesh Pillai
2021-11-26 02:01:21 -08:00
cometido por Madan Koyyalamudi
ascendente 0115477838
cometimento 63ea23ade1
6 ficheiros modificados com 81 adições e 12 eliminações

Ver ficheiro

@@ -368,7 +368,8 @@ dp_rx_mon_status_process_tlv(struct dp_soc *soc, struct dp_intr *int_ctx,
ppdu_info,
tlv_status);
rx_tlv = hal_rx_status_get_next_tlv(rx_tlv);
rx_tlv = hal_rx_status_get_next_tlv(rx_tlv,
mon_pdev->is_tlv_hdr_64_bit);
if ((rx_tlv - rx_tlv_start) >=
RX_MON_STATUS_BUF_SIZE)

Ver ficheiro

@@ -4500,6 +4500,29 @@ QDF_STATUS dp_mon_soc_cfg_init(struct dp_soc *soc)
return QDF_STATUS_SUCCESS;
}
/**
* dp_mon_pdev_per_target_config() - Target specific monitor pdev configuration
* @pdev: PDEV handle [Should be valid]
*
* Return: None
*/
static void dp_mon_pdev_per_target_config(struct dp_pdev *pdev)
{
struct dp_soc *soc = pdev->soc;
struct dp_mon_pdev *mon_pdev = pdev->monitor_pdev;
int target_type;
target_type = hal_get_target_type(soc->hal_soc);
switch (target_type) {
case TARGET_TYPE_WCN7850:
mon_pdev->is_tlv_hdr_64_bit = true;
break;
default:
mon_pdev->is_tlv_hdr_64_bit = false;
break;
}
}
QDF_STATUS dp_mon_pdev_attach(struct dp_pdev *pdev)
{
struct dp_soc *soc;
@@ -4548,6 +4571,7 @@ QDF_STATUS dp_mon_pdev_attach(struct dp_pdev *pdev)
}
pdev->monitor_pdev = mon_pdev;
dp_mon_pdev_per_target_config(pdev);
return QDF_STATUS_SUCCESS;
fail3:

Ver ficheiro

@@ -795,6 +795,7 @@ struct dp_mon_pdev {
/* enable spcl vap stats reset on ch change */
bool reset_scan_spcl_vap_stats_enable;
#endif
bool is_tlv_hdr_64_bit;
};
struct dp_mon_vdev {

Ver ficheiro

@@ -415,11 +415,11 @@ hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo,
struct hal_rx_ppdu_info *ppdu_info =
(struct hal_rx_ppdu_info *)ppduinfo;
tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr);
tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
tlv_tag = HAL_RX_GET_USER_TLV64_TYPE(rx_tlv_hdr);
user_id = HAL_RX_GET_USER_TLV64_USERID(rx_tlv_hdr);
tlv_len = HAL_RX_GET_USER_TLV64_LEN(rx_tlv_hdr);
rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE;
qdf_trace_hex_dump(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
rx_tlv, tlv_len);

Ver ficheiro

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2017-2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -50,6 +51,23 @@
HAL_RX_USER_TLV32_USERID_MASK) >> \
HAL_RX_USER_TLV32_USERID_LSB)
#define HAL_RX_TLV64_HDR_SIZE 8
#define HAL_RX_GET_USER_TLV64_TYPE(rx_status_tlv_ptr) \
((*((uint64_t *)(rx_status_tlv_ptr)) & \
HAL_RX_USER_TLV64_TYPE_MASK) >> \
HAL_RX_USER_TLV64_TYPE_LSB)
#define HAL_RX_GET_USER_TLV64_LEN(rx_status_tlv_ptr) \
((*((uint64_t *)(rx_status_tlv_ptr)) & \
HAL_RX_USER_TLV64_LEN_MASK) >> \
HAL_RX_USER_TLV64_LEN_LSB)
#define HAL_RX_GET_USER_TLV64_USERID(rx_status_tlv_ptr) \
((*((uint64_t *)(rx_status_tlv_ptr)) & \
HAL_RX_USER_TLV64_USERID_MASK) >> \
HAL_RX_USER_TLV64_USERID_LSB)
#define HAL_TLV_STATUS_PPDU_NOT_DONE 0
#define HAL_TLV_STATUS_PPDU_DONE 1
#define HAL_TLV_STATUS_BUF_DONE 2
@@ -721,11 +739,20 @@ hal_get_rx_status_buf_size(void) {
}
static inline uint8_t*
hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
uint32_t tlv_len, tlv_tag;
hal_rx_status_get_next_tlv(uint8_t *rx_tlv, bool is_tlv_hdr_64_bit) {
uint32_t tlv_len, tlv_tag, tlv_hdr_size;
tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
if (is_tlv_hdr_64_bit) {
tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
tlv_hdr_size = HAL_RX_TLV64_HDR_SIZE;
} else {
tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv);
tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv);
tlv_hdr_size = HAL_RX_TLV32_HDR_SIZE;
}
/* The actual length of PPDU_END is the combined length of many PHY
* TLVs that follow. Skip the TLV header and
@@ -735,8 +762,10 @@ hal_rx_status_get_next_tlv(uint8_t *rx_tlv) {
if (tlv_tag == WIFIRX_PPDU_END_E)
tlv_len = sizeof(struct rx_rxpcu_classification_overview);
return (uint8_t *)(((unsigned long)(rx_tlv + tlv_len +
HAL_RX_TLV32_HDR_SIZE + 3)) & (~((unsigned long)3)));
return (uint8_t *)(uintptr_t)qdf_align((uint64_t)((uintptr_t)rx_tlv +
tlv_len +
tlv_hdr_size),
tlv_hdr_size);
}
/**

Ver ficheiro

@@ -1,5 +1,6 @@
/*
* Copyright (c) 2021 The Linux Foundation. All rights reserved.
* Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Permission to use, copy, modify, and/or distribute this software for
* any purpose with or without fee is hereby granted, provided that the
@@ -19,7 +20,7 @@
#ifndef _HAL_RX_HW_DEFINES_H_
#define _HAL_RX_HW_DEFINES_H_
/* Unified desc fields */
/* Unified 32-bit desc fields */
#define HAL_RX_USER_TLV32_TYPE_OFFSET 0x00000000
#define HAL_RX_USER_TLV32_TYPE_LSB 1
#define HAL_RX_USER_TLV32_TYPE_MASK 0x000003FE
@@ -32,6 +33,19 @@
#define HAL_RX_USER_TLV32_USERID_LSB 26
#define HAL_RX_USER_TLV32_USERID_MASK 0xFC000000
/* Unified 64-bit desc fields */
#define HAL_RX_USER_TLV64_TYPE_OFFSET 0x0000000000000000
#define HAL_RX_USER_TLV64_TYPE_LSB 1
#define HAL_RX_USER_TLV64_TYPE_MASK 0x00000000000003FE
#define HAL_RX_USER_TLV64_LEN_OFFSET 0x0000000000000000
#define HAL_RX_USER_TLV64_LEN_LSB 10
#define HAL_RX_USER_TLV64_LEN_MASK 0x00000000003FFC00
#define HAL_RX_USER_TLV64_USERID_OFFSET 0x0000000000000000
#define HAL_RX_USER_TLV64_USERID_LSB 26
#define HAL_RX_USER_TLV64_USERID_MASK 0x00000000FC000000
/* rx mpdu desc info */
#define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_OFFSET 0x0
#define HAL_RX_MPDU_DESC_INFO_MSDU_COUNT_LSB 0