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Merge "ipa: added missing ipa 5.0 registers support"

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This commit is contained in:
qctecmdr
2021-11-04 15:02:01 -07:00
committed by Gerrit - the friendly Code Review server
parent 9861c7b45a 5f16b09c14
commit 635d6a65f5
3 changed files with 97 additions and 0 deletions
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5
drivers/platform/msm/ipa/ipa_v3/dump/ipa5.0/ipa_hw_common_ex.h
View File

@@ -467,6 +467,11 @@ enum ipa_hw_irq_srcs_e {
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC 2
/*
* Total number of event ring contexts that need to be saved for Q6
*/
#define IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6 11
/*
* Total number of endpoints for which ipa_reg_save.pipes[endp_number]
* are not saved by default (only if ipa_cfg.gen.full_reg_trace =

22
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.c
View File

@@ -1199,6 +1199,28 @@ void ipa_save_registers(void)
n + IPA_GSI_OFFSET_WORDS_SCRATCH5);
}
for (i = 0; i < IPA_HW_REG_SAVE_GSI_NUM_CH_CNTXT_Q6; i++) {
u32 phys_ch_idx = ipa_reg_save.gsi.ch_cntxt.q6[
i].gsi_map_ee_n_ch_k_vp_table.phy_ch;
u32 n = phys_ch_idx * IPA_REG_SAVE_BYTES_PER_CHNL_SHRAM;
if (!ipa_reg_save.gsi.ch_cntxt.q6[
i].gsi_map_ee_n_ch_k_vp_table.valid)
continue;
ipa_reg_save.gsi.ch_cntxt.q6[
i].mcs_channel_scratch.scratch4.shram =
IPA_READ_1xVECTOR_REG(
GSI_SHRAM_n,
n + IPA_GSI_OFFSET_WORDS_SCRATCH4);
ipa_reg_save.gsi.ch_cntxt.q6[
i].mcs_channel_scratch.scratch5.shram =
IPA_READ_1xVECTOR_REG(
GSI_SHRAM_n,
n + IPA_GSI_OFFSET_WORDS_SCRATCH5);
}
/*
* On targets that support SSR, we generally want to disable
* the following reg save functionality as it may cause stalls

70
drivers/platform/msm/ipa/ipa_v3/dump/ipa_reg_dump.h
View File

@@ -474,6 +474,39 @@ struct map_src_dst_addr_s {
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.uc[1].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[0].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[1].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[2].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[3].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[4].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[5].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[6].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[7].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[8].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[9].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \
(u32 *)&ipa_reg_save.gsi.ch_cntxt.q6[10].var_name, \
GEN_REG_ATTR(reg_name) }
#define IPA_REG_SAVE_CFG_ENTRY_GSI_EVT_CNTXT(reg_name, var_name) \
@@ -536,6 +569,39 @@ struct map_src_dst_addr_s {
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_REG_SAVE_HWP_GSI_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.uc[0].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 0), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[0].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 1), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[1].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 2), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[2].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 3), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[3].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 4), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[4].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 5), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[5].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 6), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[6].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 7), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[7].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 8), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[8].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 9), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[9].var_name, \
GEN_REG_ATTR(reg_name) }, \
{ GEN_2xVECTOR_REG_OFST(reg_name, IPA_HW_Q6_EE, 10), \
(u32 *)&ipa_reg_save.gsi.evt_cntxt.q6[10].var_name, \
GEN_REG_ATTR(reg_name) }
/*
@@ -1770,6 +1836,10 @@ struct ipa_reg_save_gsi_evt_cntxt_s {
a7[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_A7];
struct ipa_reg_save_gsi_evt_cntxt_per_ep_s
uc[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_UC];
#ifdef CONFIG_IPA3_REGDUMP_IPA_5_0
struct ipa_reg_save_gsi_evt_cntxt_per_ep_s
q6[IPA_HW_REG_SAVE_GSI_NUM_EVT_CNTXT_Q6];
#endif
};
/* Top level IPA register save data struct */