disp: msm: sde: support a single dsc setup function
This change adds a single setup function for different dsc topologies. This simplifies the dsc code and allows for additional topologies support. Change-Id: Iaaddd6e51a2fa53d113d618328dee2bf63e30cab Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
This commit is contained in:
Abhijit Kulkarni
@@ -54,7 +54,7 @@ bool sde_encoder_is_dsc_merge(struct drm_encoder *drm_enc)
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return false;
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}
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static int _sde_encoder_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
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static int _dce_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
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int pic_width, int pic_height)
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{
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@@ -78,7 +78,7 @@ static int _sde_encoder_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
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return 0;
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}
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static void _sde_encoder_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc,
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static void _dce_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc,
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int intf_width)
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{
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int slice_per_pkt, slice_per_intf;
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@@ -111,7 +111,7 @@ static void _sde_encoder_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc,
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dsc->pkt_per_line = slice_per_intf / slice_per_pkt;
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}
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static int _sde_encoder_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
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static int _dce_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
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int enc_ip_width)
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{
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int max_ssm_delay, max_se_size, obuf_latency;
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@@ -139,7 +139,7 @@ static int _sde_encoder_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
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return 0;
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}
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static bool _sde_encoder_dsc_ich_reset_override_needed(bool pu_en,
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static bool _dce_dsc_ich_reset_override_needed(bool pu_en,
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struct msm_display_dsc_info *dsc)
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{
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/*
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@@ -161,7 +161,7 @@ static bool _sde_encoder_dsc_ich_reset_override_needed(bool pu_en,
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(dsc->slice_width == dsc->pic_width);
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}
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static void _sde_encoder_dsc_pipe_cfg(struct sde_hw_dsc *hw_dsc,
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static void _dce_dsc_pipe_cfg(struct sde_hw_dsc *hw_dsc,
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struct sde_hw_pingpong *hw_pp, struct msm_display_dsc_info *dsc,
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u32 common_mode, bool ich_reset, bool enable,
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struct sde_hw_pingpong *hw_dsc_pp)
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@@ -201,157 +201,139 @@ static void _sde_encoder_dsc_pipe_cfg(struct sde_hw_dsc *hw_dsc,
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hw_dsc_pp->ops.enable_dsc(hw_dsc_pp);
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}
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static int _sde_encoder_dsc_n_lm_1_enc_1_intf(struct sde_encoder_virt *sde_enc)
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{
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int this_frame_slices;
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int intf_ip_w, enc_ip_w;
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int ich_res, dsc_common_mode = 0;
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struct sde_hw_pingpong *hw_pp = sde_enc->hw_pp[0];
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struct sde_hw_pingpong *hw_dsc_pp = sde_enc->hw_dsc_pp[0];
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struct sde_hw_dsc *hw_dsc = sde_enc->hw_dsc[0];
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struct sde_encoder_phys *enc_master = sde_enc->cur_master;
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const struct sde_rect *roi = &sde_enc->cur_conn_roi;
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struct msm_display_dsc_info *dsc = NULL;
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struct sde_hw_ctl *hw_ctl;
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struct sde_ctl_dsc_cfg cfg;
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if (hw_dsc == NULL || hw_pp == NULL || !enc_master) {
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SDE_ERROR_DCE(sde_enc, "invalid params for DSC\n");
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return -EINVAL;
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}
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hw_ctl = enc_master->hw_ctl;
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memset(&cfg, 0, sizeof(cfg));
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dsc = &sde_enc->mode_info.comp_info.dsc_info;
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_sde_encoder_dsc_update_pic_dim(dsc, roi->w, roi->h);
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this_frame_slices = roi->w / dsc->slice_width;
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intf_ip_w = this_frame_slices * dsc->slice_width;
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_sde_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
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enc_ip_w = intf_ip_w;
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_sde_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
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ich_res = _sde_encoder_dsc_ich_reset_override_needed(false, dsc);
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if (enc_master->intf_mode == INTF_MODE_VIDEO)
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dsc_common_mode = DSC_MODE_VIDEO;
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SDE_DEBUG_DCE(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
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roi->w, roi->h, dsc_common_mode);
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SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h, dsc_common_mode);
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_sde_encoder_dsc_pipe_cfg(hw_dsc, hw_pp, dsc, dsc_common_mode,
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ich_res, true, hw_dsc_pp);
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cfg.dsc[cfg.dsc_count++] = hw_dsc->idx;
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/* setup dsc active configuration in the control path */
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if (hw_ctl->ops.setup_dsc_cfg) {
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hw_ctl->ops.setup_dsc_cfg(hw_ctl, &cfg);
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SDE_DEBUG_DCE(sde_enc,
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"setup dsc_cfg hw_ctl[%d], count:%d,dsc[0]:%d, dsc[1]:%d\n",
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hw_ctl->idx,
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cfg.dsc_count,
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cfg.dsc[0],
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cfg.dsc[1]);
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}
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if (hw_ctl->ops.update_bitmask_dsc)
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hw_ctl->ops.update_bitmask_dsc(hw_ctl, hw_dsc->idx, 1);
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return 0;
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}
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static int _sde_encoder_dsc_2_lm_2_enc_2_intf(struct sde_encoder_virt *sde_enc,
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static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
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struct sde_encoder_kickoff_params *params)
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{
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int this_frame_slices;
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int intf_ip_w, enc_ip_w;
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int ich_res, dsc_common_mode;
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struct sde_encoder_phys *enc_master = sde_enc->cur_master;
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const struct sde_rect *roi = &sde_enc->cur_conn_roi;
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struct sde_kms *sde_kms;
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struct msm_drm_private *priv;
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struct drm_encoder *drm_enc;
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struct drm_connector *drm_conn;
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struct sde_encoder_phys *enc_master;
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struct sde_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
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struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
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struct sde_hw_pingpong *hw_dsc_pp[MAX_CHANNELS_PER_ENC];
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struct msm_display_dsc_info dsc[MAX_CHANNELS_PER_ENC];
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bool half_panel_partial_update;
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struct sde_hw_ctl *hw_ctl = enc_master->hw_ctl;
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struct msm_display_dsc_info *dsc = NULL;
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enum sde_rm_topology_name topology;
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const struct sde_rm_topology_def *def;
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const struct sde_rect *roi;
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struct sde_hw_ctl *hw_ctl;
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struct sde_ctl_dsc_cfg cfg;
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bool half_panel_partial_update, dsc_merge;
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int this_frame_slices;
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int intf_ip_w, enc_ip_w;
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int num_intf, num_dsc;
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int ich_res;
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int dsc_common_mode = 0;
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int i;
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memset(&cfg, 0, sizeof(cfg));
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if (!sde_enc || !params || !sde_enc->phys_encs[0] ||
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!sde_enc->phys_encs[0]->connector)
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return -EINVAL;
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drm_conn = sde_enc->phys_encs[0]->connector;
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drm_enc = &sde_enc->base;
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priv = drm_enc->dev->dev_private;
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sde_kms = to_sde_kms(priv->kms);
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topology = sde_connector_get_topology_name(drm_conn);
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if (topology == SDE_RM_TOPOLOGY_NONE) {
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SDE_ERROR_DCE(sde_enc, "topology not set yet\n");
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return -EINVAL;
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}
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SDE_DEBUG_DCE(sde_enc, "topology:%d\n", topology);
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if (sde_kms_rect_is_equal(&sde_enc->cur_conn_roi,
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&sde_enc->prv_conn_roi))
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return 0;
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SDE_EVT32(DRMID(&sde_enc->base), topology,
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sde_enc->cur_conn_roi.x,
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sde_enc->cur_conn_roi.y,
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sde_enc->cur_conn_roi.w,
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sde_enc->cur_conn_roi.h,
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sde_enc->prv_conn_roi.x,
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sde_enc->prv_conn_roi.y,
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sde_enc->prv_conn_roi.w,
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sde_enc->prv_conn_roi.h,
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sde_enc->cur_master->cached_mode.hdisplay,
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sde_enc->cur_master->cached_mode.vdisplay);
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memset(&cfg, 0, sizeof(cfg));
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enc_master = sde_enc->cur_master;
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roi = &sde_enc->cur_conn_roi;
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hw_ctl = enc_master->hw_ctl;
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dsc = &sde_enc->mode_info.comp_info.dsc_info;
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def = sde_rm_topology_get_topology_def(&sde_kms->rm, topology);
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if (IS_ERR_OR_NULL(def))
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return -EINVAL;
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num_dsc = def->num_comp_enc;
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num_intf = def->num_intf;
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/*
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* If this encoder is driving more than one DSC encoder, they
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* operate in tandem, same pic dimension needs to be used by
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* each of them.(pp-split is assumed to be not supported)
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*/
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_dce_dsc_update_pic_dim(dsc, roi->w, roi->h);
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half_panel_partial_update = (num_dsc > 1) ?
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(hweight_long(params->affected_displays) != num_dsc) :
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false;
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dsc_merge = (num_dsc > num_intf) ? true : false;
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if (!half_panel_partial_update)
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dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
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if (dsc_merge)
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dsc_common_mode |= DSC_MODE_MULTIPLEX;
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if (enc_master->intf_mode == INTF_MODE_VIDEO)
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dsc_common_mode |= DSC_MODE_VIDEO;
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this_frame_slices = roi->w / dsc->slice_width;
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intf_ip_w = this_frame_slices * dsc->slice_width;
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if ((!half_panel_partial_update) && (num_intf > 1))
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intf_ip_w /= 2;
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_dce_dsc_pclk_param_calc(dsc, intf_ip_w);
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/*
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* in dsc merge case: when using 2 encoders for the same stream,
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* no. of slices need to be same on both the encoders.
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*/
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enc_ip_w = intf_ip_w;
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if (dsc_merge)
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enc_ip_w = intf_ip_w / 2;
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_dce_dsc_initial_line_calc(dsc, enc_ip_w);
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/*
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* __is_ich_reset_override_needed should be called only after
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* updating pic dimension, mdss_panel_dsc_update_pic_dim.
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*/
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ich_res = _dce_dsc_ich_reset_override_needed(
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half_panel_partial_update, dsc);
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SDE_DEBUG_DCE(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
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roi->w, roi->h, dsc_common_mode);
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for (i = 0; i < num_dsc; i++) {
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bool active = !!((1 << i) & params->affected_displays);
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for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
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hw_pp[i] = sde_enc->hw_pp[i];
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hw_dsc[i] = sde_enc->hw_dsc[i];
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hw_dsc_pp[i] = sde_enc->hw_dsc_pp[i];
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if (!hw_pp[i] || !hw_dsc[i] || !hw_dsc_pp[i]) {
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SDE_ERROR_DCE(sde_enc, "invalid params for DSC\n");
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SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h,
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dsc_common_mode, i, active);
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return -EINVAL;
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}
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}
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half_panel_partial_update =
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hweight_long(params->affected_displays) == 1;
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dsc_common_mode = 0;
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if (!half_panel_partial_update)
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dsc_common_mode |= DSC_MODE_SPLIT_PANEL;
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if (enc_master->intf_mode == INTF_MODE_VIDEO)
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dsc_common_mode |= DSC_MODE_VIDEO;
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memcpy(&dsc[0], &sde_enc->mode_info.comp_info.dsc_info, sizeof(dsc[0]));
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memcpy(&dsc[1], &sde_enc->mode_info.comp_info.dsc_info, sizeof(dsc[1]));
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/*
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* Since both DSC use same pic dimension, set same pic dimension
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* to both DSC structures.
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*/
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_sde_encoder_dsc_update_pic_dim(&dsc[0], roi->w, roi->h);
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_sde_encoder_dsc_update_pic_dim(&dsc[1], roi->w, roi->h);
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this_frame_slices = roi->w / dsc[0].slice_width;
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intf_ip_w = this_frame_slices * dsc[0].slice_width;
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if (!half_panel_partial_update)
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intf_ip_w /= 2;
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/*
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* In this topology when both interfaces are active, they have same
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* load so intf_ip_w will be same.
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*/
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_sde_encoder_dsc_pclk_param_calc(&dsc[0], intf_ip_w);
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_sde_encoder_dsc_pclk_param_calc(&dsc[1], intf_ip_w);
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/*
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* In this topology, since there is no dsc_merge, uncompressed input
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* to encoder and interface is same.
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*/
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enc_ip_w = intf_ip_w;
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_sde_encoder_dsc_initial_line_calc(&dsc[0], enc_ip_w);
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_sde_encoder_dsc_initial_line_calc(&dsc[1], enc_ip_w);
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/*
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* __is_ich_reset_override_needed should be called only after
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* updating pic dimension, mdss_panel_dsc_update_pic_dim.
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*/
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ich_res = _sde_encoder_dsc_ich_reset_override_needed(
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half_panel_partial_update, &dsc[0]);
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SDE_DEBUG_DCE(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
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roi->w, roi->h, dsc_common_mode);
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for (i = 0; i < sde_enc->num_phys_encs; i++) {
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bool active = !!((1 << i) & params->affected_displays);
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SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h,
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dsc_common_mode, i, active);
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_sde_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], &dsc[i],
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_dce_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc,
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dsc_common_mode, ich_res, active, hw_dsc_pp[i]);
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if (active) {
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@@ -381,155 +363,6 @@ static int _sde_encoder_dsc_2_lm_2_enc_2_intf(struct sde_encoder_virt *sde_enc,
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return 0;
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}
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static int _sde_encoder_dsc_2_lm_2_enc_1_intf(struct sde_encoder_virt *sde_enc,
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struct sde_encoder_kickoff_params *params)
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{
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int this_frame_slices;
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int intf_ip_w, enc_ip_w;
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int ich_res, dsc_common_mode;
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struct sde_encoder_phys *enc_master = sde_enc->cur_master;
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const struct sde_rect *roi = &sde_enc->cur_conn_roi;
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struct sde_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
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struct sde_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
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struct sde_hw_pingpong *hw_dsc_pp[MAX_CHANNELS_PER_ENC];
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struct msm_display_dsc_info *dsc = NULL;
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bool half_panel_partial_update;
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struct sde_hw_ctl *hw_ctl = enc_master->hw_ctl;
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struct sde_ctl_dsc_cfg cfg;
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int i;
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memset(&cfg, 0, sizeof(cfg));
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for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
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hw_pp[i] = sde_enc->hw_pp[i];
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hw_dsc[i] = sde_enc->hw_dsc[i];
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hw_dsc_pp[i] = sde_enc->hw_dsc_pp[i];
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if (!hw_pp[i] || !hw_dsc[i] || !hw_dsc_pp[i]) {
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SDE_ERROR_DCE(sde_enc, "invalid params for DSC\n");
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return -EINVAL;
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}
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}
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dsc = &sde_enc->mode_info.comp_info.dsc_info;
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half_panel_partial_update =
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hweight_long(params->affected_displays) == 1;
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dsc_common_mode = 0;
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if (!half_panel_partial_update)
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dsc_common_mode |= DSC_MODE_SPLIT_PANEL | DSC_MODE_MULTIPLEX;
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if (enc_master->intf_mode == INTF_MODE_VIDEO)
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dsc_common_mode |= DSC_MODE_VIDEO;
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_sde_encoder_dsc_update_pic_dim(dsc, roi->w, roi->h);
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this_frame_slices = roi->w / dsc->slice_width;
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intf_ip_w = this_frame_slices * dsc->slice_width;
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_sde_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
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/*
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* dsc merge case: when using 2 encoders for the same stream,
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* no. of slices need to be same on both the encoders.
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*/
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enc_ip_w = intf_ip_w / 2;
|
||||
_sde_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
|
||||
|
||||
ich_res = _sde_encoder_dsc_ich_reset_override_needed(
|
||||
half_panel_partial_update, dsc);
|
||||
|
||||
SDE_DEBUG_DCE(sde_enc, "pic_w: %d pic_h: %d mode:%d\n",
|
||||
roi->w, roi->h, dsc_common_mode);
|
||||
SDE_EVT32(DRMID(&sde_enc->base), roi->w, roi->h,
|
||||
dsc_common_mode, i, params->affected_displays);
|
||||
|
||||
_sde_encoder_dsc_pipe_cfg(hw_dsc[0], hw_pp[0], dsc, dsc_common_mode,
|
||||
ich_res, true, hw_dsc_pp[0]);
|
||||
cfg.dsc[0] = hw_dsc[0]->idx;
|
||||
cfg.dsc_count++;
|
||||
if (hw_ctl->ops.update_bitmask_dsc)
|
||||
hw_ctl->ops.update_bitmask_dsc(hw_ctl, hw_dsc[0]->idx, 1);
|
||||
|
||||
|
||||
_sde_encoder_dsc_pipe_cfg(hw_dsc[1], hw_pp[1], dsc, dsc_common_mode,
|
||||
ich_res, !half_panel_partial_update, hw_dsc_pp[1]);
|
||||
if (!half_panel_partial_update) {
|
||||
cfg.dsc[1] = hw_dsc[1]->idx;
|
||||
cfg.dsc_count++;
|
||||
if (hw_ctl->ops.update_bitmask_dsc)
|
||||
hw_ctl->ops.update_bitmask_dsc(hw_ctl, hw_dsc[1]->idx,
|
||||
1);
|
||||
}
|
||||
/* setup dsc active configuration in the control path */
|
||||
if (hw_ctl->ops.setup_dsc_cfg) {
|
||||
hw_ctl->ops.setup_dsc_cfg(hw_ctl, &cfg);
|
||||
SDE_DEBUG_DCE(sde_enc,
|
||||
"setup_dsc_cfg hw_ctl[%d], count:%d,dsc[0]:%d, dsc[1]:%d\n",
|
||||
hw_ctl->idx,
|
||||
cfg.dsc_count,
|
||||
cfg.dsc[0],
|
||||
cfg.dsc[1]);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int _dce_dsc_setup(struct sde_encoder_virt *sde_enc,
|
||||
struct sde_encoder_kickoff_params *params)
|
||||
{
|
||||
enum sde_rm_topology_name topology;
|
||||
struct drm_connector *drm_conn;
|
||||
int ret = 0;
|
||||
|
||||
if (!sde_enc || !params || !sde_enc->phys_encs[0] ||
|
||||
!sde_enc->phys_encs[0]->connector)
|
||||
return -EINVAL;
|
||||
|
||||
drm_conn = sde_enc->phys_encs[0]->connector;
|
||||
|
||||
topology = sde_connector_get_topology_name(drm_conn);
|
||||
if (topology == SDE_RM_TOPOLOGY_NONE) {
|
||||
SDE_ERROR_DCE(sde_enc, "topology not set yet\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
SDE_DEBUG_DCE(sde_enc, "topology:%d\n", topology);
|
||||
SDE_EVT32(DRMID(&sde_enc->base), topology,
|
||||
sde_enc->cur_conn_roi.x,
|
||||
sde_enc->cur_conn_roi.y,
|
||||
sde_enc->cur_conn_roi.w,
|
||||
sde_enc->cur_conn_roi.h,
|
||||
sde_enc->prv_conn_roi.x,
|
||||
sde_enc->prv_conn_roi.y,
|
||||
sde_enc->prv_conn_roi.w,
|
||||
sde_enc->prv_conn_roi.h,
|
||||
sde_enc->cur_master->cached_mode.hdisplay,
|
||||
sde_enc->cur_master->cached_mode.vdisplay);
|
||||
|
||||
if (sde_kms_rect_is_equal(&sde_enc->cur_conn_roi,
|
||||
&sde_enc->prv_conn_roi))
|
||||
return ret;
|
||||
|
||||
switch (topology) {
|
||||
case SDE_RM_TOPOLOGY_SINGLEPIPE_DSC:
|
||||
case SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC:
|
||||
ret = _sde_encoder_dsc_n_lm_1_enc_1_intf(sde_enc);
|
||||
break;
|
||||
case SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE:
|
||||
ret = _sde_encoder_dsc_2_lm_2_enc_1_intf(sde_enc, params);
|
||||
break;
|
||||
case SDE_RM_TOPOLOGY_DUALPIPE_DSC:
|
||||
ret = _sde_encoder_dsc_2_lm_2_enc_2_intf(sde_enc, params);
|
||||
break;
|
||||
default:
|
||||
SDE_ERROR_DCE(sde_enc, "No DSC support for topology %d",
|
||||
topology);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void _dce_dsc_disable(struct sde_encoder_virt *sde_enc)
|
||||
{
|
||||
int i;
|
||||
@@ -555,7 +388,7 @@ static void _dce_dsc_disable(struct sde_encoder_virt *sde_enc)
|
||||
hw_dsc = sde_enc->hw_dsc[i];
|
||||
hw_dsc_pp = sde_enc->hw_dsc_pp[i];
|
||||
|
||||
_sde_encoder_dsc_pipe_cfg(hw_dsc, hw_pp, NULL,
|
||||
_dce_dsc_pipe_cfg(hw_dsc, hw_pp, NULL,
|
||||
0, 0, 0, hw_dsc_pp);
|
||||
|
||||
if (hw_dsc)
|
||||
|
||||
Reference in New Issue
Block a user