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Merge "disp: msm: fix kw issues in sde driver"

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qctecmdr
2020-06-10 17:06:50 -07:00
committed by Gerrit - the friendly Code Review server
parent 8975496690 5a1af16b1a
commit 621a624d8c
5 changed files with 12 additions and 16 deletions
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6
msm/sde/sde_encoder.c
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@@ -2086,7 +2086,7 @@ static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
struct sde_rm_hw_iter pp_iter, qdss_iter; struct sde_rm_hw_iter pp_iter, qdss_iter;
struct sde_rm_hw_iter dsc_iter, vdc_iter; struct sde_rm_hw_iter dsc_iter, vdc_iter;
struct sde_rm_hw_request request_hw; struct sde_rm_hw_request request_hw;
int i; int i, j;
sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG); sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
@@ -2102,7 +2102,7 @@ static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
if (phys) { if (phys) {
sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id, sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
SDE_HW_BLK_QDSS); SDE_HW_BLK_QDSS);
for (i = 0; i < QDSS_MAX; i++) { for (j = 0; j < QDSS_MAX; j++) {
if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) { if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
phys->hw_qdss = phys->hw_qdss =
(struct sde_hw_qdss *)qdss_iter.hw; (struct sde_hw_qdss *)qdss_iter.hw;
@@ -2156,7 +2156,7 @@ static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc); struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
enum sde_intf_mode intf_mode; enum sde_intf_mode intf_mode;
int ret; int ret;
bool is_cmd_mode; bool is_cmd_mode = false;
if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE)) if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
is_cmd_mode = true; is_cmd_mode = true;

4
msm/sde/sde_encoder_dce.c
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@@ -385,9 +385,7 @@ static int _dce_dsc_setup_single(struct sde_encoder_virt *sde_enc,
SDE_DEBUG("mode_3d %s, on CTL_%d PP-%d merge3d:%d\n", SDE_DEBUG("mode_3d %s, on CTL_%d PP-%d merge3d:%d\n",
!disable_merge_3d ? "enabled" : "disabled", !disable_merge_3d ? "enabled" : "disabled",
hw_ctl->idx - CTL_0, hw_pp->idx - PINGPONG_0, hw_ctl->idx - CTL_0, hw_pp->idx - PINGPONG_0,
hw_pp->merge_3d ? hw_pp->merge_3d->idx - MERGE_3D_0);
hw_pp->merge_3d->idx - MERGE_3D_0 :
-1);
} }
return 0; return 0;

6
msm/sde/sde_encoder_phys_cmd.c
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@@ -330,8 +330,8 @@ static void _sde_encoder_phys_cmd_setup_irq_hw_idx(
int ret = 0; int ret = 0;
if (!phys_enc->sde_kms || !phys_enc->hw_pp || !phys_enc->hw_ctl) { if (!phys_enc->sde_kms || !phys_enc->hw_pp || !phys_enc->hw_ctl) {
SDE_ERROR("invalid args %d %d\n", !phys_enc, SDE_ERROR("invalid args %d %d %d\n", !phys_enc->sde_kms,
phys_enc ? !phys_enc->hw_pp : 0); !phys_enc->hw_pp, !phys_enc->hw_ctl);
return; return;
} }
@@ -500,7 +500,7 @@ static int _sde_encoder_phys_cmd_handle_ppdone_timeout(
u32 pending_kickoff_cnt; u32 pending_kickoff_cnt;
unsigned long lock_flags; unsigned long lock_flags;
if (!phys_enc || !phys_enc->hw_pp || !phys_enc->hw_ctl) if (!phys_enc->hw_pp || !phys_enc->hw_ctl)
return -EINVAL; return -EINVAL;
conn = phys_enc->connector; conn = phys_enc->connector;

8
msm/sde/sde_plane.c
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@@ -846,11 +846,9 @@ static void _sde_plane_setup_scaler3(struct sde_plane *psde,
bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE)); bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90); bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
if (!psde || !pstate || !fmt || if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
!chroma_subsmpl_h || !chroma_subsmpl_v) { SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
SDE_ERROR("psde %d pstate %d fmt %d smp_h %d smp_v %d\n", chroma_subsmpl_h, chroma_subsmpl_v);
!!psde, !!pstate, !!fmt, chroma_subsmpl_h,
chroma_subsmpl_v);
return; return;
} }

4
msm/sde_dsc_helper.c
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@@ -93,7 +93,7 @@ static struct sde_dsc_v1_1_table_index_lut {
int scr_ver; int scr_ver;
u32 bpc; u32 bpc;
u32 bpp; u32 bpp;
enum sde_dsc_ratio_type type; u32 type;
} sde_dsc_v1_1_index_map[] = { } sde_dsc_v1_1_index_map[] = {
{0, 8, 8, DSC_V11_8BPC_8BPP}, {0, 8, 8, DSC_V11_8BPC_8BPP},
{0, 10, 8, DSC_V11_10BPC_8BPP}, {0, 10, 8, DSC_V11_10BPC_8BPP},
@@ -108,7 +108,7 @@ static struct sde_dsc_v1_2_table_index_lut {
u32 fmt; u32 fmt;
u32 bpc; u32 bpc;
u32 bpp; u32 bpp;
enum sde_dsc_ratio_type type; u32 type;
} sde_dsc_v1_2_index_map[] = { } sde_dsc_v1_2_index_map[] = {
{MSM_CHROMA_444, 8, 8, DSC_V12_444_8BPC_8BPP}, {MSM_CHROMA_444, 8, 8, DSC_V12_444_8BPC_8BPP},
{MSM_CHROMA_444, 10, 8, DSC_V12_444_10BPC_8BPP}, {MSM_CHROMA_444, 10, 8, DSC_V12_444_10BPC_8BPP},