msm: camera: isp: Fix for disable UBWC case
Sometimes multiple io cofigs comes before start_dev. Therefore even we force disable UBWC compression at start_dev time it can be override by those io configs. Therefore moving disable UBWC comp logic to acquire time. Acquire time a flag is sent if we have to enable or disable ubwc compression, based on this we set bus side ubwc_disable flag. When ever we start the WM or update the WM UBWC config we check this flag and based on this flag we override the ubwc_mode_cfg register. CRs-Fixed: 2833514 Change-Id: I8efc3f7abd53e0757f8e77ac0788e303f7c695b9 Signed-off-by: Wyes Karny <wkarny@codeaurora.org>
Bu işleme şunda yer alıyor:
@@ -637,6 +637,9 @@ int cam_a5_process_cmd(void *device_priv, uint32_t cmd_type,
|
||||
if (*disable_ubwc_comp) {
|
||||
ubwc_ipe_cfg[1] &= ~CAM_ICP_UBWC_COMP_EN;
|
||||
ubwc_bps_cfg[1] &= ~CAM_ICP_UBWC_COMP_EN;
|
||||
CAM_DBG(CAM_ICP,
|
||||
"Force disable UBWC compression, ubwc_ipe_cfg: 0x%x, ubwc_bps_cfg: 0x%x",
|
||||
ubwc_ipe_cfg[1], ubwc_bps_cfg[1]);
|
||||
}
|
||||
rc = hfi_cmd_ubwc_config_ext(&ubwc_ipe_cfg[0],
|
||||
&ubwc_bps_cfg[0]);
|
||||
|
@@ -1537,6 +1537,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_rdi(
|
||||
vfe_acquire.vfe_out.split_id = CAM_ISP_HW_SPLIT_LEFT;
|
||||
vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index;
|
||||
vfe_acquire.vfe_out.is_dual = 0;
|
||||
vfe_acquire.vfe_out.disable_ubwc_comp =
|
||||
g_ife_hw_mgr.debug_cfg.disable_ubwc_comp;
|
||||
vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler;
|
||||
vfe_acquire.buf_done_controller = ife_ctx->buf_done_controller;
|
||||
hw_intf = ife_src_res->hw_res[0]->hw_intf;
|
||||
@@ -1619,6 +1621,8 @@ static int cam_ife_hw_mgr_acquire_res_ife_out_pixel(
|
||||
vfe_acquire.vfe_out.out_port_info = out_port;
|
||||
vfe_acquire.vfe_out.is_dual = ife_src_res->is_dual_isp;
|
||||
vfe_acquire.vfe_out.unique_id = ife_ctx->ctx_index;
|
||||
vfe_acquire.vfe_out.disable_ubwc_comp =
|
||||
g_ife_hw_mgr.debug_cfg.disable_ubwc_comp;
|
||||
vfe_acquire.event_cb = cam_ife_hw_mgr_event_handler;
|
||||
vfe_acquire.buf_done_controller = ife_ctx->buf_done_controller;
|
||||
|
||||
@@ -5372,7 +5376,6 @@ static int cam_isp_blob_bw_update(
|
||||
if (hw_intf && hw_intf->hw_ops.process_cmd) {
|
||||
bw_upd_args.node_res =
|
||||
hw_mgr_res->hw_res[i];
|
||||
|
||||
bw_upd_args.camnoc_bw_bytes = cam_bw_bps;
|
||||
bw_upd_args.external_bw_bytes = ext_bw_bps;
|
||||
|
||||
@@ -6019,8 +6022,8 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args)
|
||||
struct cam_ife_hw_mgr_ctx *ctx;
|
||||
struct cam_isp_hw_mgr_res *hw_mgr_res;
|
||||
struct cam_isp_resource_node *rsrc_node = NULL;
|
||||
uint32_t i, j;
|
||||
uint32_t camif_debug, disable_ubwc_comp;
|
||||
uint32_t i;
|
||||
uint32_t camif_debug;
|
||||
bool res_rdi_context_set = false;
|
||||
uint32_t primary_rdi_src_res;
|
||||
uint32_t primary_rdi_out_res;
|
||||
@@ -6139,27 +6142,6 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args)
|
||||
}
|
||||
}
|
||||
|
||||
if (g_ife_hw_mgr.debug_cfg.disable_ubwc_comp) {
|
||||
disable_ubwc_comp = 1;
|
||||
for (i = 0; i < max_ife_out_res; i++) {
|
||||
hw_mgr_res = &ctx->res_list_ife_out[i];
|
||||
for (j = 0; j < CAM_ISP_HW_SPLIT_MAX; j++) {
|
||||
if (!hw_mgr_res->hw_res[i])
|
||||
continue;
|
||||
|
||||
rsrc_node = hw_mgr_res->hw_res[i];
|
||||
if (rsrc_node->hw_intf->hw_ops.process_cmd) {
|
||||
rc = rsrc_node->hw_intf->hw_ops.process_cmd(
|
||||
rsrc_node->hw_intf->hw_priv,
|
||||
CAM_ISP_HW_CMD_DISABLE_UBWC_COMP,
|
||||
&disable_ubwc_comp,
|
||||
sizeof(disable_ubwc_comp));
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
rc = cam_ife_hw_mgr_init_hw(ctx);
|
||||
if (rc) {
|
||||
CAM_ERR(CAM_ISP, "Init failed");
|
||||
|
@@ -39,8 +39,6 @@ enum cam_ife_ctx_master_type {
|
||||
#define CAM_IFE_CTX_CFG_SFE_FS_MODE BIT(2)
|
||||
#define CAM_IFE_CTX_CFG_DYNAMIC_SWITCH_ON BIT(3)
|
||||
|
||||
#define CAM_IFE_UBWC_COMP_EN BIT(1)
|
||||
|
||||
/**
|
||||
* struct cam_ife_hw_mgr_debug - contain the debug information
|
||||
*
|
||||
|
@@ -134,7 +134,6 @@ enum cam_isp_hw_cmd_type {
|
||||
CAM_ISP_HW_CMD_CSID_CLOCK_DUMP,
|
||||
CAM_ISP_HW_CMD_TPG_CORE_CFG_CMD,
|
||||
CAM_ISP_HW_CMD_CSID_CHANGE_HALT_MODE,
|
||||
CAM_ISP_HW_CMD_DISABLE_UBWC_COMP,
|
||||
CAM_ISP_HW_CMD_SET_SFE_DEBUG_CFG,
|
||||
CAM_ISP_HW_CMD_QUERY_BUS_CAP,
|
||||
CAM_IFE_CSID_CMD_GET_TIME_STAMP,
|
||||
|
@@ -141,6 +141,7 @@ struct cam_vfe_hw_vfe_bus_rd_acquire_args {
|
||||
* (Default is Master in case of Single VFE)
|
||||
* @dual_slave_core: If Master and Slave exists, HW Index of Slave
|
||||
* @cdm_ops: CDM operations
|
||||
* @disable_ubwc_comp: Disable UBWC compression
|
||||
*/
|
||||
struct cam_vfe_hw_vfe_out_acquire_args {
|
||||
struct cam_isp_resource_node *rsrc_node;
|
||||
@@ -151,6 +152,7 @@ struct cam_vfe_hw_vfe_out_acquire_args {
|
||||
uint32_t is_master;
|
||||
uint32_t dual_slave_core;
|
||||
struct cam_cdm_utils_ops *cdm_ops;
|
||||
bool disable_ubwc_comp;
|
||||
};
|
||||
|
||||
/*
|
||||
|
@@ -526,7 +526,6 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
|
||||
case CAM_ISP_HW_CMD_UNMASK_BUS_WR_IRQ:
|
||||
case CAM_ISP_HW_CMD_DUMP_BUS_INFO:
|
||||
case CAM_ISP_HW_CMD_GET_RES_FOR_MID:
|
||||
case CAM_ISP_HW_CMD_DISABLE_UBWC_COMP:
|
||||
case CAM_ISP_HW_CMD_QUERY_BUS_CAP:
|
||||
rc = core_info->vfe_bus->hw_ops.process_cmd(
|
||||
core_info->vfe_bus->bus_priv, cmd_type, cmd_args,
|
||||
|
@@ -238,6 +238,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_client ubwc_regs_client_3 = {
|
||||
.meta_stride = 0x00002540,
|
||||
.mode_cfg_0 = 0x00002544,
|
||||
.bw_limit = 0x000025A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_client ubwc_regs_client_4 = {
|
||||
@@ -249,6 +250,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_client ubwc_regs_client_4 = {
|
||||
.meta_stride = 0x00002640,
|
||||
.mode_cfg_0 = 0x00002644,
|
||||
.bw_limit = 0x000026A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_hw_info vfe170_bus_hw_info = {
|
||||
|
@@ -205,6 +205,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_client
|
||||
.meta_stride = 0x00002540,
|
||||
.mode_cfg_0 = 0x00002544,
|
||||
.bw_limit = 0x000025A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_client
|
||||
@@ -217,6 +218,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_client
|
||||
.meta_stride = 0x00002640,
|
||||
.mode_cfg_0 = 0x00002644,
|
||||
.bw_limit = 0x000026A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_hw_info vfe170_150_bus_hw_info = {
|
||||
|
@@ -267,6 +267,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00002544,
|
||||
.mode_cfg_1 = 0x000025A4,
|
||||
.bw_limit = 0x000025A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
@@ -280,6 +281,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00002644,
|
||||
.mode_cfg_1 = 0x000026A4,
|
||||
.bw_limit = 0x000026A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
@@ -293,6 +295,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00003644,
|
||||
.mode_cfg_1 = 0x000036A4,
|
||||
.bw_limit = 0x000036A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
@@ -306,6 +309,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00003744,
|
||||
.mode_cfg_1 = 0x000037A4,
|
||||
.bw_limit = 0x000037A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_hw_info vfe175_bus_hw_info = {
|
||||
|
@@ -338,6 +338,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00002544,
|
||||
.mode_cfg_1 = 0x000025A4,
|
||||
.bw_limit = 0x000025A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
@@ -351,6 +352,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00002644,
|
||||
.mode_cfg_1 = 0x000026A4,
|
||||
.bw_limit = 0x000026A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
@@ -364,6 +366,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00003644,
|
||||
.mode_cfg_1 = 0x000036A4,
|
||||
.bw_limit = 0x000036A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
@@ -377,6 +380,7 @@ static struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client
|
||||
.mode_cfg_0 = 0x00003744,
|
||||
.mode_cfg_1 = 0x000037A4,
|
||||
.bw_limit = 0x000037A0,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_rd_ver1_hw_info vfe175_130_bus_rd_hw_info = {
|
||||
|
@@ -340,6 +340,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x0000AC58,
|
||||
.off_lossy_var = 0x0000AC5C,
|
||||
.bw_limit = 0x0000AC1C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
@@ -353,6 +354,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x0000AD58,
|
||||
.off_lossy_var = 0x0000AD5C,
|
||||
.bw_limit = 0x0000AD1C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
@@ -366,6 +368,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x0000B058,
|
||||
.off_lossy_var = 0x0000B05C,
|
||||
.bw_limit = 0x0000B01C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
@@ -379,6 +382,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x0000B158,
|
||||
.off_lossy_var = 0x0000B15C,
|
||||
.bw_limit = 0x0000B11C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_hw_info vfe480_bus_hw_info = {
|
||||
|
@@ -461,6 +461,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x00000E58,
|
||||
.off_lossy_var = 0x00000E5C,
|
||||
.bw_limit = 0x00000E1C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
@@ -474,6 +475,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x00000F58,
|
||||
.off_lossy_var = 0x00000F5C,
|
||||
.bw_limit = 0x00000F1C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
@@ -487,6 +489,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x00001258,
|
||||
.off_lossy_var = 0x0000125C,
|
||||
.bw_limit = 0x0000121C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
@@ -500,6 +503,7 @@ static struct cam_vfe_bus_ver3_reg_offset_ubwc_client
|
||||
.lossy_thresh1 = 0x00001358,
|
||||
.off_lossy_var = 0x0000135C,
|
||||
.bw_limit = 0x0000131C,
|
||||
.ubwc_comp_en_bit = BIT(1),
|
||||
};
|
||||
|
||||
static struct cam_vfe_bus_ver3_hw_info vfe680_bus_hw_info = {
|
||||
|
@@ -1259,11 +1259,19 @@ static int cam_vfe_bus_start_wm(
|
||||
(struct
|
||||
cam_vfe_bus_ver2_reg_offset_ubwc_client *)
|
||||
rsrc_data->hw_regs->ubwc_regs;
|
||||
if (!ubwc_regs) {
|
||||
CAM_ERR(CAM_ISP, "ubwc_regs is NULL");
|
||||
return -EINVAL;
|
||||
}
|
||||
val = cam_io_r_mb(common_data->mem_base +
|
||||
ubwc_regs->mode_cfg_0);
|
||||
val |= 0x1;
|
||||
if (disable_ubwc_comp)
|
||||
val &= ~CAM_IFE_UBWC_COMP_EN;
|
||||
if (disable_ubwc_comp) {
|
||||
val &= ~ubwc_regs->ubwc_comp_en_bit;
|
||||
CAM_DBG(CAM_ISP,
|
||||
"Force disable UBWC compression, ubwc_mode_cfg: 0x%x",
|
||||
val);
|
||||
}
|
||||
cam_io_w_mb(val, common_data->mem_base +
|
||||
ubwc_regs->mode_cfg_0);
|
||||
} else if ((camera_hw_version == CAM_CPAS_TITAN_175_V100) ||
|
||||
@@ -1278,11 +1286,19 @@ static int cam_vfe_bus_start_wm(
|
||||
(struct
|
||||
cam_vfe_bus_ver2_reg_offset_ubwc_3_client *)
|
||||
rsrc_data->hw_regs->ubwc_regs;
|
||||
if (!ubwc_regs) {
|
||||
CAM_ERR(CAM_ISP, "ubwc_regs is NULL");
|
||||
return -EINVAL;
|
||||
}
|
||||
val = cam_io_r_mb(common_data->mem_base +
|
||||
ubwc_regs->mode_cfg_0);
|
||||
val |= 0x1;
|
||||
if (disable_ubwc_comp)
|
||||
val &= ~CAM_IFE_UBWC_COMP_EN;
|
||||
if (disable_ubwc_comp) {
|
||||
val &= ~ubwc_regs->ubwc_comp_en_bit;
|
||||
CAM_DBG(CAM_ISP,
|
||||
"Force disable UBWC compression, ubwc_mode_cfg: 0x%x",
|
||||
val);
|
||||
}
|
||||
cam_io_w_mb(val, common_data->mem_base +
|
||||
ubwc_regs->mode_cfg_0);
|
||||
} else {
|
||||
@@ -2069,6 +2085,8 @@ static int cam_vfe_bus_acquire_vfe_out(void *bus_priv, void *acquire_args,
|
||||
|
||||
rsrc_data = rsrc_node->res_priv;
|
||||
rsrc_data->common_data->event_cb = acq_args->event_cb;
|
||||
rsrc_data->common_data->disable_ubwc_comp =
|
||||
out_acquire_args->disable_ubwc_comp;
|
||||
rsrc_data->priv = acq_args->priv;
|
||||
|
||||
secure_caps = cam_vfe_bus_can_be_secure(rsrc_data->out_type);
|
||||
@@ -2687,6 +2705,13 @@ static int cam_vfe_bus_update_ubwc_3_regs(
|
||||
CAM_DBG(CAM_ISP, "WM %d meta stride 0x%x",
|
||||
wm_data->index, reg_val_pair[*j-1]);
|
||||
|
||||
if (wm_data->common_data->disable_ubwc_comp) {
|
||||
wm_data->ubwc_mode_cfg_0 &= ~ubwc_regs->ubwc_comp_en_bit;
|
||||
CAM_DBG(CAM_ISP,
|
||||
"Force disable UBWC compression on VFE:%d WM:%d",
|
||||
wm_data->common_data->core_index, wm_data->index);
|
||||
}
|
||||
|
||||
CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j,
|
||||
ubwc_regs->mode_cfg_0, wm_data->ubwc_mode_cfg_0);
|
||||
CAM_DBG(CAM_ISP, "WM %d ubwc_mode_cfg_0 0x%x",
|
||||
@@ -2766,6 +2791,12 @@ static int cam_vfe_bus_update_ubwc_legacy_regs(
|
||||
CAM_DBG(CAM_ISP, "WM %d meta stride 0x%x",
|
||||
wm_data->index, reg_val_pair[*j-1]);
|
||||
|
||||
if (wm_data->common_data->disable_ubwc_comp) {
|
||||
wm_data->ubwc_mode_cfg_0 &= ~ubwc_regs->ubwc_comp_en_bit;
|
||||
CAM_DBG(CAM_ISP,
|
||||
"Force disable UBWC compression on VFE:%d WM:%d",
|
||||
wm_data->common_data->core_index, wm_data->index);
|
||||
}
|
||||
CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j,
|
||||
ubwc_regs->mode_cfg_0, wm_data->ubwc_mode_cfg_0);
|
||||
CAM_DBG(CAM_ISP, "WM %d ubwc_mode_cfg_0 0x%x",
|
||||
@@ -3693,10 +3724,6 @@ static int cam_vfe_bus_process_cmd(
|
||||
bus_priv = (struct cam_vfe_bus_ver2_priv *) priv;
|
||||
rc = cam_vfe_bus_get_res_for_mid(bus_priv, cmd_args, arg_size);
|
||||
break;
|
||||
case CAM_ISP_HW_CMD_DISABLE_UBWC_COMP:
|
||||
bus_priv = (struct cam_vfe_bus_ver2_priv *) priv;
|
||||
bus_priv->common_data.disable_ubwc_comp = true;
|
||||
break;
|
||||
case CAM_ISP_HW_CMD_QUERY_BUS_CAP:
|
||||
bus_priv = (struct cam_vfe_bus_ver2_priv *) priv;
|
||||
vfe_bus_cap = (struct cam_isp_hw_bus_cap *) cmd_args;
|
||||
|
@@ -101,6 +101,7 @@ struct cam_vfe_bus_ver2_reg_offset_ubwc_client {
|
||||
uint32_t meta_stride;
|
||||
uint32_t mode_cfg_0;
|
||||
uint32_t bw_limit;
|
||||
uint32_t ubwc_comp_en_bit;
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -118,6 +119,7 @@ struct cam_vfe_bus_ver2_reg_offset_ubwc_3_client {
|
||||
uint32_t mode_cfg_0;
|
||||
uint32_t mode_cfg_1;
|
||||
uint32_t bw_limit;
|
||||
uint32_t ubwc_comp_en_bit;
|
||||
};
|
||||
|
||||
|
||||
|
@@ -1451,10 +1451,22 @@ static int cam_vfe_bus_ver3_start_wm(struct cam_isp_resource_node *wm_res)
|
||||
|
||||
/* enable ubwc if needed*/
|
||||
if (rsrc_data->en_ubwc) {
|
||||
if (!ubwc_regs) {
|
||||
CAM_ERR(CAM_ISP,
|
||||
"ubwc_regs is NULL, VFE:%d WM:%d en_ubwc:%d",
|
||||
rsrc_data->common_data->core_index,
|
||||
rsrc_data->index, rsrc_data->en_ubwc);
|
||||
return -EINVAL;
|
||||
}
|
||||
val = cam_io_r_mb(common_data->mem_base + ubwc_regs->mode_cfg);
|
||||
val |= 0x1;
|
||||
if (disable_ubwc_comp)
|
||||
val &= ~(0x1<<1);
|
||||
if (disable_ubwc_comp) {
|
||||
val &= ~ubwc_regs->ubwc_comp_en_bit;
|
||||
CAM_DBG(CAM_ISP,
|
||||
"Force disable UBWC compression, VFE:%d WM:%d ubwc_mode_cfg: 0x%x",
|
||||
rsrc_data->common_data->core_index,
|
||||
rsrc_data->index, val);
|
||||
}
|
||||
cam_io_w_mb(val, common_data->mem_base + ubwc_regs->mode_cfg);
|
||||
}
|
||||
|
||||
@@ -1999,6 +2011,8 @@ static int cam_vfe_bus_ver3_acquire_vfe_out(void *bus_priv, void *acquire_args,
|
||||
|
||||
rsrc_data = rsrc_node->res_priv;
|
||||
rsrc_data->common_data->event_cb = acq_args->event_cb;
|
||||
rsrc_data->common_data->disable_ubwc_comp =
|
||||
out_acquire_args->disable_ubwc_comp;
|
||||
rsrc_data->priv = acq_args->priv;
|
||||
rsrc_data->bus_priv = ver3_bus_priv;
|
||||
comp_acq_args.composite_mask = (1 << vfe_out_res_id);
|
||||
@@ -2980,8 +2994,12 @@ static int cam_vfe_bus_ver3_update_ubwc_regs(
|
||||
CAM_DBG(CAM_ISP, "WM:%d meta stride 0x%X",
|
||||
wm_data->index, reg_val_pair[*j-1]);
|
||||
|
||||
if (wm_data->common_data->disable_ubwc_comp)
|
||||
wm_data->ubwc_mode_cfg &= ~(0x1<<1);
|
||||
if (wm_data->common_data->disable_ubwc_comp) {
|
||||
wm_data->ubwc_mode_cfg &= ~ubwc_regs->ubwc_comp_en_bit;
|
||||
CAM_DBG(CAM_ISP,
|
||||
"Force disable UBWC compression on VFE:%d WM:%d",
|
||||
wm_data->common_data->core_index, wm_data->index);
|
||||
}
|
||||
|
||||
CAM_VFE_ADD_REG_VAL_PAIR(reg_val_pair, *j,
|
||||
ubwc_regs->mode_cfg, wm_data->ubwc_mode_cfg);
|
||||
@@ -3754,10 +3772,6 @@ static int cam_vfe_bus_ver3_process_cmd(
|
||||
bus_priv = (struct cam_vfe_bus_ver3_priv *) priv;
|
||||
rc = cam_vfe_bus_get_res_for_mid(bus_priv, cmd_args, arg_size);
|
||||
break;
|
||||
case CAM_ISP_HW_CMD_DISABLE_UBWC_COMP:
|
||||
bus_priv = (struct cam_vfe_bus_ver3_priv *) priv;
|
||||
bus_priv->common_data.disable_ubwc_comp = true;
|
||||
break;
|
||||
case CAM_ISP_HW_CMD_QUERY_BUS_CAP:
|
||||
bus_priv = (struct cam_vfe_bus_ver3_priv *) priv;
|
||||
vfe_bus_cap = (struct cam_isp_hw_bus_cap *) cmd_args;
|
||||
|
@@ -126,6 +126,7 @@ struct cam_vfe_bus_ver3_reg_offset_ubwc_client {
|
||||
uint32_t lossy_thresh1;
|
||||
uint32_t off_lossy_var;
|
||||
uint32_t bw_limit;
|
||||
uint32_t ubwc_comp_en_bit;
|
||||
};
|
||||
|
||||
/*
|
||||
|
Yeni konuda referans
Bir kullanıcı engelle