disp: msm: sde: add support for 3d_mux DSC topology

This change adds support for dsc using the 3d mux hw block.
The 3d_mux hw block merges the input from layer mixer before passing to
dsc block for compression.

Change-Id: I21544c33fff2c1e604c0ae712a036a127d25afcf
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>

msm/sde/sde_hw_ctl.c

@@ -1087,6 +1087,7 @@ static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
 	u32 cwb_active = 0;
 	u32 merge_3d_active = 0;
 	u32 wb_active = 0;
+	u32 dsc_active = 0;
 	struct sde_hw_blk_reg_map *c;
 
 	if (!ctx)
@@ -1095,7 +1096,6 @@ static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
 	c = &ctx->hw;
 
 	if (cfg->cwb_count) {
-		wb_active = 0;
 		cwb_active = SDE_REG_READ(c, CTL_CWB_ACTIVE);
 		for (i = 0; i < cfg->cwb_count; i++) {
 			if (cfg->cwb[i])
@@ -1117,28 +1117,21 @@ static int sde_hw_ctl_update_intf_cfg(struct sde_hw_ctl *ctx,
 					(cfg->merge_3d[i] - MERGE_3D_0),
 					enable);
 		}
+
 		SDE_REG_WRITE(c, CTL_MERGE_3D_ACTIVE, merge_3d_active);
 	}
 
-	return 0;
-}
+	if (cfg->dsc_count) {
+		dsc_active = SDE_REG_READ(c, CTL_DSC_ACTIVE);
+		for (i = 0; i < cfg->dsc_count; i++) {
+			if (cfg->dsc[i])
+				UPDATE_ACTIVE(dsc_active,
+					(cfg->dsc[i] - DSC_0), enable);
+		}
 
-static int sde_hw_ctl_dsc_cfg(struct sde_hw_ctl *ctx,
-		struct sde_ctl_dsc_cfg *cfg)
-{
-	struct sde_hw_blk_reg_map *c;
-	u32 dsc_active = 0;
-	int i;
+		SDE_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
+	}
 
-	if (!ctx)
-		return -EINVAL;
-
-	c = &ctx->hw;
-	for (i = 0; i < cfg->dsc_count; i++)
-		if (cfg->dsc[i])
-			dsc_active |= BIT(cfg->dsc[i] - DSC_0);
-
-	SDE_REG_WRITE(c, CTL_DSC_ACTIVE, dsc_active);
 	return 0;
 }
 
@@ -1288,7 +1281,6 @@ static void _setup_ctl_ops(struct sde_hw_ctl_ops *ops,
 
 		ops->setup_intf_cfg_v1 = sde_hw_ctl_intf_cfg_v1;
 		ops->update_intf_cfg = sde_hw_ctl_update_intf_cfg;
-		ops->setup_dsc_cfg = sde_hw_ctl_dsc_cfg;
 
 		ops->update_bitmask_cdm = sde_hw_ctl_update_bitmask_cdm_v1;
 		ops->update_bitmask_wb = sde_hw_ctl_update_bitmask_wb_v1;