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@@ -36,7 +36,6 @@
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#define DP_PHY_AUX_CFG1 0x0024
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#define DP_PHY_AUX_CFG2 0x0028
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-#define DP_PHY_VCO_DIV 0x0070
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#define DP_PHY_TX0_TX1_LANE_CTL 0x0078
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#define DP_PHY_TX2_TX3_LANE_CTL 0x009C
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@@ -213,66 +212,66 @@ static int dp_vco_pll_init_db_4nm(struct dp_pll_db *pdb,
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case DP_VCO_HSCLK_RATE_1620MHZDIV1000:
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DP_DEBUG("VCO rate: %ld\n", DP_VCO_RATE_9720MHZDIV1000);
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pdb->hsclk_sel = 0x05;
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- pdb->dec_start_mode0 = 0x69;
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- pdb->div_frac_start2_mode0 = 0x80;
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- pdb->div_frac_start3_mode0 = 0x07;
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- pdb->lock_cmp1_mode0 = 0x6f;
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- pdb->lock_cmp2_mode0 = 0x08;
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+ pdb->dec_start_mode0 = 0x34;
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+ pdb->div_frac_start2_mode0 = 0xc0;
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+ pdb->div_frac_start3_mode0 = 0x0b;
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+ pdb->lock_cmp1_mode0 = 0x37;
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+ pdb->lock_cmp2_mode0 = 0x04;
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pdb->phy_vco_div = 0x1;
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pdb->lock_cmp_en = 0x04;
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- pdb->ssc_step_size1_mode0 = 0x45;
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- pdb->ssc_step_size2_mode0 = 0x06;
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- pdb->ssc_per1 = 0x36;
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- pdb->cmp_code1_mode0 = 0xE2;
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- pdb->cmp_code2_mode0 = 0x18;
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+ pdb->ssc_step_size1_mode0 = 0x92;
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+ pdb->ssc_step_size2_mode0 = 0x01;
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+ pdb->ssc_per1 = 0x6B;
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+ pdb->cmp_code1_mode0 = 0x71;
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+ pdb->cmp_code2_mode0 = 0x0c;
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break;
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case DP_VCO_HSCLK_RATE_2700MHZDIV1000:
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DP_DEBUG("VCO rate: %ld\n", DP_VCO_RATE_10800MHZDIV1000);
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pdb->hsclk_sel = 0x03;
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- pdb->dec_start_mode0 = 0x69;
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- pdb->div_frac_start2_mode0 = 0x80;
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- pdb->div_frac_start3_mode0 = 0x07;
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- pdb->lock_cmp1_mode0 = 0x0f;
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- pdb->lock_cmp2_mode0 = 0x0e;
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+ pdb->dec_start_mode0 = 0x34;
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+ pdb->div_frac_start2_mode0 = 0xc0;
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+ pdb->div_frac_start3_mode0 = 0x0b;
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+ pdb->lock_cmp1_mode0 = 0x07;
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+ pdb->lock_cmp2_mode0 = 0x07;
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pdb->phy_vco_div = 0x1;
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pdb->lock_cmp_en = 0x08;
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- pdb->ssc_step_size1_mode0 = 0x45;
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- pdb->ssc_step_size2_mode0 = 0x06;
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- pdb->ssc_per1 = 0x36;
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- pdb->cmp_code1_mode0 = 0xE2;
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- pdb->cmp_code2_mode0 = 0x18;
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+ pdb->ssc_step_size1_mode0 = 0x92;
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+ pdb->ssc_step_size2_mode0 = 0x01;
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+ pdb->ssc_per1 = 0x6B;
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+ pdb->cmp_code1_mode0 = 0x71;
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+ pdb->cmp_code2_mode0 = 0x0c;
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break;
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case DP_VCO_HSCLK_RATE_5400MHZDIV1000:
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DP_DEBUG("VCO rate: %ld\n", DP_VCO_RATE_10800MHZDIV1000);
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pdb->hsclk_sel = 0x01;
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- pdb->dec_start_mode0 = 0x8c;
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+ pdb->dec_start_mode0 = 0x46;
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pdb->div_frac_start2_mode0 = 0x00;
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- pdb->div_frac_start3_mode0 = 0x0a;
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- pdb->lock_cmp1_mode0 = 0x1f;
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- pdb->lock_cmp2_mode0 = 0x1c;
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+ pdb->div_frac_start3_mode0 = 0x05;
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+ pdb->lock_cmp1_mode0 = 0x0f;
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+ pdb->lock_cmp2_mode0 = 0x0e;
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pdb->phy_vco_div = 0x2;
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pdb->lock_cmp_en = 0x08;
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- pdb->ssc_step_size1_mode0 = 0x5C;
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- pdb->ssc_step_size2_mode0 = 0x08;
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- pdb->ssc_per1 = 0x36;
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- pdb->cmp_code1_mode0 = 0x2E;
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- pdb->cmp_code2_mode0 = 0x21;
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+ pdb->ssc_step_size1_mode0 = 0x18;
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+ pdb->ssc_step_size2_mode0 = 0x02;
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+ pdb->ssc_per1 = 0x6B;
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+ pdb->cmp_code1_mode0 = 0x97;
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+ pdb->cmp_code2_mode0 = 0x10;
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break;
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case DP_VCO_HSCLK_RATE_8100MHZDIV1000:
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DP_DEBUG("VCO rate: %ld\n", DP_VCO_RATE_8100MHZDIV1000);
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pdb->hsclk_sel = 0x00;
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- pdb->dec_start_mode0 = 0x69;
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- pdb->div_frac_start2_mode0 = 0x80;
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- pdb->div_frac_start3_mode0 = 0x07;
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- pdb->lock_cmp1_mode0 = 0x2f;
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- pdb->lock_cmp2_mode0 = 0x2a;
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+ pdb->dec_start_mode0 = 0x34;
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+ pdb->div_frac_start2_mode0 = 0xc0;
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+ pdb->div_frac_start3_mode0 = 0x0b;
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+ pdb->lock_cmp1_mode0 = 0x17;
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+ pdb->lock_cmp2_mode0 = 0x15;
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pdb->phy_vco_div = 0x0;
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pdb->lock_cmp_en = 0x08;
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- pdb->ssc_step_size1_mode0 = 0x45;
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- pdb->ssc_step_size2_mode0 = 0x06;
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- pdb->ssc_per1 = 0x36;
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- pdb->cmp_code1_mode0 = 0xE2;
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- pdb->cmp_code2_mode0 = 0x18;
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+ pdb->ssc_step_size1_mode0 = 0x92;
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+ pdb->ssc_step_size2_mode0 = 0x01;
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+ pdb->ssc_per1 = 0x6B;
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+ pdb->cmp_code1_mode0 = 0x71;
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+ pdb->cmp_code2_mode0 = 0x0c;
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break;
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default:
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DP_ERR("unsupported rate %ld\n", rate);
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@@ -317,7 +316,7 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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wmb();
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/* PLL Optimization */
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- dp_pll_write(dp_pll, QSERDES_COM_PLL_IVCO, 0x0f);
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+ dp_pll_write(dp_pll, QSERDES_COM_PLL_IVCO, 0x07);
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dp_pll_write(dp_pll, QSERDES_COM_PLL_CCTRL_MODE0, 0x36);
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dp_pll_write(dp_pll, QSERDES_COM_PLL_RCTRL_MODE0, 0x16);
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dp_pll_write(dp_pll, QSERDES_COM_CP_CTRL_MODE0, 0x06);
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@@ -347,14 +346,11 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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/* Make sure the PHY register writes are done */
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wmb();
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- dp_pll_write(dp_pll, QSERDES_COM_BG_TIMER, 0x0e);
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+ dp_pll_write(dp_pll, QSERDES_COM_BG_TIMER, 0x0a);
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dp_pll_write(dp_pll, QSERDES_COM_CORECLK_DIV_MODE0, 0x14);
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dp_pll_write(dp_pll, QSERDES_COM_VCO_TUNE_CTRL, 0x00);
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- if (pll->bonding_en)
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- dp_pll_write(dp_pll, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1f);
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- else
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- dp_pll_write(dp_pll, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17);
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+ dp_pll_write(dp_pll, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1f);
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dp_pll_write(dp_pll, QSERDES_COM_CORE_CLK_EN, 0x0f);
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dp_pll_write(dp_pll, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, pdb->cmp_code1_mode0);
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@@ -366,7 +362,7 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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dp_pll_write(dp_pll, QSERDES_COM_SSC_EN_CENTER, 0x01);
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dp_pll_write(dp_pll, QSERDES_COM_SSC_ADJ_PER1, 0x00);
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dp_pll_write(dp_pll, QSERDES_COM_SSC_PER1, pdb->ssc_per1);
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- dp_pll_write(dp_pll, QSERDES_COM_SSC_PER2, 0x01);
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+ dp_pll_write(dp_pll, QSERDES_COM_SSC_PER2, 0x02);
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dp_pll_write(dp_pll, QSERDES_COM_SSC_STEP_SIZE1_MODE0,
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pdb->ssc_step_size1_mode0);
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dp_pll_write(dp_pll, QSERDES_COM_SSC_STEP_SIZE2_MODE0,
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@@ -393,8 +389,8 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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dp_pll_write(dp_ln_tx0, DP_TRAN_DRVR_EMP_EN, 0xf);
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dp_pll_write(dp_ln_tx0, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
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dp_pll_write(dp_ln_tx0, DP_TX_INTERFACE_MODE, 0x00);
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- dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_TX, 0x0C);
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- dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_RX, 0x0C);
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+ dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_TX, 0x0A);
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+ dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
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dp_pll_write(dp_ln_tx0, TXn_TX_BAND, 0x04);
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/* Make sure the PLL register writes are done */
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wmb();
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@@ -409,8 +405,8 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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dp_pll_write(dp_ln_tx1, DP_TRAN_DRVR_EMP_EN, 0xf);
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dp_pll_write(dp_ln_tx1, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
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dp_pll_write(dp_ln_tx1, DP_TX_INTERFACE_MODE, 0x00);
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- dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_TX, 0x0C);
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- dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_RX, 0x0C);
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+ dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_TX, 0x11);
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+ dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
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dp_pll_write(dp_ln_tx1, TXn_TX_BAND, 0x04);
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/* Make sure the PHY register writes are done */
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wmb();
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