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qcacmn: DP changes for umac reset in QCA5332

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Make DP changes for handling umac reset in QCA5332.
Changes are done to program msi_data value of the IPC interrupt to FW.

Change-Id: Ib6453755e191da655b87b528a7cef38a464f316b
CRs-Fixed: 3401146
This commit is contained in:
Nandha Kishore Easwaran
2023-02-09 11:12:02 +05:30
committed by Madan Koyyalamudi
parent 3062af6ed0
commit 610ccaa126
4 changed files with 36 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
dp/wifi3.0/dp_main.c
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@@ -3224,8 +3224,6 @@ static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
soc->wlan_cfg_ctx, intr_ctx_num); soc->wlan_cfg_ctx, intr_ctx_num);
int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask( int txmon2host_mon_ring_mask = wlan_cfg_get_tx_mon_ring_mask(
soc->wlan_cfg_ctx, intr_ctx_num); soc->wlan_cfg_ctx, intr_ctx_num);
int umac_reset_mask = wlan_cfg_get_umac_reset_intr_mask(
soc->wlan_cfg_ctx, intr_ctx_num);
soc->intr_mode = DP_INTR_INTEGRATED; soc->intr_mode = DP_INTR_INTEGRATED;
@@ -3282,9 +3280,6 @@ static void dp_soc_interrupt_map_calculate_integrated(struct dp_soc *soc,
(txmon2host_monitor_destination_mac1 - j); (txmon2host_monitor_destination_mac1 - j);
} }
if (umac_reset_mask & (1 << j))
irq_id_map[num_irq++] = (umac_reset - j);
} }
*num_irq_r = num_irq; *num_irq_r = num_irq;
} }

46
dp/wifi3.0/dp_umac_reset.c
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@@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
* *
* Permission to use, copy, modify, and/or distribute this software for any * Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above * purpose with or without fee is hereby granted, provided that the above
@@ -63,15 +63,17 @@ dp_umac_reset_send_setup_cmd(struct dp_soc *soc)
struct dp_htt_umac_reset_setup_cmd_params params; struct dp_htt_umac_reset_setup_cmd_params params;
umac_reset_ctx = &soc->umac_reset_ctx; umac_reset_ctx = &soc->umac_reset_ctx;
qdf_mem_zero(&params, sizeof(params));
ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP", ret = pld_get_user_msi_assignment(soc->osdev->dev, "DP",
&msi_vector_count, &msi_base_data, &msi_vector_count, &msi_base_data,
&msi_vector_start); &msi_vector_start);
if (ret) if (ret) {
return QDF_STATUS_E_FAILURE; params.msi_data = UMAC_RESET_IPC;
} else {
params.msi_data = (umac_reset_ctx->intr_offset %
msi_vector_count) + msi_base_data;
}
qdf_mem_zero(&params, sizeof(params));
params.msi_data = (umac_reset_ctx->intr_offset % msi_vector_count) +
msi_base_data;
params.shmem_addr_low = params.shmem_addr_low =
qdf_get_lower_32_bits(umac_reset_ctx->shmem_paddr_aligned); qdf_get_lower_32_bits(umac_reset_ctx->shmem_paddr_aligned);
params.shmem_addr_high = params.shmem_addr_high =
@@ -374,6 +376,7 @@ QDF_STATUS dp_umac_reset_interrupt_attach(struct dp_soc *soc)
int msi_vector_count, ret; int msi_vector_count, ret;
uint32_t msi_base_data, msi_vector_start; uint32_t msi_base_data, msi_vector_start;
uint32_t umac_reset_vector, umac_reset_irq; uint32_t umac_reset_vector, umac_reset_irq;
QDF_STATUS status;
if (!soc) { if (!soc) {
dp_umac_reset_err("DP SOC is null"); dp_umac_reset_err("DP SOC is null");
@@ -396,21 +399,28 @@ QDF_STATUS dp_umac_reset_interrupt_attach(struct dp_soc *soc)
&msi_vector_count, &msi_base_data, &msi_vector_count, &msi_base_data,
&msi_vector_start); &msi_vector_start);
if (ret) { if (ret) {
dp_umac_reset_err("UMAC reset is only supported in MSI interrupt mode"); /* UMAC reset uses IPC interrupt for AHB devices */
return QDF_STATUS_E_FAILURE; status = hif_get_umac_reset_irq(soc->hif_handle,
} &umac_reset_irq);
if (status) {
dp_umac_reset_err("get_umac_reset_irq failed status %d",
status);
return QDF_STATUS_E_FAILURE;
}
} else {
if (umac_reset_ctx->intr_offset < 0 ||
umac_reset_ctx->intr_offset >= WLAN_CFG_INT_NUM_CONTEXTS) {
dp_umac_reset_err("Invalid interrupt offset");
return QDF_STATUS_E_FAILURE;
}
if (umac_reset_ctx->intr_offset < 0 || umac_reset_vector = msi_vector_start +
umac_reset_ctx->intr_offset >= WLAN_CFG_INT_NUM_CONTEXTS) {
dp_umac_reset_err("Invalid interrupt offset");
return QDF_STATUS_E_FAILURE;
}
umac_reset_vector = msi_vector_start +
(umac_reset_ctx->intr_offset % msi_vector_count); (umac_reset_ctx->intr_offset % msi_vector_count);
/* Get IRQ number */ /* Get IRQ number */
umac_reset_irq = pld_get_msi_irq(soc->osdev->dev, umac_reset_vector); umac_reset_irq = pld_get_msi_irq(soc->osdev->dev,
umac_reset_vector);
}
/* Finally register to this IRQ from HIF layer */ /* Finally register to this IRQ from HIF layer */
return hif_register_umac_reset_handler( return hif_register_umac_reset_handler(

6
wlan_cfg/wlan_cfg.c
View File

@@ -886,6 +886,12 @@ static struct dp_int_mask_assignment dp_mask_assignment[NUM_INTERRUPT_COMBINATIO
/* tx mon ring masks */ /* tx mon ring masks */
{WLAN_CFG_TX_MON_RING_MASK_0, WLAN_CFG_TX_MON_RING_MASK_1, 0, {WLAN_CFG_TX_MON_RING_MASK_0, WLAN_CFG_TX_MON_RING_MASK_1, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
/* ppe ds wbm release ring ring mask */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
/* Reo2ppe ring mask */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
/* ppe2tcl ring mask */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
/* umac reset mask */ /* umac reset mask */
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
WLAN_CFG_UMAC_RESET_INTR_MASK_0}, WLAN_CFG_UMAC_RESET_INTR_MASK_0},

2
wlan_cfg/wlan_cfg.h
View File

@@ -106,6 +106,8 @@
#define WLAN_MAX_MLO_CHIPS 1 #define WLAN_MAX_MLO_CHIPS 1
#endif #endif
#define UMAC_RESET_IPC 451
struct wlan_cfg_dp_pdev_ctxt; struct wlan_cfg_dp_pdev_ctxt;
/** /**