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audio-lnx: Rename folders to new flat structure.

瀏覽代碼 
Kernel audio drivers can be categorised into below folders.
asoc - ALSA based drivers,
asoc/codecs - codec drivers,
ipc - APR IPC communication drivers,
dsp - DSP low level drivers/Audio ION/ADSP Loader,
dsp/codecs - Native encoders and decoders,
soc - SoC based drivers(pinctrl/regmap/soundwire)

Restructure drivers to above folder format.
Include directories also follow above format.

Change-Id: I8fa0857baaacd47db126fb5c1f1f5ed7e886dbc0
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
此提交包含在：
Laxminath Kasam
2017-08-01 22:02:15 +05:30
提交者 Martin Fick
父節點 84f7f73144
當前提交 605b42f92c
共有 269 個檔案被更改，包括 423 行新增 和 2706 行删除
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2
asoc/codecs/sdm660_cdc/Makefile 一般檔案
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snd-soc-sdm660-cdc-objs := msm-analog-cdc.o msm-digital-cdc.o sdm660-regmap.o
obj-$(CONFIG_SND_SOC_SDM660_CDC) += snd-soc-sdm660-cdc.o sdm660-cdc-irq.o

4691
asoc/codecs/sdm660_cdc/msm-analog-cdc.c 一般檔案
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240
asoc/codecs/sdm660_cdc/msm-analog-cdc.h 一般檔案
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/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_ANALOG_CDC_H
#define MSM_ANALOG_CDC_H
#include <sound/soc.h>
#include <sound/jack.h>
#include <dsp/q6afe-v2.h>
#include "../wcd-mbhc-v2.h"
#include "../wcdcal-hwdep.h"
#include "sdm660-cdc-registers.h"
#define MICBIAS_EXT_BYP_CAP 0x00
#define MICBIAS_NO_EXT_BYP_CAP 0x01
#define MSM89XX_NUM_IRQ_REGS 2
#define MAX_REGULATOR 7
#define MSM89XX_REG_VAL(reg, val) {reg, 0, val}
#define MSM89XX_VDD_SPKDRV_NAME "cdc-vdd-spkdrv"
#define DEFAULT_MULTIPLIER 800
#define DEFAULT_GAIN 9
#define DEFAULT_OFFSET 100
extern const u8 msm89xx_pmic_cdc_reg_readable[MSM89XX_PMIC_CDC_CACHE_SIZE];
extern const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE];
extern struct regmap_config msm89xx_cdc_core_regmap_config;
extern struct regmap_config msm89xx_pmic_cdc_regmap_config;
enum wcd_curr_ref {
I_h4_UA = 0,
I_pt5_UA,
I_14_UA,
I_l4_UA,
I_1_UA,
};
enum wcd_mbhc_imp_det_pin {
WCD_MBHC_DET_NONE = 0,
WCD_MBHC_DET_HPHL,
WCD_MBHC_DET_HPHR,
WCD_MBHC_DET_BOTH,
};
/* Each micbias can be assigned to one of three cfilters
* Vbatt_min >= .15V + ldoh_v
* ldoh_v >= .15v + cfiltx_mv
* If ldoh_v = 1.95 160 mv < cfiltx_mv < 1800 mv
* If ldoh_v = 2.35 200 mv < cfiltx_mv < 2200 mv
* If ldoh_v = 2.75 240 mv < cfiltx_mv < 2600 mv
* If ldoh_v = 2.85 250 mv < cfiltx_mv < 2700 mv
*/
struct wcd_micbias_setting {
u8 ldoh_v;
u32 cfilt1_mv; /* in mv */
u32 cfilt2_mv; /* in mv */
u32 cfilt3_mv; /* in mv */
/* Different WCD9xxx series codecs may not
* have 4 mic biases. If a codec has fewer
* mic biases, some of these properties will
* not be used.
*/
u8 bias1_cfilt_sel;
u8 bias2_cfilt_sel;
u8 bias3_cfilt_sel;
u8 bias4_cfilt_sel;
u8 bias1_cap_mode;
u8 bias2_cap_mode;
u8 bias3_cap_mode;
u8 bias4_cap_mode;
bool bias2_is_headset_only;
};
enum sdm660_cdc_pid_current {
MSM89XX_PID_MIC_2P5_UA,
MSM89XX_PID_MIC_5_UA,
MSM89XX_PID_MIC_10_UA,
MSM89XX_PID_MIC_20_UA,
};
struct sdm660_cdc_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
enum {
/* INTR_REG 0 - Digital Periph */
MSM89XX_IRQ_SPKR_CNP = 0,
MSM89XX_IRQ_SPKR_CLIP,
MSM89XX_IRQ_SPKR_OCP,
MSM89XX_IRQ_MBHC_INSREM_DET1,
MSM89XX_IRQ_MBHC_RELEASE,
MSM89XX_IRQ_MBHC_PRESS,
MSM89XX_IRQ_MBHC_INSREM_DET,
MSM89XX_IRQ_MBHC_HS_DET,
/* INTR_REG 1 - Analog Periph */
MSM89XX_IRQ_EAR_OCP,
MSM89XX_IRQ_HPHR_OCP,
MSM89XX_IRQ_HPHL_OCP,
MSM89XX_IRQ_EAR_CNP,
MSM89XX_IRQ_HPHR_CNP,
MSM89XX_IRQ_HPHL_CNP,
MSM89XX_NUM_IRQS,
};
enum {
ON_DEMAND_MICBIAS = 0,
ON_DEMAND_SPKDRV,
ON_DEMAND_SUPPLIES_MAX,
};
/*
* The delay list is per codec HW specification.
* Please add delay in the list in the future instead
* of magic number
*/
enum {
CODEC_DELAY_1_MS = 1000,
CODEC_DELAY_1_1_MS = 1100,
};
struct sdm660_cdc_regulator {
const char *name;
int min_uv;
int max_uv;
int optimum_ua;
bool ondemand;
struct regulator *regulator;
};
struct on_demand_supply {
struct regulator *supply;
atomic_t ref;
int min_uv;
int max_uv;
int optimum_ua;
};
struct wcd_imped_i_ref {
enum wcd_curr_ref curr_ref;
int min_val;
int multiplier;
int gain_adj;
int offset;
};
enum sdm660_cdc_micbias_num {
MSM89XX_MICBIAS1 = 0,
};
/* Hold instance to digital codec platform device */
struct msm_dig_ctrl_data {
struct platform_device *dig_pdev;
};
struct msm_dig_ctrl_platform_data {
void *handle;
void (*update_clkdiv)(void *handle, int val);
int (*get_cdc_version)(void *handle);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
struct sdm660_cdc_priv {
struct device *dev;
u32 num_of_supplies;
struct regulator_bulk_data *supplies;
struct snd_soc_codec *codec;
struct work_struct msm_anlg_add_child_devices_work;
struct msm_dig_ctrl_platform_data dig_plat_data;
/* digital codec data structure */
struct msm_dig_ctrl_data *dig_ctrl_data;
struct blocking_notifier_head notifier;
u16 pmic_rev;
u16 codec_version;
u16 analog_major_rev;
u32 boost_voltage;
u32 adc_count;
u32 rx_bias_count;
bool int_mclk0_enabled;
u16 boost_option;
/* mode to select hd2 */
u32 hph_mode;
/* compander used for each rx chain */
bool spk_boost_set;
bool ear_pa_boost_set;
bool ext_spk_boost_set;
struct on_demand_supply on_demand_list[ON_DEMAND_SUPPLIES_MAX];
struct regulator *spkdrv_reg;
struct blocking_notifier_head notifier_mbhc;
/* mbhc module */
struct wcd_mbhc mbhc;
/* cal info for codec */
struct fw_info *fw_data;
struct notifier_block audio_ssr_nb;
int (*codec_spk_ext_pa_cb)(struct snd_soc_codec *codec, int enable);
unsigned long status_mask;
struct wcd_imped_i_ref imped_i_ref;
enum wcd_mbhc_imp_det_pin imped_det_pin;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
};
struct sdm660_cdc_pdata {
struct wcd_micbias_setting micbias;
struct sdm660_cdc_regulator regulator[MAX_REGULATOR];
};
extern int msm_anlg_cdc_mclk_enable(struct snd_soc_codec *codec,
int mclk_enable, bool dapm);
extern int msm_anlg_cdc_hs_detect(struct snd_soc_codec *codec,
struct wcd_mbhc_config *mbhc_cfg);
extern void msm_anlg_cdc_hs_detect_exit(struct snd_soc_codec *codec);
extern void sdm660_cdc_update_int_spk_boost(bool enable);
extern void msm_anlg_cdc_spk_ext_pa_cb(
int (*codec_spk_ext_pa)(struct snd_soc_codec *codec,
int enable), struct snd_soc_codec *codec);
int msm_anlg_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
struct snd_soc_codec *codec);
#endif

67
asoc/codecs/sdm660_cdc/msm-cdc-common.h 一般檔案
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/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/regmap.h>
#include "sdm660-cdc-registers.h"
extern struct reg_default
msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE];
extern struct reg_default
msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE];
bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg);
bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg);
bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg);
enum {
AIF1_PB = 0,
AIF1_CAP,
AIF2_VIFEED,
AIF3_SVA,
NUM_CODEC_DAIS,
};
enum codec_versions {
TOMBAK_1_0,
TOMBAK_2_0,
CONGA,
CAJON,
CAJON_2_0,
DIANGU,
DRAX_CDC,
UNSUPPORTED,
};
/* Support different hph modes */
enum {
NORMAL_MODE = 0,
HD2_MODE,
};
enum dig_cdc_notify_event {
DIG_CDC_EVENT_INVALID,
DIG_CDC_EVENT_CLK_ON,
DIG_CDC_EVENT_CLK_OFF,
DIG_CDC_EVENT_RX1_MUTE_ON,
DIG_CDC_EVENT_RX1_MUTE_OFF,
DIG_CDC_EVENT_RX2_MUTE_ON,
DIG_CDC_EVENT_RX2_MUTE_OFF,
DIG_CDC_EVENT_RX3_MUTE_ON,
DIG_CDC_EVENT_RX3_MUTE_OFF,
DIG_CDC_EVENT_PRE_RX1_INT_ON,
DIG_CDC_EVENT_PRE_RX2_INT_ON,
DIG_CDC_EVENT_POST_RX1_INT_OFF,
DIG_CDC_EVENT_POST_RX2_INT_OFF,
DIG_CDC_EVENT_SSR_DOWN,
DIG_CDC_EVENT_SSR_UP,
DIG_CDC_EVENT_LAST,
};

2191
asoc/codecs/sdm660_cdc/msm-digital-cdc.c 一般檔案
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91
asoc/codecs/sdm660_cdc/msm-digital-cdc.h 一般檔案
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/* Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef MSM_DIGITAL_CDC_H
#define MSM_DIGITAL_CDC_H
#define HPHL_PA_DISABLE (0x01 << 1)
#define HPHR_PA_DISABLE (0x01 << 2)
#define SPKR_PA_DISABLE (0x01 << 3)
#define NUM_DECIMATORS 5
/* Codec supports 1 compander */
enum {
COMPANDER_NONE = 0,
COMPANDER_1, /* HPHL/R */
COMPANDER_MAX,
};
/* Number of output I2S port */
enum {
MSM89XX_RX1 = 0,
MSM89XX_RX2,
MSM89XX_RX3,
MSM89XX_RX_MAX,
};
struct msm_dig_priv {
struct snd_soc_codec *codec;
u32 comp_enabled[MSM89XX_RX_MAX];
int (*codec_hph_comp_gpio)(bool enable, struct snd_soc_codec *codec);
s32 dmic_1_2_clk_cnt;
s32 dmic_3_4_clk_cnt;
bool dec_active[NUM_DECIMATORS];
int version;
/* Entry for version info */
struct snd_info_entry *entry;
struct snd_info_entry *version_entry;
char __iomem *dig_base;
struct regmap *regmap;
struct notifier_block nblock;
u32 mute_mask;
int dapm_bias_off;
void *handle;
void (*update_clkdiv)(void *handle, int val);
int (*get_cdc_version)(void *handle);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
struct dig_ctrl_platform_data {
void *handle;
void (*update_clkdiv)(void *handle, int val);
int (*get_cdc_version)(void *handle);
int (*register_notifier)(void *handle,
struct notifier_block *nblock,
bool enable);
};
struct hpf_work {
struct msm_dig_priv *dig_cdc;
u32 decimator;
u8 tx_hpf_cut_of_freq;
struct delayed_work dwork;
};
/* Codec supports 5 bands */
enum {
BAND1 = 0,
BAND2,
BAND3,
BAND4,
BAND5,
BAND_MAX,
};
extern void msm_dig_cdc_hph_comp_cb(
int (*codec_hph_comp_gpio)(
bool enable, struct snd_soc_codec *codec),
struct snd_soc_codec *codec);
int msm_dig_codec_info_create_codec_entry(struct snd_info_entry *codec_root,
struct snd_soc_codec *codec);
#endif

413
asoc/codecs/sdm660_cdc/sdm660-cdc-irq.c 一般檔案
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/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/of_irq.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/slab.h>
#include <linux/spmi.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/interrupt.h>
#include <linux/pm_qos.h>
#include <soc/qcom/pm.h>
#include <sound/soc.h>
#include "msm-analog-cdc.h"
#include "sdm660-cdc-irq.h"
#include "sdm660-cdc-registers.h"
#define MAX_NUM_IRQS 14
#define NUM_IRQ_REGS 2
#define WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS 700
#define BYTE_BIT_MASK(nr) (1UL << ((nr) % BITS_PER_BYTE))
#define BIT_BYTE(nr) ((nr) / BITS_PER_BYTE)
static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data);
char *irq_names[MAX_NUM_IRQS] = {
"spk_cnp_int",
"spk_clip_int",
"spk_ocp_int",
"ins_rem_det1",
"but_rel_det",
"but_press_det",
"ins_rem_det",
"mbhc_int",
"ear_ocp_int",
"hphr_ocp_int",
"hphl_ocp_det",
"ear_cnp_int",
"hphr_cnp_int",
"hphl_cnp_int"
};
int order[MAX_NUM_IRQS] = {
MSM89XX_IRQ_SPKR_CNP,
MSM89XX_IRQ_SPKR_CLIP,
MSM89XX_IRQ_SPKR_OCP,
MSM89XX_IRQ_MBHC_INSREM_DET1,
MSM89XX_IRQ_MBHC_RELEASE,
MSM89XX_IRQ_MBHC_PRESS,
MSM89XX_IRQ_MBHC_INSREM_DET,
MSM89XX_IRQ_MBHC_HS_DET,
MSM89XX_IRQ_EAR_OCP,
MSM89XX_IRQ_HPHR_OCP,
MSM89XX_IRQ_HPHL_OCP,
MSM89XX_IRQ_EAR_CNP,
MSM89XX_IRQ_HPHR_CNP,
MSM89XX_IRQ_HPHL_CNP,
};
enum wcd9xxx_spmi_pm_state {
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE,
WCD9XXX_PM_ASLEEP,
};
struct wcd9xxx_spmi_map {
uint8_t handled[NUM_IRQ_REGS];
uint8_t mask[NUM_IRQ_REGS];
int linuxirq[MAX_NUM_IRQS];
irq_handler_t handler[MAX_NUM_IRQS];
struct platform_device *spmi[NUM_IRQ_REGS];
struct snd_soc_codec *codec;
enum wcd9xxx_spmi_pm_state pm_state;
struct mutex pm_lock;
/* pm_wq notifies change of pm_state */
wait_queue_head_t pm_wq;
struct pm_qos_request pm_qos_req;
int wlock_holders;
};
struct wcd9xxx_spmi_map map;
void wcd9xxx_spmi_enable_irq(int irq)
{
pr_debug("%s: irqno =%d\n", __func__, irq);
if (!(map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq))))
return;
map.mask[BIT_BYTE(irq)] &=
~(BYTE_BIT_MASK(irq));
enable_irq(map.linuxirq[irq]);
}
void wcd9xxx_spmi_disable_irq(int irq)
{
pr_debug("%s: irqno =%d\n", __func__, irq);
if (map.mask[BIT_BYTE(irq)] & (BYTE_BIT_MASK(irq)))
return;
map.mask[BIT_BYTE(irq)] |=
(BYTE_BIT_MASK(irq));
disable_irq_nosync(map.linuxirq[irq]);
}
int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler,
const char *name, void *priv)
{
int rc;
unsigned long irq_flags;
map.linuxirq[irq] =
platform_get_irq_byname(map.spmi[BIT_BYTE(irq)],
irq_names[irq]);
if (strcmp(name, "mbhc sw intr"))
irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_ONESHOT;
else
irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
IRQF_ONESHOT | IRQF_NO_SUSPEND;
pr_debug("%s: name:%s irq_flags = %lx\n", __func__, name, irq_flags);
rc = devm_request_threaded_irq(&map.spmi[BIT_BYTE(irq)]->dev,
map.linuxirq[irq], NULL,
wcd9xxx_spmi_irq_handler,
irq_flags,
name, priv);
if (rc < 0) {
dev_err(&map.spmi[BIT_BYTE(irq)]->dev,
"Can't request %d IRQ\n", irq);
return rc;
}
dev_dbg(&map.spmi[BIT_BYTE(irq)]->dev,
"irq %d linuxIRQ: %d\n", irq, map.linuxirq[irq]);
map.mask[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq);
map.handler[irq] = handler;
enable_irq_wake(map.linuxirq[irq]);
return 0;
}
int wcd9xxx_spmi_free_irq(int irq, void *priv)
{
devm_free_irq(&map.spmi[BIT_BYTE(irq)]->dev, map.linuxirq[irq],
priv);
map.mask[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq);
return 0;
}
static int get_irq_bit(int linux_irq)
{
int i = 0;
for (; i < MAX_NUM_IRQS; i++)
if (map.linuxirq[i] == linux_irq)
return i;
return i;
}
static int get_order_irq(int i)
{
return order[i];
}
static irqreturn_t wcd9xxx_spmi_irq_handler(int linux_irq, void *data)
{
int irq, i, j;
unsigned long status[NUM_IRQ_REGS] = {0};
if (unlikely(wcd9xxx_spmi_lock_sleep() == false)) {
pr_err("Failed to hold suspend\n");
return IRQ_NONE;
}
irq = get_irq_bit(linux_irq);
if (irq == MAX_NUM_IRQS)
return IRQ_HANDLED;
status[BIT_BYTE(irq)] |= BYTE_BIT_MASK(irq);
for (i = 0; i < NUM_IRQ_REGS; i++) {
status[i] |= snd_soc_read(map.codec,
BIT_BYTE(irq) * 0x100 +
MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS);
status[i] &= ~map.mask[i];
}
for (i = 0; i < MAX_NUM_IRQS; i++) {
j = get_order_irq(i);
if ((status[BIT_BYTE(j)] & BYTE_BIT_MASK(j)) &&
((map.handled[BIT_BYTE(j)] &
BYTE_BIT_MASK(j)) == 0)) {
map.handler[j](irq, data);
map.handled[BIT_BYTE(j)] |=
BYTE_BIT_MASK(j);
}
}
map.handled[BIT_BYTE(irq)] &= ~BYTE_BIT_MASK(irq);
wcd9xxx_spmi_unlock_sleep();
return IRQ_HANDLED;
}
enum wcd9xxx_spmi_pm_state wcd9xxx_spmi_pm_cmpxchg(
enum wcd9xxx_spmi_pm_state o,
enum wcd9xxx_spmi_pm_state n)
{
enum wcd9xxx_spmi_pm_state old;
mutex_lock(&map.pm_lock);
old = map.pm_state;
if (old == o)
map.pm_state = n;
pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state);
mutex_unlock(&map.pm_lock);
return old;
}
EXPORT_SYMBOL(wcd9xxx_spmi_pm_cmpxchg);
int wcd9xxx_spmi_suspend(pm_message_t pmesg)
{
int ret = 0;
pr_debug("%s: enter\n", __func__);
/*
* pm_qos_update_request() can be called after this suspend chain call
* started. thus suspend can be called while lock is being held
*/
mutex_lock(&map.pm_lock);
if (map.pm_state == WCD9XXX_PM_SLEEPABLE) {
pr_debug("%s: suspending system, state %d, wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
map.pm_state = WCD9XXX_PM_ASLEEP;
} else if (map.pm_state == WCD9XXX_PM_AWAKE) {
/*
* unlock to wait for pm_state == WCD9XXX_PM_SLEEPABLE
* then set to WCD9XXX_PM_ASLEEP
*/
pr_debug("%s: waiting to suspend system, state %d, wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
mutex_unlock(&map.pm_lock);
if (!(wait_event_timeout(map.pm_wq,
wcd9xxx_spmi_pm_cmpxchg(
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_ASLEEP) ==
WCD9XXX_PM_SLEEPABLE,
HZ))) {
pr_debug("%s: suspend failed state %d, wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
ret = -EBUSY;
} else {
pr_debug("%s: done, state %d, wlock %d\n", __func__,
map.pm_state,
map.wlock_holders);
}
mutex_lock(&map.pm_lock);
} else if (map.pm_state == WCD9XXX_PM_ASLEEP) {
pr_warn("%s: system is already suspended, state %d, wlock %dn",
__func__, map.pm_state,
map.wlock_holders);
}
mutex_unlock(&map.pm_lock);
return ret;
}
EXPORT_SYMBOL(wcd9xxx_spmi_suspend);
int wcd9xxx_spmi_resume(void)
{
int ret = 0;
pr_debug("%s: enter\n", __func__);
mutex_lock(&map.pm_lock);
if (map.pm_state == WCD9XXX_PM_ASLEEP) {
pr_debug("%s: resuming system, state %d, wlock %d\n", __func__,
map.pm_state,
map.wlock_holders);
map.pm_state = WCD9XXX_PM_SLEEPABLE;
} else {
pr_warn("%s: system is already awake, state %d wlock %d\n",
__func__, map.pm_state,
map.wlock_holders);
}
mutex_unlock(&map.pm_lock);
wake_up_all(&map.pm_wq);
return ret;
}
EXPORT_SYMBOL(wcd9xxx_spmi_resume);
bool wcd9xxx_spmi_lock_sleep(void)
{
/*
* wcd9xxx_spmi_{lock/unlock}_sleep will be called by
* wcd9xxx_spmi_irq_thread
* and its subroutines only motly.
* but btn0_lpress_fn is not wcd9xxx_spmi_irq_thread's subroutine and
* It can race with wcd9xxx_spmi_irq_thread.
* So need to embrace wlock_holders with mutex.
*/
mutex_lock(&map.pm_lock);
if (map.wlock_holders++ == 0) {
pr_debug("%s: holding wake lock\n", __func__);
pm_qos_update_request(&map.pm_qos_req,
msm_cpuidle_get_deep_idle_latency());
pm_stay_awake(&map.spmi[0]->dev);
}
mutex_unlock(&map.pm_lock);
pr_debug("%s: wake lock counter %d\n", __func__,
map.wlock_holders);
pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state);
if (!wait_event_timeout(map.pm_wq,
((wcd9xxx_spmi_pm_cmpxchg(
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE)) ==
WCD9XXX_PM_SLEEPABLE ||
(wcd9xxx_spmi_pm_cmpxchg(
WCD9XXX_PM_SLEEPABLE,
WCD9XXX_PM_AWAKE) ==
WCD9XXX_PM_AWAKE)),
msecs_to_jiffies(
WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS))) {
pr_warn("%s: system didn't resume within %dms, s %d, w %d\n",
__func__,
WCD9XXX_SYSTEM_RESUME_TIMEOUT_MS, map.pm_state,
map.wlock_holders);
wcd9xxx_spmi_unlock_sleep();
return false;
}
wake_up_all(&map.pm_wq);
pr_debug("%s: leaving pm_state = %d\n", __func__, map.pm_state);
return true;
}
EXPORT_SYMBOL(wcd9xxx_spmi_lock_sleep);
void wcd9xxx_spmi_unlock_sleep(void)
{
mutex_lock(&map.pm_lock);
if (--map.wlock_holders == 0) {
pr_debug("%s: releasing wake lock pm_state %d -> %d\n",
__func__, map.pm_state, WCD9XXX_PM_SLEEPABLE);
/*
* if wcd9xxx_spmi_lock_sleep failed, pm_state would be still
* WCD9XXX_PM_ASLEEP, don't overwrite
*/
if (likely(map.pm_state == WCD9XXX_PM_AWAKE))
map.pm_state = WCD9XXX_PM_SLEEPABLE;
pm_qos_update_request(&map.pm_qos_req,
PM_QOS_DEFAULT_VALUE);
pm_relax(&map.spmi[0]->dev);
}
mutex_unlock(&map.pm_lock);
pr_debug("%s: wake lock counter %d\n", __func__,
map.wlock_holders);
pr_debug("%s: map.pm_state = %d\n", __func__, map.pm_state);
wake_up_all(&map.pm_wq);
}
EXPORT_SYMBOL(wcd9xxx_spmi_unlock_sleep);
void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec)
{
map.codec = codec;
}
void wcd9xxx_spmi_set_dev(struct platform_device *spmi, int i)
{
if (i < NUM_IRQ_REGS)
map.spmi[i] = spmi;
}
int wcd9xxx_spmi_irq_init(void)
{
int i = 0;
for (; i < MAX_NUM_IRQS; i++)
map.mask[BIT_BYTE(i)] |= BYTE_BIT_MASK(i);
mutex_init(&map.pm_lock);
map.wlock_holders = 0;
map.pm_state = WCD9XXX_PM_SLEEPABLE;
init_waitqueue_head(&map.pm_wq);
pm_qos_add_request(&map.pm_qos_req,
PM_QOS_CPU_DMA_LATENCY,
PM_QOS_DEFAULT_VALUE);
return 0;
}
MODULE_DESCRIPTION("MSM8x16 SPMI IRQ driver");
MODULE_LICENSE("GPL v2");

34
asoc/codecs/sdm660_cdc/sdm660-cdc-irq.h 一般檔案
查看文件

@@ -0,0 +1,34 @@
/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __WCD9XXX_SPMI_IRQ_H__
#define __WCD9XXX_SPMI_IRQ_H__
#include <sound/soc.h>
#include <linux/spmi.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/pm_qos.h>
extern void wcd9xxx_spmi_enable_irq(int irq);
extern void wcd9xxx_spmi_disable_irq(int irq);
extern int wcd9xxx_spmi_request_irq(int irq, irq_handler_t handler,
const char *name, void *priv);
extern int wcd9xxx_spmi_free_irq(int irq, void *priv);
extern void wcd9xxx_spmi_set_codec(struct snd_soc_codec *codec);
extern void wcd9xxx_spmi_set_dev(struct platform_device *spmi, int i);
extern int wcd9xxx_spmi_irq_init(void);
extern int wcd9xxx_spmi_suspend(pm_message_t pmesg);
extern int wcd9xxx_spmi_resume(void);
bool wcd9xxx_spmi_lock_sleep(void);
void wcd9xxx_spmi_unlock_sleep(void);
#endif

603
asoc/codecs/sdm660_cdc/sdm660-cdc-registers.h 一般檔案
查看文件

@@ -0,0 +1,603 @@
/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SDM660_WCD_REGISTERS_H
#define SDM660_WCD_REGISTERS_H
#define CDC_DIG_BASE 0xF000
#define CDC_ANA_BASE 0xF100
#define MSM89XX_PMIC_DIGITAL_REVISION1 (CDC_DIG_BASE+0x000)
#define MSM89XX_PMIC_DIGITAL_REVISION1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_REVISION2 (CDC_DIG_BASE+0x001)
#define MSM89XX_PMIC_DIGITAL_REVISION2__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE (CDC_DIG_BASE+0x004)
#define MSM89XX_PMIC_DIGITAL_PERPH_TYPE__POR (0x23)
#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE (CDC_DIG_BASE+0x005)
#define MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE__POR (0x01)
#define MSM89XX_PMIC_DIGITAL_INT_RT_STS (CDC_DIG_BASE+0x010)
#define MSM89XX_PMIC_DIGITAL_INT_RT_STS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE (CDC_DIG_BASE+0x011)
#define MSM89XX_PMIC_DIGITAL_INT_SET_TYPE__POR (0xFF)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH (CDC_DIG_BASE+0x012)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH__POR (0xFF)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW (CDC_DIG_BASE+0x013)
#define MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR (CDC_DIG_BASE+0x014)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_EN_SET (CDC_DIG_BASE+0x015)
#define MSM89XX_PMIC_DIGITAL_INT_EN_SET__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR (CDC_DIG_BASE+0x016)
#define MSM89XX_PMIC_DIGITAL_INT_EN_CLR__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS (CDC_DIG_BASE+0x018)
#define MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS (CDC_DIG_BASE+0x019)
#define MSM89XX_PMIC_DIGITAL_INT_PENDING_STS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL (CDC_DIG_BASE+0x01A)
#define MSM89XX_PMIC_DIGITAL_INT_MID_SEL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY (CDC_DIG_BASE+0x01B)
#define MSM89XX_PMIC_DIGITAL_INT_PRIORITY__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_GPIO_MODE (CDC_DIG_BASE+0x040)
#define MSM89XX_PMIC_DIGITAL_GPIO_MODE__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE (CDC_DIG_BASE+0x041)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_OE__POR (0x01)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA (CDC_DIG_BASE+0x042)
#define MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PIN_STATUS (CDC_DIG_BASE+0x043)
#define MSM89XX_PMIC_DIGITAL_PIN_STATUS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL (CDC_DIG_BASE+0x044)
#define MSM89XX_PMIC_DIGITAL_HDRIVE_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL (CDC_DIG_BASE+0x046)
#define MSM89XX_PMIC_DIGITAL_CDC_RST_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL (CDC_DIG_BASE+0x048)
#define MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL (CDC_DIG_BASE+0x049)
#define MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL (CDC_DIG_BASE+0x04A)
#define MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL (CDC_DIG_BASE+0x050)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL__POR (0x02)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL (CDC_DIG_BASE+0x051)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL__POR (0x02)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL (CDC_DIG_BASE+0x052)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL (CDC_DIG_BASE+0x053)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL (CDC_DIG_BASE+0x054)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL (CDC_DIG_BASE+0x055)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL (CDC_DIG_BASE+0x056)
#define MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1 (CDC_DIG_BASE+0x058)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1__POR (0x7C)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2 (CDC_DIG_BASE+0x059)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2__POR (0x7C)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3 (CDC_DIG_BASE+0x05A)
#define MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3__POR (0x7C)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0 (CDC_DIG_BASE+0x05B)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1 (CDC_DIG_BASE+0x05C)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2 (CDC_DIG_BASE+0x05D)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3 (CDC_DIG_BASE+0x05E)
#define MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL (CDC_DIG_BASE+0x068)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN (CDC_DIG_BASE+0x069)
#define MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SPARE_0 (CDC_DIG_BASE+0x070)
#define MSM89XX_PMIC_DIGITAL_SPARE_0__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SPARE_1 (CDC_DIG_BASE+0x071)
#define MSM89XX_PMIC_DIGITAL_SPARE_1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SPARE_2 (CDC_DIG_BASE+0x072)
#define MSM89XX_PMIC_DIGITAL_SPARE_2__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS (CDC_DIG_BASE+0x0D0)
#define MSM89XX_PMIC_DIGITAL_SEC_ACCESS__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1 (CDC_DIG_BASE+0x0D8)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2 (CDC_DIG_BASE+0x0D9)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2__POR (0x01)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3 (CDC_DIG_BASE+0x0DA)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3__POR (0x05)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4 (CDC_DIG_BASE+0x0DB)
#define MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_TEST1 (CDC_DIG_BASE+0x0E0)
#define MSM89XX_PMIC_DIGITAL_INT_TEST1__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL (CDC_DIG_BASE+0x0E1)
#define MSM89XX_PMIC_DIGITAL_INT_TEST_VAL__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_TRIM_NUM (CDC_DIG_BASE+0x0F0)
#define MSM89XX_PMIC_DIGITAL_TRIM_NUM__POR (0x00)
#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL (CDC_DIG_BASE+0x0F1)
#define MSM89XX_PMIC_DIGITAL_TRIM_CTRL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION1 (CDC_ANA_BASE+0x00)
#define MSM89XX_PMIC_ANALOG_REVISION1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION2 (CDC_ANA_BASE+0x01)
#define MSM89XX_PMIC_ANALOG_REVISION2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION3 (CDC_ANA_BASE+0x02)
#define MSM89XX_PMIC_ANALOG_REVISION3__POR (0x00)
#define MSM89XX_PMIC_ANALOG_REVISION4 (CDC_ANA_BASE+0x03)
#define MSM89XX_PMIC_ANALOG_REVISION4__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PERPH_TYPE (CDC_ANA_BASE+0x04)
#define MSM89XX_PMIC_ANALOG_PERPH_TYPE__POR (0x23)
#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE (CDC_ANA_BASE+0x05)
#define MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE__POR (0x09)
#define MSM89XX_PMIC_ANALOG_INT_RT_STS (CDC_ANA_BASE+0x10)
#define MSM89XX_PMIC_ANALOG_INT_RT_STS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE (CDC_ANA_BASE+0x11)
#define MSM89XX_PMIC_ANALOG_INT_SET_TYPE__POR (0x3F)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH (CDC_ANA_BASE+0x12)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH__POR (0x3F)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW (CDC_ANA_BASE+0x13)
#define MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR (CDC_ANA_BASE+0x14)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_EN_SET (CDC_ANA_BASE+0x15)
#define MSM89XX_PMIC_ANALOG_INT_EN_SET__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_EN_CLR (CDC_ANA_BASE+0x16)
#define MSM89XX_PMIC_ANALOG_INT_EN_CLR__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS (CDC_ANA_BASE+0x18)
#define MSM89XX_PMIC_ANALOG_INT_LATCHED_STS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS (CDC_ANA_BASE+0x19)
#define MSM89XX_PMIC_ANALOG_INT_PENDING_STS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_MID_SEL (CDC_ANA_BASE+0x1A)
#define MSM89XX_PMIC_ANALOG_INT_MID_SEL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_PRIORITY (CDC_ANA_BASE+0x1B)
#define MSM89XX_PMIC_ANALOG_INT_PRIORITY__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MICB_1_EN (CDC_ANA_BASE+0x40)
#define MSM89XX_PMIC_ANALOG_MICB_1_EN__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MICB_1_VAL (CDC_ANA_BASE+0x41)
#define MSM89XX_PMIC_ANALOG_MICB_1_VAL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_MICB_1_CTL (CDC_ANA_BASE+0x42)
#define MSM89XX_PMIC_ANALOG_MICB_1_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS (CDC_ANA_BASE+0x43)
#define MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS__POR (0x49)
#define MSM89XX_PMIC_ANALOG_MICB_2_EN (CDC_ANA_BASE+0x44)
#define MSM89XX_PMIC_ANALOG_MICB_2_EN__POR (0x20)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2 (CDC_ANA_BASE+0x45)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL (CDC_ANA_BASE+0x46)
#define MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1 (CDC_ANA_BASE+0x47)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1__POR (0x35)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2 (CDC_ANA_BASE+0x50)
#define MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2__POR (0x08)
#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL (CDC_ANA_BASE+0x51)
#define MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER (CDC_ANA_BASE+0x52)
#define MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER__POR (0x98)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL (CDC_ANA_BASE+0x53)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL (CDC_ANA_BASE+0x54)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL (CDC_ANA_BASE+0x55)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL__POR (0x40)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL (CDC_ANA_BASE+0x56)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL__POR (0x61)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL (CDC_ANA_BASE+0x57)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL__POR (0x80)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT (CDC_ANA_BASE+0x58)
#define MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT__POR (0x00)
#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT (CDC_ANA_BASE+0x59)
#define MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TX_1_EN (CDC_ANA_BASE+0x60)
#define MSM89XX_PMIC_ANALOG_TX_1_EN__POR (0x03)
#define MSM89XX_PMIC_ANALOG_TX_2_EN (CDC_ANA_BASE+0x61)
#define MSM89XX_PMIC_ANALOG_TX_2_EN__POR (0x03)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1 (CDC_ANA_BASE+0x62)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1__POR (0xBF)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2 (CDC_ANA_BASE+0x63)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2__POR (0x8C)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL (CDC_ANA_BASE+0x64)
#define MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS (CDC_ANA_BASE+0x65)
#define MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS__POR (0x6B)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV (CDC_ANA_BASE+0x66)
#define MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV__POR (0x51)
#define MSM89XX_PMIC_ANALOG_TX_3_EN (CDC_ANA_BASE+0x67)
#define MSM89XX_PMIC_ANALOG_TX_3_EN__POR (0x02)
#define MSM89XX_PMIC_ANALOG_NCP_EN (CDC_ANA_BASE+0x80)
#define MSM89XX_PMIC_ANALOG_NCP_EN__POR (0x26)
#define MSM89XX_PMIC_ANALOG_NCP_CLK (CDC_ANA_BASE+0x81)
#define MSM89XX_PMIC_ANALOG_NCP_CLK__POR (0x23)
#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH (CDC_ANA_BASE+0x82)
#define MSM89XX_PMIC_ANALOG_NCP_DEGLITCH__POR (0x5B)
#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL (CDC_ANA_BASE+0x83)
#define MSM89XX_PMIC_ANALOG_NCP_FBCTRL__POR (0x08)
#define MSM89XX_PMIC_ANALOG_NCP_BIAS (CDC_ANA_BASE+0x84)
#define MSM89XX_PMIC_ANALOG_NCP_BIAS__POR (0x29)
#define MSM89XX_PMIC_ANALOG_NCP_VCTRL (CDC_ANA_BASE+0x85)
#define MSM89XX_PMIC_ANALOG_NCP_VCTRL__POR (0x24)
#define MSM89XX_PMIC_ANALOG_NCP_TEST (CDC_ANA_BASE+0x86)
#define MSM89XX_PMIC_ANALOG_NCP_TEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR (CDC_ANA_BASE+0x87)
#define MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR__POR (0xD5)
#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER (CDC_ANA_BASE+0x90)
#define MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER__POR (0xE8)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL (CDC_ANA_BASE+0x91)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL__POR (0xCF)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT (CDC_ANA_BASE+0x92)
#define MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT__POR (0x6E)
#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC (CDC_ANA_BASE+0x93)
#define MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC__POR (0x18)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA (CDC_ANA_BASE+0x94)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA__POR (0x5A)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP (CDC_ANA_BASE+0x95)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP__POR (0x69)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP (CDC_ANA_BASE+0x96)
#define MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP__POR (0x29)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN (CDC_ANA_BASE+0x97)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN__POR (0x80)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL (CDC_ANA_BASE+0x98)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL__POR (0xDA)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME (CDC_ANA_BASE+0x99)
#define MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME__POR (0x16)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST (CDC_ANA_BASE+0x9A)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL (CDC_ANA_BASE+0x9B)
#define MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST (CDC_ANA_BASE+0x9C)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL (CDC_ANA_BASE+0x9D)
#define MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL__POR (0x20)
#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL (CDC_ANA_BASE+0x9E)
#define MSM89XX_PMIC_ANALOG_RX_EAR_CTL___POR (0x12)
#define MSM89XX_PMIC_ANALOG_RX_ATEST (CDC_ANA_BASE+0x9F)
#define MSM89XX_PMIC_ANALOG_RX_ATEST__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS (CDC_ANA_BASE+0xA0)
#define MSM89XX_PMIC_ANALOG_RX_HPH_STATUS__POR (0x0C)
#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS (CDC_ANA_BASE+0xA1)
#define MSM89XX_PMIC_ANALOG_RX_EAR_STATUS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL (CDC_ANA_BASE+0xAC)
#define MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL (CDC_ANA_BASE+0xAD)
#define MSM89XX_PMIC_ANALOG_RX_RX_LO_EN_CTL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL (CDC_ANA_BASE+0xB0)
#define MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL__POR (0x83)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET (CDC_ANA_BASE+0xB1)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET__POR (0x91)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL (CDC_ANA_BASE+0xB2)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL__POR (0x29)
#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET (CDC_ANA_BASE+0xB3)
#define MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET__POR (0x4D)
#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL (CDC_ANA_BASE+0xB4)
#define MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL__POR (0xE1)
#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL (CDC_ANA_BASE+0xB5)
#define MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL__POR (0x1E)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC (CDC_ANA_BASE+0xB6)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC__POR (0xCB)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG (CDC_ANA_BASE+0xB7)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG__POR (0x00)
#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT (CDC_ANA_BASE+0xC0)
#define MSM89XX_PMIC_ANALOG_CURRENT_LIMIT__POR (0x02)
#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE (CDC_ANA_BASE+0xC1)
#define MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE__POR (0x14)
#define MSM89XX_PMIC_ANALOG_BYPASS_MODE (CDC_ANA_BASE+0xC2)
#define MSM89XX_PMIC_ANALOG_BYPASS_MODE__POR (0x00)
#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL (CDC_ANA_BASE+0xC3)
#define MSM89XX_PMIC_ANALOG_BOOST_EN_CTL__POR (0x1F)
#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO (CDC_ANA_BASE+0xC4)
#define MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO__POR (0x8C)
#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE (CDC_ANA_BASE+0xC5)
#define MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE__POR (0xC0)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1 (CDC_ANA_BASE+0xC6)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST1_1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2 (CDC_ANA_BASE+0xC7)
#define MSM89XX_PMIC_ANALOG_BOOST_TEST_2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS (CDC_ANA_BASE+0xC8)
#define MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS (CDC_ANA_BASE+0xC9)
#define MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR (CDC_ANA_BASE+0xCE)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL (CDC_ANA_BASE+0xCF)
#define MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_SEC_ACCESS (CDC_ANA_BASE+0xD0)
#define MSM89XX_PMIC_ANALOG_SEC_ACCESS__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1 (CDC_ANA_BASE+0xD8)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2 (CDC_ANA_BASE+0xD9)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2__POR (0x01)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3 (CDC_ANA_BASE+0xDA)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3__POR (0x05)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4 (CDC_ANA_BASE+0xDB)
#define MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_TEST1 (CDC_ANA_BASE+0xE0)
#define MSM89XX_PMIC_ANALOG_INT_TEST1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL (CDC_ANA_BASE+0xE1)
#define MSM89XX_PMIC_ANALOG_INT_TEST_VAL__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_NUM (CDC_ANA_BASE+0xF0)
#define MSM89XX_PMIC_ANALOG_TRIM_NUM__POR (0x04)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1 (CDC_ANA_BASE+0xF1)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL1__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2 (CDC_ANA_BASE+0xF2)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL2__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3 (CDC_ANA_BASE+0xF3)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL3__POR (0x00)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4 (CDC_ANA_BASE+0xF4)
#define MSM89XX_PMIC_ANALOG_TRIM_CTRL4__POR (0x00)
#define MSM89XX_PMIC_CDC_NUM_REGISTERS \
(MSM89XX_PMIC_ANALOG_TRIM_CTRL4+1)
#define MSM89XX_PMIC_CDC_MAX_REGISTER \
(MSM89XX_PMIC_CDC_NUM_REGISTERS-1)
#define MSM89XX_PMIC_CDC_CACHE_SIZE \
MSM89XX_PMIC_CDC_NUM_REGISTERS
#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL (0x00)
#define MSM89XX_CDC_CORE_CLK_RX_RESET_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL (0x04)
#define MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL (0x08)
#define MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL (0x0C)
#define MSM89XX_CDC_CORE_CLK_RX_I2S_CTL__POR (0x13)
#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL (0x10)
#define MSM89XX_CDC_CORE_CLK_TX_I2S_CTL__POR (0x13)
#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL (0x14)
#define MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL (0x18)
#define MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_OTHR_CTL (0x1C)
#define MSM89XX_CDC_CORE_CLK_OTHR_CTL__POR (0x04)
#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL (0x20)
#define MSM89XX_CDC_CORE_CLK_RX_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_MCLK_CTL (0x24)
#define MSM89XX_CDC_CORE_CLK_MCLK_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_PDM_CTL (0x28)
#define MSM89XX_CDC_CORE_CLK_PDM_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_SD_CTL (0x2C)
#define MSM89XX_CDC_CORE_CLK_SD_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL (0x30)
#define MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL (0x34)
#define MSM89XX_CDC_CORE_CLK_RX_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL (0x38)
#define MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL__POR (0x13)
#define MSM89XX_CDC_CORE_RX1_B1_CTL (0x40)
#define MSM89XX_CDC_CORE_RX1_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B1_CTL (0x60)
#define MSM89XX_CDC_CORE_RX2_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B1_CTL (0x80)
#define MSM89XX_CDC_CORE_RX3_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B2_CTL (0x44)
#define MSM89XX_CDC_CORE_RX1_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B2_CTL (0x64)
#define MSM89XX_CDC_CORE_RX2_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B2_CTL (0x84)
#define MSM89XX_CDC_CORE_RX3_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B3_CTL (0x48)
#define MSM89XX_CDC_CORE_RX1_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B3_CTL (0x68)
#define MSM89XX_CDC_CORE_RX2_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B3_CTL (0x88)
#define MSM89XX_CDC_CORE_RX3_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B4_CTL (0x4C)
#define MSM89XX_CDC_CORE_RX1_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B4_CTL (0x6C)
#define MSM89XX_CDC_CORE_RX2_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B4_CTL (0x8C)
#define MSM89XX_CDC_CORE_RX3_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_B5_CTL (0x50)
#define MSM89XX_CDC_CORE_RX1_B5_CTL__POR (0x68)
#define MSM89XX_CDC_CORE_RX2_B5_CTL (0x70)
#define MSM89XX_CDC_CORE_RX2_B5_CTL__POR (0x68)
#define MSM89XX_CDC_CORE_RX3_B5_CTL (0x90)
#define MSM89XX_CDC_CORE_RX3_B5_CTL__POR (0x68)
#define MSM89XX_CDC_CORE_RX1_B6_CTL (0x54)
#define MSM89XX_CDC_CORE_RX1_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_B6_CTL (0x74)
#define MSM89XX_CDC_CORE_RX2_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_B6_CTL (0x94)
#define MSM89XX_CDC_CORE_RX3_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL (0x58)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL (0x78)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL (0x98)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL (0x5C)
#define MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL (0x7C)
#define MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL (0x9C)
#define MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE (0xA0)
#define MSM89XX_CDC_CORE_TOP_GAIN_UPDATE__POR (0x00)
#define MSM89XX_CDC_CORE_TOP_CTL (0xA4)
#define MSM89XX_CDC_CORE_TOP_CTL__POR (0x01)
#define MSM89XX_CDC_CORE_COMP0_B1_CTL (0xB0)
#define MSM89XX_CDC_CORE_COMP0_B1_CTL__POR (0x30)
#define MSM89XX_CDC_CORE_COMP0_B2_CTL (0xB4)
#define MSM89XX_CDC_CORE_COMP0_B2_CTL__POR (0xB5)
#define MSM89XX_CDC_CORE_COMP0_B3_CTL (0xB8)
#define MSM89XX_CDC_CORE_COMP0_B3_CTL__POR (0x28)
#define MSM89XX_CDC_CORE_COMP0_B4_CTL (0xBC)
#define MSM89XX_CDC_CORE_COMP0_B4_CTL__POR (0x37)
#define MSM89XX_CDC_CORE_COMP0_B5_CTL (0xC0)
#define MSM89XX_CDC_CORE_COMP0_B5_CTL__POR (0x7F)
#define MSM89XX_CDC_CORE_COMP0_B6_CTL (0xC4)
#define MSM89XX_CDC_CORE_COMP0_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS (0xC8)
#define MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS__POR (0x03)
#define MSM89XX_CDC_CORE_COMP0_FS_CFG (0xCC)
#define MSM89XX_CDC_CORE_COMP0_FS_CFG__POR (0x03)
#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL (0xD0)
#define MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL__POR (0x02)
#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL (0xE0)
#define MSM89XX_CDC_CORE_DEBUG_DESER1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL (0xE4)
#define MSM89XX_CDC_CORE_DEBUG_DESER2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG (0xE8)
#define MSM89XX_CDC_CORE_DEBUG_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG (0xEC)
#define MSM89XX_CDC_CORE_DEBUG_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG (0xF0)
#define MSM89XX_CDC_CORE_DEBUG_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL (0x100)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL (0x140)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL (0x104)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL (0x144)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL (0x108)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL (0x148)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL (0x10C)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL (0x14C)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL (0x110)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL (0x150)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL (0x114)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL (0x154)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL (0x118)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL (0x158)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL (0x11C)
#define MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL (0x15C)
#define MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_CTL (0x120)
#define MSM89XX_CDC_CORE_IIR1_CTL__POR (0x40)
#define MSM89XX_CDC_CORE_IIR2_CTL (0x160)
#define MSM89XX_CDC_CORE_IIR2_CTL__POR (0x40)
#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL (0x124)
#define MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL (0x164)
#define MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL (0x128)
#define MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL (0x168)
#define MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL (0x12C)
#define MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL (0x16C)
#define MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL (0x180)
#define MSM89XX_CDC_CORE_CONN_RX1_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL (0x184)
#define MSM89XX_CDC_CORE_CONN_RX1_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL (0x188)
#define MSM89XX_CDC_CORE_CONN_RX1_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL (0x18C)
#define MSM89XX_CDC_CORE_CONN_RX2_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL (0x190)
#define MSM89XX_CDC_CORE_CONN_RX2_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL (0x194)
#define MSM89XX_CDC_CORE_CONN_RX2_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL (0x198)
#define MSM89XX_CDC_CORE_CONN_RX3_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL (0x19C)
#define MSM89XX_CDC_CORE_CONN_RX3_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL (0x1A0)
#define MSM89XX_CDC_CORE_CONN_TX_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL (0x1A4)
#define MSM89XX_CDC_CORE_CONN_TX_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL (0x1A8)
#define MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL (0x1AC)
#define MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL (0x1B0)
#define MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL (0x1B4)
#define MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL (0x1B8)
#define MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL (0x1BC)
#define MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL (0x1C0)
#define MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL (0x1C4)
#define MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL (0x1C8)
#define MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL (0x1CC)
#define MSM89XX_CDC_CORE_CONN_TX_B3_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER (0x1E0)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN (0x1E4)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG (0x1E8)
#define MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_MUX_CTL (0x1EC)
#define MSM89XX_CDC_CORE_TX5_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL (0x1F0)
#define MSM89XX_CDC_CORE_TX5_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX5_DMIC_CTL (0x1F4)
#define MSM89XX_CDC_CORE_TX5_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER (0x280)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER (0x2A0)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER (0x2C0)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER (0x2E0)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN (0x284)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN (0x2A4)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN (0x2C4)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN (0x2E4)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG (0x288)
#define MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG (0x2A8)
#define MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG (0x2C8)
#define MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG (0x2E8)
#define MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_MUX_CTL (0x28C)
#define MSM89XX_CDC_CORE_TX1_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_MUX_CTL (0x2AC)
#define MSM89XX_CDC_CORE_TX2_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_MUX_CTL (0x2CC)
#define MSM89XX_CDC_CORE_TX3_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_MUX_CTL (0x2EC)
#define MSM89XX_CDC_CORE_TX4_MUX_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL (0x290)
#define MSM89XX_CDC_CORE_TX1_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL (0x2B0)
#define MSM89XX_CDC_CORE_TX2_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL (0x2D0)
#define MSM89XX_CDC_CORE_TX3_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL (0x2F0)
#define MSM89XX_CDC_CORE_TX4_CLK_FS_CTL__POR (0x03)
#define MSM89XX_CDC_CORE_TX1_DMIC_CTL (0x294)
#define MSM89XX_CDC_CORE_TX1_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX2_DMIC_CTL (0x2B4)
#define MSM89XX_CDC_CORE_TX2_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX3_DMIC_CTL (0x2D4)
#define MSM89XX_CDC_CORE_TX3_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_TX4_DMIC_CTL (0x2F4)
#define MSM89XX_CDC_CORE_TX4_DMIC_CTL__POR (0x00)
#define MSM89XX_CDC_CORE_NUM_REGISTERS \
(MSM89XX_CDC_CORE_TX4_DMIC_CTL+1)
#define MSM89XX_CDC_CORE_MAX_REGISTER \
(MSM89XX_CDC_CORE_NUM_REGISTERS-1)
#define MSM89XX_CDC_CORE_CACHE_SIZE \
MSM89XX_CDC_CORE_NUM_REGISTERS
#endif

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asoc/codecs/sdm660_cdc/sdm660-regmap.c 一般檔案
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/*
* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/regmap.h>
#include "msm-cdc-common.h"
#include "sdm660-cdc-registers.h"
/*
* Default register reset values that are common across different versions
* are defined here. If a register reset value is changed based on version
* then remove it from this structure and add it in version specific
* structures.
*/
struct reg_default
msm89xx_cdc_core_defaults[MSM89XX_CDC_CORE_CACHE_SIZE] = {
{MSM89XX_CDC_CORE_CLK_RX_RESET_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_RX_I2S_CTL, 0x13},
{MSM89XX_CDC_CORE_CLK_TX_I2S_CTL, 0x13},
{MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_OTHR_CTL, 0x04},
{MSM89XX_CDC_CORE_CLK_RX_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_MCLK_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_PDM_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_SD_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_RX_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL, 0x13},
{MSM89XX_CDC_CORE_RX1_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_B5_CTL, 0x68},
{MSM89XX_CDC_CORE_RX2_B5_CTL, 0x68},
{MSM89XX_CDC_CORE_RX3_B5_CTL, 0x68},
{MSM89XX_CDC_CORE_RX1_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_TOP_GAIN_UPDATE, 0x00},
{MSM89XX_CDC_CORE_TOP_CTL, 0x01},
{MSM89XX_CDC_CORE_COMP0_B1_CTL, 0x30},
{MSM89XX_CDC_CORE_COMP0_B2_CTL, 0xB5},
{MSM89XX_CDC_CORE_COMP0_B3_CTL, 0x28},
{MSM89XX_CDC_CORE_COMP0_B4_CTL, 0x37},
{MSM89XX_CDC_CORE_COMP0_B5_CTL, 0x7F},
{MSM89XX_CDC_CORE_COMP0_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS, 0x03},
{MSM89XX_CDC_CORE_COMP0_FS_CFG, 0x03},
{MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL, 0x02},
{MSM89XX_CDC_CORE_DEBUG_DESER1_CTL, 0x00},
{MSM89XX_CDC_CORE_DEBUG_DESER2_CTL, 0x00},
{MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_CTL, 0x40},
{MSM89XX_CDC_CORE_IIR2_CTL, 0x40},
{MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX1_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX1_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX1_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX2_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX2_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX2_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX3_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_RX3_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL, 0x00},
{MSM89XX_CDC_CORE_CONN_TX_B3_CTL, 0x00},
{MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX5_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX5_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX5_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER, 0x00},
{MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN, 0x00},
{MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG, 0x00},
{MSM89XX_CDC_CORE_TX1_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX2_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX3_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX4_MUX_CTL, 0x00},
{MSM89XX_CDC_CORE_TX1_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX2_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX3_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX4_CLK_FS_CTL, 0x03},
{MSM89XX_CDC_CORE_TX1_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX2_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX3_DMIC_CTL, 0x00},
{MSM89XX_CDC_CORE_TX4_DMIC_CTL, 0x00},
};
struct reg_default
msm89xx_pmic_cdc_defaults[MSM89XX_PMIC_CDC_CACHE_SIZE] = {
{MSM89XX_PMIC_DIGITAL_REVISION1, 0x00},
{MSM89XX_PMIC_DIGITAL_REVISION2, 0x00},
{MSM89XX_PMIC_DIGITAL_PERPH_TYPE, 0x23},
{MSM89XX_PMIC_DIGITAL_PERPH_SUBTYPE, 0x01},
{MSM89XX_PMIC_DIGITAL_INT_RT_STS, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_SET_TYPE, 0xFF},
{MSM89XX_PMIC_DIGITAL_INT_POLARITY_HIGH, 0xFF},
{MSM89XX_PMIC_DIGITAL_INT_POLARITY_LOW, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_LATCHED_CLR, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_EN_SET, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_EN_CLR, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_LATCHED_STS, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_PENDING_STS, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_MID_SEL, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_PRIORITY, 0x00},
{MSM89XX_PMIC_DIGITAL_GPIO_MODE, 0x00},
{MSM89XX_PMIC_DIGITAL_PIN_CTL_OE, 0x01},
{MSM89XX_PMIC_DIGITAL_PIN_CTL_DATA, 0x00},
{MSM89XX_PMIC_DIGITAL_PIN_STATUS, 0x00},
{MSM89XX_PMIC_DIGITAL_HDRIVE_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_RST_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_TOP_CLK_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_ANA_CLK_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_DIG_CLK_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_TX1_CTL, 0x02},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_TX2_CTL, 0x02},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_HPHR_DAC_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX1_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX2_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX3_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_CONN_RX_LB_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL1, 0x7C},
{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL2, 0x7C},
{MSM89XX_PMIC_DIGITAL_CDC_RX_CTL3, 0x7C},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA0, 0x00},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA1, 0x00},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA2, 0x00},
{MSM89XX_PMIC_DIGITAL_DEM_BYPASS_DATA3, 0x00},
{MSM89XX_PMIC_DIGITAL_DIG_DEBUG_CTL, 0x00},
{MSM89XX_PMIC_DIGITAL_DIG_DEBUG_EN, 0x00},
{MSM89XX_PMIC_DIGITAL_SPARE_0, 0x00},
{MSM89XX_PMIC_DIGITAL_SPARE_1, 0x00},
{MSM89XX_PMIC_DIGITAL_SPARE_2, 0x00},
{MSM89XX_PMIC_DIGITAL_SEC_ACCESS, 0x00},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL1, 0x00},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL2, 0x02},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL3, 0x05},
{MSM89XX_PMIC_DIGITAL_PERPH_RESET_CTL4, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_TEST1, 0x00},
{MSM89XX_PMIC_DIGITAL_INT_TEST_VAL, 0x00},
{MSM89XX_PMIC_DIGITAL_TRIM_NUM, 0x00},
{MSM89XX_PMIC_DIGITAL_TRIM_CTRL, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION1, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION2, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION3, 0x00},
{MSM89XX_PMIC_ANALOG_REVISION4, 0x00},
{MSM89XX_PMIC_ANALOG_PERPH_TYPE, 0x23},
{MSM89XX_PMIC_ANALOG_PERPH_SUBTYPE, 0x09},
{MSM89XX_PMIC_ANALOG_INT_RT_STS, 0x00},
{MSM89XX_PMIC_ANALOG_INT_SET_TYPE, 0x3F},
{MSM89XX_PMIC_ANALOG_INT_POLARITY_HIGH, 0x3F},
{MSM89XX_PMIC_ANALOG_INT_POLARITY_LOW, 0x00},
{MSM89XX_PMIC_ANALOG_INT_LATCHED_CLR, 0x00},
{MSM89XX_PMIC_ANALOG_INT_EN_SET, 0x00},
{MSM89XX_PMIC_ANALOG_INT_EN_CLR, 0x00},
{MSM89XX_PMIC_ANALOG_INT_LATCHED_STS, 0x00},
{MSM89XX_PMIC_ANALOG_INT_PENDING_STS, 0x00},
{MSM89XX_PMIC_ANALOG_INT_MID_SEL, 0x00},
{MSM89XX_PMIC_ANALOG_INT_PRIORITY, 0x00},
{MSM89XX_PMIC_ANALOG_MICB_1_EN, 0x00},
{MSM89XX_PMIC_ANALOG_MICB_1_VAL, 0x20},
{MSM89XX_PMIC_ANALOG_MICB_1_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MICB_1_INT_RBIAS, 0x49},
{MSM89XX_PMIC_ANALOG_MICB_2_EN, 0x20},
{MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL_2, 0x00},
{MSM89XX_PMIC_ANALOG_MASTER_BIAS_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_1, 0x35},
{MSM89XX_PMIC_ANALOG_MBHC_DET_CTL_2, 0x08},
{MSM89XX_PMIC_ANALOG_MBHC_FSM_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_DBNC_TIMER, 0x98},
{MSM89XX_PMIC_ANALOG_MBHC_BTN0_ZDETL_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_BTN1_ZDETM_CTL, 0x20},
{MSM89XX_PMIC_ANALOG_MBHC_BTN2_ZDETH_CTL, 0x40},
{MSM89XX_PMIC_ANALOG_MBHC_BTN3_CTL, 0x61},
{MSM89XX_PMIC_ANALOG_MBHC_BTN4_CTL, 0x80},
{MSM89XX_PMIC_ANALOG_MBHC_BTN_RESULT, 0x00},
{MSM89XX_PMIC_ANALOG_MBHC_ZDET_ELECT_RESULT, 0x00},
{MSM89XX_PMIC_ANALOG_TX_1_EN, 0x03},
{MSM89XX_PMIC_ANALOG_TX_2_EN, 0x03},
{MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_1, 0xBF},
{MSM89XX_PMIC_ANALOG_TX_1_2_TEST_CTL_2, 0x8C},
{MSM89XX_PMIC_ANALOG_TX_1_2_ATEST_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_TX_1_2_OPAMP_BIAS, 0x6B},
{MSM89XX_PMIC_ANALOG_TX_1_2_TXFE_CLKDIV, 0x51},
{MSM89XX_PMIC_ANALOG_TX_3_EN, 0x02},
{MSM89XX_PMIC_ANALOG_NCP_EN, 0x26},
{MSM89XX_PMIC_ANALOG_NCP_CLK, 0x23},
{MSM89XX_PMIC_ANALOG_NCP_DEGLITCH, 0x5B},
{MSM89XX_PMIC_ANALOG_NCP_FBCTRL, 0x08},
{MSM89XX_PMIC_ANALOG_NCP_BIAS, 0x29},
{MSM89XX_PMIC_ANALOG_NCP_VCTRL, 0x24},
{MSM89XX_PMIC_ANALOG_NCP_TEST, 0x00},
{MSM89XX_PMIC_ANALOG_NCP_CLIM_ADDR, 0xD5},
{MSM89XX_PMIC_ANALOG_RX_CLOCK_DIVIDER, 0xE8},
{MSM89XX_PMIC_ANALOG_RX_COM_OCP_CTL, 0xCF},
{MSM89XX_PMIC_ANALOG_RX_COM_OCP_COUNT, 0x6E},
{MSM89XX_PMIC_ANALOG_RX_COM_BIAS_DAC, 0x18},
{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_PA, 0x5A},
{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_LDO_OCP, 0x69},
{MSM89XX_PMIC_ANALOG_RX_HPH_BIAS_CNP, 0x29},
{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_EN, 0x80},
{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_CTL, 0xDA},
{MSM89XX_PMIC_ANALOG_RX_HPH_CNP_WG_TIME, 0x16},
{MSM89XX_PMIC_ANALOG_RX_HPH_L_TEST, 0x00},
{MSM89XX_PMIC_ANALOG_RX_HPH_L_PA_DAC_CTL, 0x20},
{MSM89XX_PMIC_ANALOG_RX_HPH_R_TEST, 0x00},
{MSM89XX_PMIC_ANALOG_RX_HPH_R_PA_DAC_CTL, 0x20},
{MSM89XX_PMIC_ANALOG_RX_EAR_CTL, 0x12},
{MSM89XX_PMIC_ANALOG_RX_ATEST, 0x00},
{MSM89XX_PMIC_ANALOG_RX_HPH_STATUS, 0x0C},
{MSM89XX_PMIC_ANALOG_RX_EAR_STATUS, 0x00},
{MSM89XX_PMIC_ANALOG_RX_LO_DAC_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_RX_LO_EN_CTL, 0x00},
{MSM89XX_PMIC_ANALOG_SPKR_DAC_CTL, 0x83},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_CLIP_DET, 0x91},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_CTL, 0x29},
{MSM89XX_PMIC_ANALOG_SPKR_ANA_BIAS_SET, 0x4D},
{MSM89XX_PMIC_ANALOG_SPKR_OCP_CTL, 0xE1},
{MSM89XX_PMIC_ANALOG_SPKR_PWRSTG_CTL, 0x1E},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_MISC, 0xCB},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_DBG, 0x00},
{MSM89XX_PMIC_ANALOG_CURRENT_LIMIT, 0x02},
{MSM89XX_PMIC_ANALOG_OUTPUT_VOLTAGE, 0x14},
{MSM89XX_PMIC_ANALOG_BYPASS_MODE, 0x00},
{MSM89XX_PMIC_ANALOG_BOOST_EN_CTL, 0x1F},
{MSM89XX_PMIC_ANALOG_SLOPE_COMP_IP_ZERO, 0x8C},
{MSM89XX_PMIC_ANALOG_RDSON_MAX_DUTY_CYCLE, 0xC0},
{MSM89XX_PMIC_ANALOG_BOOST_TEST1_1, 0x00},
{MSM89XX_PMIC_ANALOG_BOOST_TEST_2, 0x00},
{MSM89XX_PMIC_ANALOG_SPKR_SAR_STATUS, 0x00},
{MSM89XX_PMIC_ANALOG_SPKR_DRV_STATUS, 0x00},
{MSM89XX_PMIC_ANALOG_PBUS_ADD_CSR, 0x00},
{MSM89XX_PMIC_ANALOG_PBUS_ADD_SEL, 0x00},
{MSM89XX_PMIC_ANALOG_SEC_ACCESS, 0x00},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL1, 0x00},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL2, 0x01},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL3, 0x05},
{MSM89XX_PMIC_ANALOG_PERPH_RESET_CTL4, 0x00},
{MSM89XX_PMIC_ANALOG_INT_TEST1, 0x00},
{MSM89XX_PMIC_ANALOG_INT_TEST_VAL, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_NUM, 0x04},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL1, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL2, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL3, 0x00},
{MSM89XX_PMIC_ANALOG_TRIM_CTRL4, 0x00},
};
static const u8 msm89xx_cdc_core_reg_readable[MSM89XX_CDC_CORE_CACHE_SIZE] = {
[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,
[MSM89XX_CDC_CORE_TOP_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_SHUT_DOWN_STATUS] = 1,
[MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1,
[MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,
};
static const u8 msm89xx_cdc_core_reg_writeable[MSM89XX_CDC_CORE_CACHE_SIZE] = {
[MSM89XX_CDC_CORE_CLK_RX_RESET_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_RESET_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX_CLK_EN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_OTHR_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_MCLK_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_PDM_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_SD_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_DMIC_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_RX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CLK_TX2_I2S_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B3_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B4_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B5_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_B6_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B1_CTL] = 1,
[MSM89XX_CDC_CORE_RX1_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX2_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_RX3_VOL_CTL_B2_CTL] = 1,
[MSM89XX_CDC_CORE_TOP_GAIN_UPDATE] = 1,
[MSM89XX_CDC_CORE_TOP_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B1_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B2_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B3_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B4_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B5_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_B6_CTL] = 1,
[MSM89XX_CDC_CORE_COMP0_FS_CFG] = 1,
[MSM89XX_CDC_CORE_COMP0_DELAY_BUF_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER1_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_DESER2_CTL] = 1,
[MSM89XX_CDC_CORE_DEBUG_B1_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B2_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_DEBUG_B3_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B3_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B4_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B5_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B6_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B7_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_B8_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_GAIN_TIMER_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL] = 1,
[MSM89XX_CDC_CORE_IIR1_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_IIR2_COEF_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_RX3_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ1_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B2_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B3_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_EQ2_B4_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_I2S_SD1_CTL] = 1,
[MSM89XX_CDC_CORE_CONN_TX_B3_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX1_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_TIMER] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_GAIN] = 1,
[MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG] = 1,
[MSM89XX_CDC_CORE_TX5_MUX_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_CLK_FS_CTL] = 1,
[MSM89XX_CDC_CORE_TX5_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX1_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX2_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX3_DMIC_CTL] = 1,
[MSM89XX_CDC_CORE_TX4_DMIC_CTL] = 1,
};
bool msm89xx_cdc_core_readable_reg(struct device *dev, unsigned int reg)
{
return msm89xx_cdc_core_reg_readable[reg];
}
bool msm89xx_cdc_core_writeable_reg(struct device *dev, unsigned int reg)
{
return msm89xx_cdc_core_reg_writeable[reg];
}
bool msm89xx_cdc_core_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MSM89XX_CDC_CORE_RX1_B1_CTL:
case MSM89XX_CDC_CORE_RX2_B1_CTL:
case MSM89XX_CDC_CORE_RX3_B1_CTL:
case MSM89XX_CDC_CORE_RX1_B6_CTL:
case MSM89XX_CDC_CORE_RX2_B6_CTL:
case MSM89XX_CDC_CORE_RX3_B6_CTL:
case MSM89XX_CDC_CORE_TX1_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX2_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX3_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX4_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_TX5_VOL_CTL_CFG:
case MSM89XX_CDC_CORE_IIR1_COEF_B1_CTL:
case MSM89XX_CDC_CORE_IIR2_COEF_B1_CTL:
case MSM89XX_CDC_CORE_CLK_MCLK_CTL:
case MSM89XX_CDC_CORE_CLK_PDM_CTL:
return true;
default:
return false;
}
}