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disp: msm: sde: pre-downscale support for inline rotation v2

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Add support for enabling pre-downscale block to increase the
maximum downscale capability for true inline rotation use cases.

Change-Id: Ifa544bb0ae69439abef4bd427134290090fe7230
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This commit is contained in:
Steve Cohen
2019-08-01 12:18:14 -04:00
parent 5a55e2d121
commit 60133f5ebb
7 changed files with 193 additions and 40 deletions
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22
msm/sde/sde_hw_sspp.c
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@@ -67,7 +67,8 @@
#define SSPP_SRC_CONSTANT_COLOR 0x3c
#define SSPP_EXCL_REC_CTL 0x40
#define SSPP_UBWC_STATIC_CTRL 0x44
#define SSPP_FETCH_CONFIG 0x048
#define SSPP_FETCH_CONFIG 0x48
#define SSPP_PRE_DOWN_SCALE 0x50
#define SSPP_DANGER_LUT 0x60
#define SSPP_SAFE_LUT 0x64
#define SSPP_CREQ_LUT 0x68
@@ -596,6 +597,22 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx,
ctx->cap->sblk->scaler_blk.version, idx, sspp->layout.format);
}
static void sde_hw_sspp_setup_pre_downscale(struct sde_hw_pipe *ctx,
struct sde_hw_inline_pre_downscale_cfg *pre_down)
{
u32 idx, val;
if (!ctx || !pre_down || _sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))
return;
val = pre_down->pre_downscale_x_0 |
(pre_down->pre_downscale_x_1 << 4) |
(pre_down->pre_downscale_y_0 << 8) |
(pre_down->pre_downscale_y_1 << 12);
SDE_REG_WRITE(&ctx->hw, SSPP_PRE_DOWN_SCALE + idx, val);
}
static u32 _sde_hw_sspp_get_scaler3_ver(struct sde_hw_pipe *ctx)
{
u32 idx;
@@ -1242,6 +1259,9 @@ static void _setup_layer_ops(struct sde_hw_pipe *c,
c->ops.setup_scaler = reg_dmav1_setup_vig_qseed3;
}
if (test_bit(SDE_SSPP_PREDOWNSCALE, &features))
c->ops.setup_pre_downscale = sde_hw_sspp_setup_pre_downscale;
if (test_bit(SDE_PERF_SSPP_SYS_CACHE, &perf_features))
c->ops.setup_sys_cache = sde_hw_sspp_setup_sys_cache;