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cnss2: Add DP rings to host SSR dump

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Add DP rings to host SSR dump.

Change-Id: I6e2462085ee41e60cfd2e5772f03d081af86617f
CRs-Fixed: 3604908
This commit is contained in:
Amit Mehta
2023-08-10 22:01:22 -07:00
committed by Rahul Choudhary
parent a883a8f321
commit 600b1dfc1c
4 changed files with 226 additions and 29 deletions
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104
cnss2/main.c
View File

@@ -3269,7 +3269,98 @@ int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
[CNSS_HOST_CE_HISTORY_MAX] = "hif_ce_history_max", [CNSS_HOST_CE_HISTORY_MAX] = "hif_ce_history_max",
[CNSS_HOST_ONLY_FOR_CRIT_CE] = "hif_ce_only_for_crit", [CNSS_HOST_ONLY_FOR_CRIT_CE] = "hif_ce_only_for_crit",
[CNSS_HOST_HIF_EVENT_HISTORY] = "hif_event_history", [CNSS_HOST_HIF_EVENT_HISTORY] = "hif_event_history",
[CNSS_HOST_HIF_EVENT_HIST_MAX] = "hif_event_hist_max" [CNSS_HOST_HIF_EVENT_HIST_MAX] = "hif_event_hist_max",
[CNSS_HOST_DP_WBM_DESC_REL] = "wbm_desc_rel_ring",
[CNSS_HOST_DP_WBM_DESC_REL_HANDLE] = "wbm_desc_rel_ring_handle",
[CNSS_HOST_DP_TCL_CMD] = "tcl_cmd_ring",
[CNSS_HOST_DP_TCL_CMD_HANDLE] = "tcl_cmd_ring_handle",
[CNSS_HOST_DP_TCL_STATUS] = "tcl_status_ring",
[CNSS_HOST_DP_TCL_STATUS_HANDLE] = "tcl_status_ring_handle",
[CNSS_HOST_DP_REO_REINJ] = "reo_reinject_ring",
[CNSS_HOST_DP_REO_REINJ_HANDLE] = "reo_reinject_ring_handle",
[CNSS_HOST_DP_RX_REL] = "rx_rel_ring",
[CNSS_HOST_DP_RX_REL_HANDLE] = "rx_rel_ring_handle",
[CNSS_HOST_DP_REO_EXP] = "reo_exception_ring",
[CNSS_HOST_DP_REO_EXP_HANDLE] = "reo_exception_ring_handle",
[CNSS_HOST_DP_REO_CMD] = "reo_cmd_ring",
[CNSS_HOST_DP_REO_CMD_HANDLE] = "reo_cmd_ring_handle",
[CNSS_HOST_DP_REO_STATUS] = "reo_status_ring",
[CNSS_HOST_DP_REO_STATUS_HANDLE] = "reo_status_ring_handle",
[CNSS_HOST_DP_TCL_DATA_0] = "tcl_data_ring_0",
[CNSS_HOST_DP_TCL_DATA_0_HANDLE] = "tcl_data_ring_0_handle",
[CNSS_HOST_DP_TX_COMP_0] = "tx_comp_ring_0",
[CNSS_HOST_DP_TX_COMP_0_HANDLE] = "tx_comp_ring_0_handle",
[CNSS_HOST_DP_TCL_DATA_1] = "tcl_data_ring_1",
[CNSS_HOST_DP_TCL_DATA_1_HANDLE] = "tcl_data_ring_1_handle",
[CNSS_HOST_DP_TX_COMP_1] = "tx_comp_ring_1",
[CNSS_HOST_DP_TX_COMP_1_HANDLE] = "tx_comp_ring_1_handle",
[CNSS_HOST_DP_TCL_DATA_2] = "tcl_data_ring_2",
[CNSS_HOST_DP_TCL_DATA_2_HANDLE] = "tcl_data_ring_2_handle",
[CNSS_HOST_DP_TX_COMP_2] = "tx_comp_ring_2",
[CNSS_HOST_DP_TX_COMP_2_HANDLE] = "tx_comp_ring_2_handle",
[CNSS_HOST_DP_REO_DST_0] = "reo_dest_ring_0",
[CNSS_HOST_DP_REO_DST_0_HANDLE] = "reo_dest_ring_0_handle",
[CNSS_HOST_DP_REO_DST_1] = "reo_dest_ring_1",
[CNSS_HOST_DP_REO_DST_1_HANDLE] = "reo_dest_ring_1_handle",
[CNSS_HOST_DP_REO_DST_2] = "reo_dest_ring_2",
[CNSS_HOST_DP_REO_DST_2_HANDLE] = "reo_dest_ring_2_handle",
[CNSS_HOST_DP_REO_DST_3] = "reo_dest_ring_3",
[CNSS_HOST_DP_REO_DST_3_HANDLE] = "reo_dest_ring_3_handle",
[CNSS_HOST_DP_REO_DST_4] = "reo_dest_ring_4",
[CNSS_HOST_DP_REO_DST_4_HANDLE] = "reo_dest_ring_4_handle",
[CNSS_HOST_DP_REO_DST_5] = "reo_dest_ring_5",
[CNSS_HOST_DP_REO_DST_5_HANDLE] = "reo_dest_ring_5_handle",
[CNSS_HOST_DP_REO_DST_6] = "reo_dest_ring_6",
[CNSS_HOST_DP_REO_DST_6_HANDLE] = "reo_dest_ring_6_handle",
[CNSS_HOST_DP_REO_DST_7] = "reo_dest_ring_7",
[CNSS_HOST_DP_REO_DST_7_HANDLE] = "reo_dest_ring_7_handle",
[CNSS_HOST_DP_PDEV_0] = "dp_pdev_0",
[CNSS_HOST_DP_WLAN_CFG_CTX] = "wlan_cfg_ctx",
[CNSS_HOST_DP_SOC] = "dp_soc",
[CNSS_HOST_HAL_RX_FST] = "hal_rx_fst",
[CNSS_HOST_DP_FISA] = "dp_fisa",
[CNSS_HOST_DP_FISA_HW_FSE_TABLE] = "dp_fisa_hw_fse_table",
[CNSS_HOST_DP_FISA_SW_FSE_TABLE] = "dp_fisa_sw_fse_table",
[CNSS_HOST_HIF] = "hif",
[CNSS_HOST_QDF_NBUF_HIST] = "qdf_nbuf_history",
[CNSS_HOST_TCL_WBM_MAP] = "tcl_wbm_map_array",
[CNSS_HOST_RX_MAC_BUF_RING_0] = "rx_mac_buf_ring_0",
[CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE] = "rx_mac_buf_ring_0_handle",
[CNSS_HOST_RX_MAC_BUF_RING_1] = "rx_mac_buf_ring_1",
[CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE] = "rx_mac_buf_ring_1_handle",
[CNSS_HOST_RX_REFILL_0] = "rx_refill_buf_ring_0",
[CNSS_HOST_RX_REFILL_0_HANDLE] = "rx_refill_buf_ring_0_handle",
[CNSS_HOST_CE_0] = "ce_0",
[CNSS_HOST_CE_0_SRC_RING] = "ce_0_src_ring",
[CNSS_HOST_CE_0_SRC_RING_CTX] = "ce_0_src_ring_ctx",
[CNSS_HOST_CE_1] = "ce_1",
[CNSS_HOST_CE_1_STATUS_RING] = "ce_1_status_ring",
[CNSS_HOST_CE_1_STATUS_RING_CTX] = "ce_1_status_ring_ctx",
[CNSS_HOST_CE_1_DEST_RING] = "ce_1_dest_ring",
[CNSS_HOST_CE_1_DEST_RING_CTX] = "ce_1_dest_ring_ctx",
[CNSS_HOST_CE_2] = "ce_2",
[CNSS_HOST_CE_2_STATUS_RING] = "ce_2_status_ring",
[CNSS_HOST_CE_2_STATUS_RING_CTX] = "ce_2_status_ring_ctx",
[CNSS_HOST_CE_2_DEST_RING] = "ce_2_dest_ring",
[CNSS_HOST_CE_2_DEST_RING_CTX] = "ce_2_dest_ring_ctx",
[CNSS_HOST_CE_3] = "ce_3",
[CNSS_HOST_CE_3_SRC_RING] = "ce_3_src_ring",
[CNSS_HOST_CE_3_SRC_RING_CTX] = "ce_3_src_ring_ctx",
[CNSS_HOST_CE_4] = "ce_4",
[CNSS_HOST_CE_4_SRC_RING] = "ce_4_src_ring",
[CNSS_HOST_CE_4_SRC_RING_CTX] = "ce_4_src_ring_ctx",
[CNSS_HOST_CE_5] = "ce_5",
[CNSS_HOST_CE_6] = "ce_6",
[CNSS_HOST_CE_7] = "ce_7",
[CNSS_HOST_CE_7_STATUS_RING] = "ce_7_status_ring",
[CNSS_HOST_CE_7_STATUS_RING_CTX] = "ce_7_status_ring_ctx",
[CNSS_HOST_CE_7_DEST_RING] = "ce_7_dest_ring",
[CNSS_HOST_CE_7_DEST_RING_CTX] = "ce_7_dest_ring_ctx",
[CNSS_HOST_CE_8] = "ce_8",
[CNSS_HOST_DP_TCL_DATA_3] = "tcl_data_ring_3",
[CNSS_HOST_DP_TCL_DATA_3_HANDLE] = "tcl_data_ring_3_handle",
[CNSS_HOST_DP_TX_COMP_3] = "tx_comp_ring_3",
[CNSS_HOST_DP_TX_COMP_3_HANDLE] = "tx_comp_ring_3_handle"
}; };
int i; int i;
int ret = 0; int ret = 0;
@@ -3296,6 +3387,14 @@ int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
INIT_LIST_HEAD(&head); INIT_LIST_HEAD(&head);
for (i = 0; i < num_entries_loaded; i++) { for (i = 0; i < num_entries_loaded; i++) {
/* If region name registered by driver is not present in
* wlan_str. type for that entry will not be set, but entry will
* be added. Which will result in entry type being 0. Currently
* entry type 0 is for wlan_logs, which will result in parsing
* issue for wlan_logs as parsing is done based upon type field.
* So initialize type with -1(Invalid) to avoid such issues.
*/
meta_info.entry[i].type = -1;
seg = kcalloc(1, sizeof(*seg), GFP_KERNEL); seg = kcalloc(1, sizeof(*seg), GFP_KERNEL);
if (!seg) { if (!seg) {
cnss_pr_err("Failed to alloc seg entry %d\n", i); cnss_pr_err("Failed to alloc seg entry %d\n", i);
@@ -3307,8 +3406,7 @@ int cnss_do_host_ramdump(struct cnss_plat_data *plat_priv,
seg->size = ssr_entry[i].buffer_size; seg->size = ssr_entry[i].buffer_size;
for (j = 0; j < CNSS_HOST_DUMP_TYPE_MAX; j++) { for (j = 0; j < CNSS_HOST_DUMP_TYPE_MAX; j++) {
if (strncmp(ssr_entry[i].region_name, wlan_str[j], if (strcmp(ssr_entry[i].region_name, wlan_str[j]) == 0) {
strlen(wlan_str[j])) == 0) {
meta_info.entry[i].type = j; meta_info.entry[i].type = j;
} }
} }

2
cnss2/main.h
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@@ -279,7 +279,7 @@ enum cnss_fw_dump_type {
}; };
struct cnss_dump_entry { struct cnss_dump_entry {
u32 type; int type;
u32 entry_start; u32 entry_start;
u32 entry_num; u32 entry_num;
}; };

10
cnss2/pci.c
View File

@@ -5946,12 +5946,18 @@ exit:
#ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP #ifdef CONFIG_CNSS2_SSR_DRIVER_DUMP
void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv) void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv)
{ {
struct cnss_ssr_driver_dump_entry ssr_entry[CNSS_HOST_DUMP_TYPE_MAX] = {0}; struct cnss_ssr_driver_dump_entry *ssr_entry;
struct cnss_plat_data *plat_priv = pci_priv->plat_priv; struct cnss_plat_data *plat_priv = pci_priv->plat_priv;
size_t num_entries_loaded = 0; size_t num_entries_loaded = 0;
int x; int x;
int ret = -1; int ret = -1;
ssr_entry = kmalloc(sizeof(*ssr_entry) * CNSS_HOST_DUMP_TYPE_MAX, GFP_KERNEL);
if (!ssr_entry) {
cnss_pr_err("ssr_entry malloc failed");
return;
}
if (pci_priv->driver_ops && if (pci_priv->driver_ops &&
pci_priv->driver_ops->collect_driver_dump) { pci_priv->driver_ops->collect_driver_dump) {
ret = pci_priv->driver_ops->collect_driver_dump(pci_priv->pci_dev, ret = pci_priv->driver_ops->collect_driver_dump(pci_priv->pci_dev,
@@ -5971,6 +5977,8 @@ void cnss_pci_collect_host_dump_info(struct cnss_pci_data *pci_priv)
} else { } else {
cnss_pr_info("Host SSR elf dump collection feature disabled\n"); cnss_pr_info("Host SSR elf dump collection feature disabled\n");
} }
kfree(ssr_entry);
} }
#endif #endif

139
inc/cnss2.h
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@@ -90,30 +90,121 @@ enum cnss_driver_status {
}; };
enum cnss_host_dump_type { enum cnss_host_dump_type {
CNSS_HOST_WLAN_LOGS, CNSS_HOST_WLAN_LOGS = 0,
CNSS_HOST_HTC_CREDIT, CNSS_HOST_HTC_CREDIT = 1,
CNSS_HOST_WMI_TX_CMP, CNSS_HOST_WMI_TX_CMP = 2,
CNSS_HOST_WMI_COMMAND_LOG, CNSS_HOST_WMI_COMMAND_LOG = 3,
CNSS_HOST_WMI_EVENT_LOG, CNSS_HOST_WMI_EVENT_LOG = 4,
CNSS_HOST_WMI_RX_EVENT, CNSS_HOST_WMI_RX_EVENT = 5,
CNSS_HOST_HAL_SOC, CNSS_HOST_HAL_SOC = 6,
CNSS_HOST_GWLAN_LOGGING, CNSS_HOST_GWLAN_LOGGING = 7,
CNSS_HOST_WMI_DEBUG_LOG_INFO, CNSS_HOST_WMI_DEBUG_LOG_INFO = 8,
CNSS_HOST_HTC_CREDIT_IDX, CNSS_HOST_HTC_CREDIT_IDX = 9,
CNSS_HOST_HTC_CREDIT_LEN, CNSS_HOST_HTC_CREDIT_LEN = 10,
CNSS_HOST_WMI_TX_CMP_IDX, CNSS_HOST_WMI_TX_CMP_IDX = 11,
CNSS_HOST_WMI_COMMAND_LOG_IDX, CNSS_HOST_WMI_COMMAND_LOG_IDX = 12,
CNSS_HOST_WMI_EVENT_LOG_IDX, CNSS_HOST_WMI_EVENT_LOG_IDX = 13,
CNSS_HOST_WMI_RX_EVENT_IDX, CNSS_HOST_WMI_RX_EVENT_IDX = 14,
CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF, CNSS_HOST_HIF_CE_DESC_HISTORY_BUFF = 15,
CNSS_HOST_HANG_EVENT_DATA, CNSS_HOST_HANG_EVENT_DATA = 16,
CNSS_HOST_CE_DESC_HIST, CNSS_HOST_CE_DESC_HIST = 17,
CNSS_HOST_CE_COUNT_MAX, CNSS_HOST_CE_COUNT_MAX = 18,
CNSS_HOST_CE_HISTORY_MAX, CNSS_HOST_CE_HISTORY_MAX = 19,
CNSS_HOST_ONLY_FOR_CRIT_CE, CNSS_HOST_ONLY_FOR_CRIT_CE = 20,
CNSS_HOST_HIF_EVENT_HISTORY, CNSS_HOST_HIF_EVENT_HISTORY = 21,
CNSS_HOST_HIF_EVENT_HIST_MAX, CNSS_HOST_HIF_EVENT_HIST_MAX = 22,
CNSS_HOST_DUMP_TYPE_MAX, CNSS_HOST_DP_WBM_DESC_REL = 23,
CNSS_HOST_DP_WBM_DESC_REL_HANDLE = 24,
CNSS_HOST_DP_TCL_CMD = 25,
CNSS_HOST_DP_TCL_CMD_HANDLE = 26,
CNSS_HOST_DP_TCL_STATUS = 27,
CNSS_HOST_DP_TCL_STATUS_HANDLE = 28,
CNSS_HOST_DP_REO_REINJ = 29,
CNSS_HOST_DP_REO_REINJ_HANDLE = 30,
CNSS_HOST_DP_RX_REL = 31,
CNSS_HOST_DP_RX_REL_HANDLE = 32,
CNSS_HOST_DP_REO_EXP = 33,
CNSS_HOST_DP_REO_EXP_HANDLE = 34,
CNSS_HOST_DP_REO_CMD = 35,
CNSS_HOST_DP_REO_CMD_HANDLE = 36,
CNSS_HOST_DP_REO_STATUS = 37,
CNSS_HOST_DP_REO_STATUS_HANDLE = 38,
CNSS_HOST_DP_TCL_DATA_0 = 39,
CNSS_HOST_DP_TCL_DATA_0_HANDLE = 40,
CNSS_HOST_DP_TX_COMP_0 = 41,
CNSS_HOST_DP_TX_COMP_0_HANDLE = 42,
CNSS_HOST_DP_TCL_DATA_1 = 43,
CNSS_HOST_DP_TCL_DATA_1_HANDLE = 44,
CNSS_HOST_DP_TX_COMP_1 = 45,
CNSS_HOST_DP_TX_COMP_1_HANDLE = 46,
CNSS_HOST_DP_TCL_DATA_2 = 47,
CNSS_HOST_DP_TCL_DATA_2_HANDLE = 48,
CNSS_HOST_DP_TX_COMP_2 = 49,
CNSS_HOST_DP_TX_COMP_2_HANDLE = 50,
CNSS_HOST_DP_REO_DST_0 = 51,
CNSS_HOST_DP_REO_DST_0_HANDLE = 52,
CNSS_HOST_DP_REO_DST_1 = 53,
CNSS_HOST_DP_REO_DST_1_HANDLE = 54,
CNSS_HOST_DP_REO_DST_2 = 55,
CNSS_HOST_DP_REO_DST_2_HANDLE = 56,
CNSS_HOST_DP_REO_DST_3 = 57,
CNSS_HOST_DP_REO_DST_3_HANDLE = 58,
CNSS_HOST_DP_REO_DST_4 = 59,
CNSS_HOST_DP_REO_DST_4_HANDLE = 60,
CNSS_HOST_DP_REO_DST_5 = 61,
CNSS_HOST_DP_REO_DST_5_HANDLE = 62,
CNSS_HOST_DP_REO_DST_6 = 63,
CNSS_HOST_DP_REO_DST_6_HANDLE = 64,
CNSS_HOST_DP_REO_DST_7 = 65,
CNSS_HOST_DP_REO_DST_7_HANDLE = 66,
CNSS_HOST_DP_PDEV_0 = 67,
CNSS_HOST_DP_WLAN_CFG_CTX = 68,
CNSS_HOST_DP_SOC = 69,
CNSS_HOST_HAL_RX_FST = 70,
CNSS_HOST_DP_FISA = 71,
CNSS_HOST_DP_FISA_HW_FSE_TABLE = 72,
CNSS_HOST_DP_FISA_SW_FSE_TABLE = 73,
CNSS_HOST_HIF = 74,
CNSS_HOST_QDF_NBUF_HIST = 75,
CNSS_HOST_TCL_WBM_MAP = 76,
CNSS_HOST_RX_MAC_BUF_RING_0 = 77,
CNSS_HOST_RX_MAC_BUF_RING_0_HANDLE = 78,
CNSS_HOST_RX_MAC_BUF_RING_1 = 79,
CNSS_HOST_RX_MAC_BUF_RING_1_HANDLE = 80,
CNSS_HOST_RX_REFILL_0 = 81,
CNSS_HOST_RX_REFILL_0_HANDLE = 82,
CNSS_HOST_CE_0 = 83,
CNSS_HOST_CE_0_SRC_RING = 84,
CNSS_HOST_CE_0_SRC_RING_CTX = 85,
CNSS_HOST_CE_1 = 86,
CNSS_HOST_CE_1_STATUS_RING = 87,
CNSS_HOST_CE_1_STATUS_RING_CTX = 88,
CNSS_HOST_CE_1_DEST_RING = 89,
CNSS_HOST_CE_1_DEST_RING_CTX = 90,
CNSS_HOST_CE_2 = 91,
CNSS_HOST_CE_2_STATUS_RING = 92,
CNSS_HOST_CE_2_STATUS_RING_CTX = 93,
CNSS_HOST_CE_2_DEST_RING = 94,
CNSS_HOST_CE_2_DEST_RING_CTX = 95,
CNSS_HOST_CE_3 = 96,
CNSS_HOST_CE_3_SRC_RING = 97,
CNSS_HOST_CE_3_SRC_RING_CTX = 98,
CNSS_HOST_CE_4 = 99,
CNSS_HOST_CE_4_SRC_RING = 100,
CNSS_HOST_CE_4_SRC_RING_CTX = 101,
CNSS_HOST_CE_5 = 102,
CNSS_HOST_CE_6 = 103,
CNSS_HOST_CE_7 = 104,
CNSS_HOST_CE_7_STATUS_RING = 105,
CNSS_HOST_CE_7_STATUS_RING_CTX = 106,
CNSS_HOST_CE_7_DEST_RING = 107,
CNSS_HOST_CE_7_DEST_RING_CTX = 108,
CNSS_HOST_CE_8 = 109,
CNSS_HOST_DP_TCL_DATA_3 = 110,
CNSS_HOST_DP_TCL_DATA_3_HANDLE = 111,
CNSS_HOST_DP_TX_COMP_3 = 112,
CNSS_HOST_DP_TX_COMP_3_HANDLE = 113,
CNSS_HOST_DUMP_TYPE_MAX = 114,
}; };
enum cnss_bus_event_type { enum cnss_bus_event_type {