disp: msm: dp: replace dp clock trees with single nodes
The current pll driver models the entire DP clock hierarchy using the clock framework. This creates unnecessary dependency between the dp driver and the clock driver and also limits the flexibility to dp driver when configuring the DP clocks. This change models these clocks as single nodes and provide full control to the dp driver and also minimizes the dependency on the clock driver. Change-Id: Id5221441ea33b576e7c543396a12cbeb7b44d319 Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
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@@ -1,6 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DP_PLL_H
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@@ -56,24 +56,14 @@ struct dp_pll_io {
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struct dp_pll_vco_clk {
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struct clk_hw hw;
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unsigned long rate; /* current vco rate */
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u64 min_rate; /* min vco rate */
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u64 max_rate; /* max vco rate */
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void *priv;
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};
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struct dp_pll {
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/*
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* target pll revision information
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*/
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u32 revision;
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/*
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* Certain plls needs to update the same vco rate after resume in
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* suspend/resume scenario. Cached the vco rate for such plls.
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*/
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unsigned long vco_cached_rate;
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/* target pll revision information */
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u32 revision;
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/* save vco current rate */
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unsigned long vco_rate;
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/*
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* PLL index if multiple index are available. Eg. in case of
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* DSI we have 2 plls.
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@@ -90,6 +80,10 @@ struct dp_pll {
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struct dp_aux *aux;
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struct dp_pll_io io;
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struct clk_onecell_data *clk_data;
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int (*pll_cfg)(struct dp_pll *pll, unsigned long rate);
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int (*pll_prepare)(struct dp_pll *pll);
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int (*pll_unprepare)(struct dp_pll *pll);
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};
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struct dp_pll_db {
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@@ -117,7 +111,6 @@ struct dp_pll_db {
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u32 phy_vco_div;
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};
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static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw)
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{
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return container_of(hw, struct dp_pll_vco_clk, hw);
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