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@@ -5043,13 +5043,21 @@ static int _sde_crtc_vblank_enable(
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static void _sde_crtc_reserve_resource(struct drm_crtc *crtc, struct drm_connector *conn)
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{
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+ struct sde_kms *kms;
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+ struct drm_encoder *encoder;
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u32 min_transfer_time = 0, lm_count = 1;
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u64 mode_clock_hz = 0, updated_fps = 0, topology_id;
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- struct drm_encoder *encoder;
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+ u32 inf_factor = 105, lm_width, num_bubbles = 0;
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if (!crtc || !conn)
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return;
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+ kms = _sde_crtc_get_kms(crtc);
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+ if (!kms || !kms->catalog) {
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+ SDE_ERROR("invalid kms\n");
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+ return;
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+ }
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+
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encoder = conn->state->best_encoder;
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if (!sde_encoder_is_built_in_display(encoder))
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return;
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@@ -5063,17 +5071,31 @@ static void _sde_crtc_reserve_resource(struct drm_crtc *crtc, struct drm_connect
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updated_fps = drm_mode_vrefresh(&crtc->mode);
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topology_id = sde_connector_get_topology_name(conn);
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- if (TOPOLOGY_DUALPIPE_MODE(topology_id))
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+ if (TOPOLOGY_DUALPIPE_MODE(topology_id)) {
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lm_count = 2;
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- else if (TOPOLOGY_QUADPIPE_MODE(topology_id))
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+ if (SDE_HW_MAJOR(kms->catalog->hw_rev) == SDE_HW_MAJOR(SDE_HW_VER_A00))
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+ num_bubbles = 40;
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+ } else if (TOPOLOGY_QUADPIPE_MODE(topology_id)) {
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lm_count = 4;
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+ if (SDE_HW_MAJOR(kms->catalog->hw_rev) == SDE_HW_MAJOR(SDE_HW_VER_A00))
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+ num_bubbles = 56;
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+ }
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+
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+ if (SDE_HW_MAJOR(kms->catalog->hw_rev) == SDE_HW_MAJOR(SDE_HW_VER_900)
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+ && lm_count > 1)
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+ num_bubbles = 30;
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+
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+ lm_width = (crtc->mode.hdisplay) / lm_count;
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+ num_bubbles = mult_frac(num_bubbles, 100, lm_width);
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+ inf_factor = max((100 + num_bubbles), inf_factor);
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/* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
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- mode_clock_hz = mult_frac(crtc->mode.htotal * crtc->mode.vtotal * updated_fps, 105, 100);
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+ mode_clock_hz = mult_frac(crtc->mode.htotal * crtc->mode.vtotal * updated_fps,
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+ inf_factor, 100);
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mode_clock_hz = div_u64(mode_clock_hz, lm_count);
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- SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u\n",
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+ SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%u inf_factor=%u\n",
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crtc->mode.name, crtc->mode.htotal, crtc->mode.vtotal,
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- updated_fps, lm_count, mode_clock_hz);
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+ updated_fps, lm_count, mode_clock_hz, inf_factor);
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sde_core_perf_crtc_reserve_res(crtc, mode_clock_hz);
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}
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