disp: msm: sde: rename MDSS_INTR_* enums to SDE_INTR_*

Rename sde_intr_enum members to prefix with SDE instead of
the old MDSS naming used in legacy display driver.

Change-Id: I21bc67b4a79b7e53af0ac1beaebb6e9482015b0f
Signed-off-by: Steve Cohen <[email protected]>

msm/sde/sde_hw_catalog.c

@@ -4056,14 +4056,14 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 
 	/* default settings for *MOST* targets */
 	sde_cfg->has_mixer_combined_alpha = true;
-	for (i = 0; i < MDSS_INTR_MAX; i++)
+	for (i = 0; i < SDE_INTR_MAX; i++)
 		set_bit(i, sde_cfg->mdss_irqs);
 
 	/* target specific settings */
 	if (IS_MSM8996_TARGET(hw_rev)) {
 		sde_cfg->perf.min_prefill_lines = 21;
-		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_decimation = true;
 		sde_cfg->has_mixer_combined_alpha = false;
 	} else if (IS_MSM8998_TARGET(hw_rev)) {
@@ -4071,8 +4071,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->perf.min_prefill_lines = 25;
 		sde_cfg->vbif_qos_nlvl = 4;
 		sde_cfg->ts_prefill_rev = 1;
-		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_decimation = true;
 		sde_cfg->has_cursor = true;
 		sde_cfg->has_hdr = true;
@@ -4085,8 +4085,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->sui_misr_supported = true;
 		sde_cfg->sui_block_xin_mask = 0x3F71;
-		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_decimation = true;
 		sde_cfg->has_hdr = true;
 		sde_cfg->has_vig_p010 = true;
@@ -4095,8 +4095,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->perf.min_prefill_lines = 24;
 		sde_cfg->vbif_qos_nlvl = 8;
 		sde_cfg->ts_prefill_rev = 2;
-		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_decimation = true;
 		sde_cfg->has_hdr = true;
 		sde_cfg->has_vig_p010 = true;
@@ -4119,8 +4119,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->has_sui_blendstage = true;
 		sde_cfg->has_qos_fl_nocalc = true;
 		sde_cfg->has_3d_merge_reset = true;
-		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_decimation = true;
 		sde_cfg->has_intf_te = true;
 		sde_cfg->vbif_disable_inner_outer_shareable = true;
@@ -4131,8 +4131,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->ts_prefill_rev = 2;
 		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
 		sde_cfg->delay_prg_fetch_start = true;
-		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_decimation = true;
 		sde_cfg->has_hdr = true;
 		sde_cfg->has_vig_p010 = true;
@@ -4152,8 +4152,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->has_sui_blendstage = true;
 		sde_cfg->has_qos_fl_nocalc = true;
 		sde_cfg->has_3d_merge_reset = true;
-		clear_bit(MDSS_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_LTM_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_hdr = true;
 		sde_cfg->has_vig_p010 = true;
 		sde_cfg->has_intf_te = true;
@@ -4190,8 +4190,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->has_sui_blendstage = true;
 		sde_cfg->has_qos_fl_nocalc = true;
 		sde_cfg->has_3d_merge_reset = true;
-		clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_hdr = true;
 		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
@@ -4224,8 +4224,8 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
 		sde_cfg->has_sui_blendstage = true;
 		sde_cfg->has_qos_fl_nocalc = true;
 		sde_cfg->has_3d_merge_reset = true;
-		clear_bit(MDSS_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);
-		clear_bit(MDSS_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_AD4_0_INTR, sde_cfg->mdss_irqs);
+		clear_bit(SDE_INTR_AD4_1_INTR, sde_cfg->mdss_irqs);
 		sde_cfg->has_hdr = true;
 		sde_cfg->has_hdr_plus = true;
 		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);

msm/sde/sde_hw_catalog.h

@@ -141,21 +141,21 @@ enum {
  * by 'sde_irq_map'
  */
 enum sde_intr_enum {
-	MDSS_INTR_SSPP_TOP0_INTR,
-	MDSS_INTR_SSPP_TOP0_INTR2,
-	MDSS_INTF_TEAR_1_INTR,
-	MDSS_INTF_TEAR_2_INTR,
-	MDSS_INTR_SSPP_TOP0_HIST_INTR,
-	MDSS_INTR_INTF_0_INTR,
-	MDSS_INTR_INTF_1_INTR,
-	MDSS_INTR_INTF_2_INTR,
-	MDSS_INTR_INTF_3_INTR,
-	MDSS_INTR_INTF_4_INTR,
-	MDSS_INTR_AD4_0_INTR,
-	MDSS_INTR_AD4_1_INTR,
-	MDSS_INTR_LTM_0_INTR,
-	MDSS_INTR_LTM_1_INTR,
-	MDSS_INTR_MAX
+	SDE_INTR_SSPP_TOP0_INTR,
+	SDE_INTR_SSPP_TOP0_INTR2,
+	SDE_INTF_TEAR_1_INTR,
+	SDE_INTF_TEAR_2_INTR,
+	SDE_INTR_SSPP_TOP0_HIST_INTR,
+	SDE_INTR_INTF_0_INTR,
+	SDE_INTR_INTF_1_INTR,
+	SDE_INTR_INTF_2_INTR,
+	SDE_INTR_INTF_3_INTR,
+	SDE_INTR_INTF_4_INTR,
+	SDE_INTR_AD4_0_INTR,
+	SDE_INTR_AD4_1_INTR,
+	SDE_INTR_LTM_0_INTR,
+	SDE_INTR_LTM_1_INTR,
+	SDE_INTR_MAX
 };
 
 /**
@@ -1429,7 +1429,7 @@ struct sde_mdss_cfg {
 	struct sde_format_extended *virt_vig_formats;
 	struct sde_format_extended *inline_rot_formats;
 
-	DECLARE_BITMAP(mdss_irqs, MDSS_INTR_MAX);
+	DECLARE_BITMAP(mdss_irqs, SDE_INTR_MAX);
 };
 
 struct sde_mdss_hw_cfg_handler {

msm/sde/sde_hw_interrupts.c

@@ -1060,7 +1060,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 		sde_irq = &sde_irq_tbl[idx];
 
 		switch (sde_irq->sde_irq_idx) {
-		case MDSS_INTR_SSPP_TOP0_INTR:
+		case SDE_INTR_SSPP_TOP0_INTR:
 			sde_irq->clr_off =
 				MDP_SSPP_TOP0_OFF+INTR_CLEAR;
 			sde_irq->en_off =
@@ -1068,7 +1068,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_SSPP_TOP0_OFF+INTR_STATUS;
 			break;
-		case MDSS_INTR_SSPP_TOP0_INTR2:
+		case SDE_INTR_SSPP_TOP0_INTR2:
 			sde_irq->clr_off =
 				MDP_SSPP_TOP0_OFF+INTR2_CLEAR;
 			sde_irq->en_off =
@@ -1076,7 +1076,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_SSPP_TOP0_OFF+INTR2_STATUS;
 			break;
-		case MDSS_INTR_SSPP_TOP0_HIST_INTR:
+		case SDE_INTR_SSPP_TOP0_HIST_INTR:
 			sde_irq->clr_off =
 				MDP_SSPP_TOP0_OFF+HIST_INTR_CLEAR;
 			sde_irq->en_off =
@@ -1084,7 +1084,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_SSPP_TOP0_OFF+HIST_INTR_STATUS;
 			break;
-		case MDSS_INTR_INTF_0_INTR:
+		case SDE_INTR_INTF_0_INTR:
 			sde_irq->clr_off =
 				MDP_INTF_0_OFF+INTF_INTR_CLEAR;
 			sde_irq->en_off =
@@ -1092,7 +1092,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_INTF_0_OFF+INTF_INTR_STATUS;
 			break;
-		case MDSS_INTR_INTF_1_INTR:
+		case SDE_INTR_INTF_1_INTR:
 			sde_irq->clr_off =
 				MDP_INTF_1_OFF+INTF_INTR_CLEAR;
 			sde_irq->en_off =
@@ -1100,7 +1100,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_INTF_1_OFF+INTF_INTR_STATUS;
 			break;
-		case MDSS_INTR_INTF_2_INTR:
+		case SDE_INTR_INTF_2_INTR:
 			sde_irq->clr_off =
 				MDP_INTF_2_OFF+INTF_INTR_CLEAR;
 			sde_irq->en_off =
@@ -1108,7 +1108,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_INTF_2_OFF+INTF_INTR_STATUS;
 			break;
-		case MDSS_INTR_INTF_3_INTR:
+		case SDE_INTR_INTF_3_INTR:
 			sde_irq->clr_off =
 				MDP_INTF_3_OFF+INTF_INTR_CLEAR;
 			sde_irq->en_off =
@@ -1116,7 +1116,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_INTF_3_OFF+INTF_INTR_STATUS;
 			break;
-		case MDSS_INTR_INTF_4_INTR:
+		case SDE_INTR_INTF_4_INTR:
 			sde_irq->clr_off =
 				MDP_INTF_4_OFF+INTF_INTR_CLEAR;
 			sde_irq->en_off =
@@ -1124,7 +1124,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_INTF_4_OFF+INTF_INTR_STATUS;
 			break;
-		case MDSS_INTR_AD4_0_INTR:
+		case SDE_INTR_AD4_0_INTR:
 			sde_irq->clr_off =
 				MDP_AD4_0_OFF + MDP_AD4_INTR_CLEAR_OFF;
 			sde_irq->en_off =
@@ -1132,7 +1132,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_AD4_0_OFF + MDP_AD4_INTR_STATUS_OFF;
 			break;
-		case MDSS_INTR_AD4_1_INTR:
+		case SDE_INTR_AD4_1_INTR:
 			sde_irq->clr_off =
 				MDP_AD4_1_OFF + MDP_AD4_INTR_CLEAR_OFF;
 			sde_irq->en_off =
@@ -1140,7 +1140,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_AD4_1_OFF + MDP_AD4_INTR_STATUS_OFF;
 			break;
-		case MDSS_INTF_TEAR_1_INTR:
+		case SDE_INTF_TEAR_1_INTR:
 			sde_irq->clr_off = MDP_INTF_TEAR_INTF_1_IRQ_OFF +
 				MDP_INTF_TEAR_INTR_CLEAR_OFF;
 			sde_irq->en_off =
@@ -1149,7 +1149,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off = MDP_INTF_TEAR_INTF_1_IRQ_OFF +
 				MDP_INTF_TEAR_INTR_STATUS_OFF;
 			break;
-		case MDSS_INTF_TEAR_2_INTR:
+		case SDE_INTF_TEAR_2_INTR:
 			sde_irq->clr_off = MDP_INTF_TEAR_INTF_2_IRQ_OFF +
 				MDP_INTF_TEAR_INTR_CLEAR_OFF;
 			sde_irq->en_off = MDP_INTF_TEAR_INTF_2_IRQ_OFF +
@@ -1157,7 +1157,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off = MDP_INTF_TEAR_INTF_2_IRQ_OFF +
 				MDP_INTF_TEAR_INTR_STATUS_OFF;
 			break;
-		case MDSS_INTR_LTM_0_INTR:
+		case SDE_INTR_LTM_0_INTR:
 			sde_irq->clr_off =
 				MDP_LTM_0_OFF + MDP_LTM_INTR_CLEAR_OFF;
 			sde_irq->en_off =
@@ -1165,7 +1165,7 @@ static inline int _sde_hw_intr_init_sde_irq_tbl(u32 irq_tbl_size,
 			sde_irq->status_off =
 				MDP_LTM_0_OFF + MDP_LTM_INTR_STATUS_OFF;
 			break;
-		case MDSS_INTR_LTM_1_INTR:
+		case SDE_INTR_LTM_1_INTR:
 			sde_irq->clr_off =
 				MDP_LTM_1_OFF + MDP_LTM_INTR_CLEAR_OFF;
 			sde_irq->en_off =
@@ -1203,46 +1203,46 @@ static inline u32 _get_irq_map_size(int idx)
 	u32 ret = 0;
 
 	switch (idx) {
-	case MDSS_INTR_SSPP_TOP0_INTR:
+	case SDE_INTR_SSPP_TOP0_INTR:
 		ret = ARRAY_SIZE(sde_irq_intr_map);
 		break;
-	case MDSS_INTR_SSPP_TOP0_INTR2:
+	case SDE_INTR_SSPP_TOP0_INTR2:
 		ret = ARRAY_SIZE(sde_irq_intr2_map);
 		break;
-	case MDSS_INTR_SSPP_TOP0_HIST_INTR:
+	case SDE_INTR_SSPP_TOP0_HIST_INTR:
 		ret = ARRAY_SIZE(sde_irq_hist_map);
 		break;
-	case MDSS_INTR_INTF_0_INTR:
+	case SDE_INTR_INTF_0_INTR:
 		ret = ARRAY_SIZE(sde_irq_intf0_map);
 		break;
-	case MDSS_INTR_INTF_1_INTR:
+	case SDE_INTR_INTF_1_INTR:
 		ret = ARRAY_SIZE(sde_irq_inf1_map);
 		break;
-	case MDSS_INTR_INTF_2_INTR:
+	case SDE_INTR_INTF_2_INTR:
 		ret = ARRAY_SIZE(sde_irq_intf2_map);
 		break;
-	case MDSS_INTR_INTF_3_INTR:
+	case SDE_INTR_INTF_3_INTR:
 		ret = ARRAY_SIZE(sde_irq_intf3_map);
 		break;
-	case MDSS_INTR_INTF_4_INTR:
+	case SDE_INTR_INTF_4_INTR:
 		ret = ARRAY_SIZE(sde_irq_inf4_map);
 		break;
-	case MDSS_INTR_AD4_0_INTR:
+	case SDE_INTR_AD4_0_INTR:
 		ret = ARRAY_SIZE(sde_irq_ad4_0_map);
 		break;
-	case MDSS_INTR_AD4_1_INTR:
+	case SDE_INTR_AD4_1_INTR:
 		ret = ARRAY_SIZE(sde_irq_ad4_1_map);
 		break;
-	case MDSS_INTF_TEAR_1_INTR:
+	case SDE_INTF_TEAR_1_INTR:
 		ret = ARRAY_SIZE(sde_irq_intf1_te_map);
 		break;
-	case MDSS_INTF_TEAR_2_INTR:
+	case SDE_INTF_TEAR_2_INTR:
 		ret = ARRAY_SIZE(sde_irq_intf2_te_map);
 		break;
-	case MDSS_INTR_LTM_0_INTR:
+	case SDE_INTR_LTM_0_INTR:
 		ret = ARRAY_SIZE(sde_irq_ltm_0_map);
 		break;
-	case MDSS_INTR_LTM_1_INTR:
+	case SDE_INTR_LTM_1_INTR:
 		ret = ARRAY_SIZE(sde_irq_ltm_1_map);
 		break;
 	default:
@@ -1257,46 +1257,46 @@ static inline struct sde_irq_type *_get_irq_map_addr(int idx)
 	struct sde_irq_type *ret = NULL;
 
 	switch (idx) {
-	case MDSS_INTR_SSPP_TOP0_INTR:
+	case SDE_INTR_SSPP_TOP0_INTR:
 		ret = sde_irq_intr_map;
 		break;
-	case MDSS_INTR_SSPP_TOP0_INTR2:
+	case SDE_INTR_SSPP_TOP0_INTR2:
 		ret = sde_irq_intr2_map;
 		break;
-	case MDSS_INTR_SSPP_TOP0_HIST_INTR:
+	case SDE_INTR_SSPP_TOP0_HIST_INTR:
 		ret = sde_irq_hist_map;
 		break;
-	case MDSS_INTR_INTF_0_INTR:
+	case SDE_INTR_INTF_0_INTR:
 		ret = sde_irq_intf0_map;
 		break;
-	case MDSS_INTR_INTF_1_INTR:
+	case SDE_INTR_INTF_1_INTR:
 		ret = sde_irq_inf1_map;
 		break;
-	case MDSS_INTR_INTF_2_INTR:
+	case SDE_INTR_INTF_2_INTR:
 		ret = sde_irq_intf2_map;
 		break;
-	case MDSS_INTR_INTF_3_INTR:
+	case SDE_INTR_INTF_3_INTR:
 		ret = sde_irq_intf3_map;
 		break;
-	case MDSS_INTR_INTF_4_INTR:
+	case SDE_INTR_INTF_4_INTR:
 		ret = sde_irq_inf4_map;
 		break;
-	case MDSS_INTR_AD4_0_INTR:
+	case SDE_INTR_AD4_0_INTR:
 		ret = sde_irq_ad4_0_map;
 		break;
-	case MDSS_INTR_AD4_1_INTR:
+	case SDE_INTR_AD4_1_INTR:
 		ret = sde_irq_ad4_1_map;
 		break;
-	case MDSS_INTF_TEAR_1_INTR:
+	case SDE_INTF_TEAR_1_INTR:
 		ret = sde_irq_intf1_te_map;
 		break;
-	case MDSS_INTF_TEAR_2_INTR:
+	case SDE_INTF_TEAR_2_INTR:
 		ret = sde_irq_intf2_te_map;
 		break;
-	case MDSS_INTR_LTM_0_INTR:
+	case SDE_INTR_LTM_0_INTR:
 		ret = sde_irq_ltm_0_map;
 		break;
-	case MDSS_INTR_LTM_1_INTR:
+	case SDE_INTR_LTM_1_INTR:
 		ret = sde_irq_ltm_1_map;
 		break;
 	default:
@@ -1337,7 +1337,7 @@ static int _sde_hw_intr_init_irq_tables(struct sde_hw_intr *intr,
 	u32 sde_irq_map_idx = 0;
 
 	/* Initialize the offset of the irq's in the sde_irq_map table */
-	for (idx = 0; idx < MDSS_INTR_MAX; idx++) {
+	for (idx = 0; idx < SDE_INTR_MAX; idx++) {
 		if (test_bit(idx, m->mdss_irqs)) {
 			low_idx = sde_irq_map_idx;
 			high_idx = low_idx + _get_irq_map_size(idx);
@@ -1419,14 +1419,14 @@ struct sde_hw_intr *sde_hw_intr_init(void __iomem *addr,
 	}
 	__setup_intr_ops(&intr->ops);
 
-	if (MDSS_INTR_MAX >= UINT_MAX) {
-		pr_err("max intr exceeded:%d\n", MDSS_INTR_MAX);
+	if (SDE_INTR_MAX >= UINT_MAX) {
+		pr_err("max intr exceeded:%d\n", SDE_INTR_MAX);
 		ret  = -EINVAL;
 		goto exit;
 	}
 
 	/* check how many irq's this target supports */
-	for (idx = 0; idx < MDSS_INTR_MAX; idx++) {
+	for (idx = 0; idx < SDE_INTR_MAX; idx++) {
 		if (test_bit(idx, m->mdss_irqs)) {
 			irq_regs_count++;
 
@@ -1442,7 +1442,7 @@ struct sde_hw_intr *sde_hw_intr_init(void __iomem *addr,
 		}
 	}
 
-	if (irq_regs_count == 0 || irq_regs_count > MDSS_INTR_MAX ||
+	if (irq_regs_count == 0 || irq_regs_count > SDE_INTR_MAX ||
 		irq_map_count == 0) {
 		pr_err("wrong mapping of supported irqs 0x%lx\n",
 			m->mdss_irqs[0]);