Merge 3737f300d4a163391a6acfdb398155a64723bff8 on remote branch

Change-Id: Icefbfd8d77e05ce2f3376fc271012ebd3e9b4a6a

asoc/codecs/audio-ext-clk-up.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/kernel.h>
@@ -38,6 +38,9 @@ enum {
 	AUDIO_EXT_CLK_LPASS11,
 	AUDIO_EXT_CLK_LPASS12,
 	AUDIO_EXT_CLK_LPASS13,
+	AUDIO_EXT_CLK_LPASS14,
+	AUDIO_EXT_CLK_LPASS15,
+	AUDIO_EXT_CLK_LPASS16,
 	AUDIO_EXT_CLK_LPASS_MAX,
 	AUDIO_EXT_CLK_EXTERNAL_PLL = AUDIO_EXT_CLK_LPASS_MAX,
 	AUDIO_EXT_CLK_MAX,
@@ -473,6 +476,39 @@ static struct audio_ext_clk audio_clk_array[] = {
 			},
 		},
 	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk14",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk15",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
+	{
+		.pnctrl_info = {NULL},
+		.fact = {
+			.mult = 1,
+			.div = 1,
+			.hw.init = &(struct clk_init_data){
+				.name = "audio_lpass_mclk16",
+				.ops = &audio_ext_clk_ops,
+			},
+		},
+	},
 	{
 		.pnctrl_info = {NULL},
 		.fact = {

asoc/codecs/msm_stub.c

@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /* Copyright (c) 2011-2014, 2017-2019 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/platform_device.h>
@@ -20,8 +20,8 @@ static struct snd_soc_dai_driver msm_stub_dais[] = {
 		.playback = { /* Support maximum range */
 			.stream_name = "Playback",
 			.channels_min = 1,
-			.channels_max = 8,
-			.rates = SNDRV_PCM_RATE_8000_48000,
+			.channels_max = 32,
+			.rates = SNDRV_PCM_RATE_8000_96000,
 			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
 				    SNDRV_PCM_FMTBIT_S24_LE |
 				    SNDRV_PCM_FMTBIT_S24_3LE |
@@ -33,8 +33,8 @@ static struct snd_soc_dai_driver msm_stub_dais[] = {
 		.capture = { /* Support maximum range */
 			.stream_name = "Record",
 			.channels_min = 1,
-			.channels_max = 8,
-			.rates = SNDRV_PCM_RATE_8000_48000,
+			.channels_max = 32,
+			.rates = SNDRV_PCM_RATE_8000_96000,
 			.formats = (SNDRV_PCM_FMTBIT_S16_LE |
 				    SNDRV_PCM_FMTBIT_S24_LE |
 				    SNDRV_PCM_FMTBIT_S24_3LE |

asoc/codecs/wcd9378/wcd9378.c

@@ -1275,7 +1275,7 @@ static int wcd9378_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
 		break;
 	case SND_SOC_DAPM_POST_PMD:
 		wcd9378_micbias_control(component, tx_num,
-				MICB_PULLUP_ENABLE, true);
+				MICB_PULLUP_DISABLE, true);
 		break;
 	};
 
@@ -1408,7 +1408,6 @@ static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
 	struct snd_soc_component *component =
 			snd_soc_dapm_to_component(w->dapm);
 	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
-	int ret;
 	int bank = 0;
 	int act_ps = 0;
 
@@ -1424,13 +1423,7 @@ static int wcd9378_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
 			wcd9378->update_wcd_event(wcd9378->handle,
 						SLV_BOLERO_EVT_RX_MUTE,
 						(WCD_RX1 << 0x10 | 0x01));
-		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
-
-		ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
-					wcd9378->rx_swr_dev->dev_num,
-					true);
 
-		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
 		if (wcd9378->update_wcd_event)
 			wcd9378->update_wcd_event(wcd9378->handle,
 						SLV_BOLERO_EVT_RX_MUTE,
@@ -1473,7 +1466,6 @@ static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
 	struct snd_soc_component *component =
 			snd_soc_dapm_to_component(w->dapm);
 	struct wcd9378_priv *wcd9378 = snd_soc_component_get_drvdata(component);
-	int ret;
 	int act_ps = 0;
 
 	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
@@ -1485,9 +1477,7 @@ static int wcd9378_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
 			wcd9378->update_wcd_event(wcd9378->handle,
 						SLV_BOLERO_EVT_RX_MUTE,
 						(WCD_RX2 << 0x10 | 0x1));
-		ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
-				    wcd9378->rx_swr_dev->dev_num,
-				    true);
+
 		if (wcd9378->update_wcd_event)
 			wcd9378->update_wcd_event(wcd9378->handle,
 						SLV_BOLERO_EVT_RX_MUTE,
@@ -1760,7 +1750,8 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
 				snd_soc_dapm_to_component(w->dapm);
 	struct wcd9378_priv *wcd9378 =
 				snd_soc_component_get_drvdata(component);
-	int power_level;
+	int power_level, bank = 0;
+	int ret = 0;
 	struct swr_device *swr_dev = wcd9378->tx_swr_dev;
 	u8 scp_commit_val = 0x2;
 
@@ -1814,6 +1805,14 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
 				WCD9378_FU42_MUTE_CH2_FU42_MUTE_CH2_MASK, 0x00);
 
 		swr_write(swr_dev, swr_dev->dev_num, 0x004c, &scp_commit_val);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, bank, RX_PATH, true);
+
+		ret = swr_slvdev_datapath_control(wcd9378->rx_swr_dev,
+					wcd9378->rx_swr_dev->dev_num,
+					true);
+
+		wcd9378_swr_slave_clk_set(wcd9378->dev, !bank, RX_PATH, true);
 		break;
 	case SND_SOC_DAPM_POST_PMD:
 		/*RX0 mute*/
@@ -1838,7 +1837,7 @@ static int wcd9378_hph_sequencer_enable(struct snd_soc_dapm_widget *w,
 		break;
 	};
 
-	return 0;
+	return ret;
 }
 
 static int wcd9378_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
@@ -1950,7 +1949,7 @@ static int wcd9378_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
 		} else {
 			snd_soc_component_update_bits(component, WCD9378_CDC_AUX_GAIN_CTL,
 					WCD9378_CDC_AUX_GAIN_CTL_AUX_EN_MASK, 0x00);
-			wcd9378_rx_connect_port(component, LO, true);
+			wcd9378_rx_connect_port(component, LO, false);
 		}
 		break;
 	};
@@ -2072,12 +2071,6 @@ int wcd9378_micbias_control(struct snd_soc_component *component,
 	micb_index = micb_num - 1;
 	switch (req) {
 	case MICB_PULLUP_ENABLE:
-		if (!wcd9378->dev_up) {
-			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
-				__func__, req);
-			ret = -ENODEV;
-			goto done;
-		}
 		wcd9378->pullup_ref[micb_index]++;
 		if ((wcd9378->pullup_ref[micb_index] == 1) &&
 			(wcd9378->micb_ref[micb_index] == 0)) {
@@ -2090,12 +2083,7 @@ int wcd9378_micbias_control(struct snd_soc_component *component,
 	case MICB_PULLUP_DISABLE:
 		if (wcd9378->pullup_ref[micb_index] > 0)
 			wcd9378->pullup_ref[micb_index]--;
-		if (!wcd9378->dev_up) {
-			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
-				__func__, req);
-			ret = -ENODEV;
-			goto done;
-		}
+
 		if ((wcd9378->pullup_ref[micb_index] == 0) &&
 			    (wcd9378->micb_ref[micb_index] == 0))
 			snd_soc_component_update_bits(component, micb_usage, micb_mask, 0x01);
@@ -2130,12 +2118,6 @@ int wcd9378_micbias_control(struct snd_soc_component *component,
 	case MICB_DISABLE:
 		if (wcd9378->micb_ref[micb_index] > 0)
 			wcd9378->micb_ref[micb_index]--;
-		if (!wcd9378->dev_up) {
-			dev_dbg(component->dev, "%s: enable req %d wcd device down\n",
-				__func__, req);
-			ret = -ENODEV;
-			goto done;
-		}
 		if ((wcd9378->micb_ref[micb_index] == 0) &&
 			(wcd9378->pullup_ref[micb_index] > 0)) {
 			/*PULL UP?*/
@@ -2297,6 +2279,11 @@ static int wcd9378_event_notify(struct notifier_block *block,
 		wcd9378_get_logical_addr(wcd9378->tx_swr_dev);
 		wcd9378_get_logical_addr(wcd9378->rx_swr_dev);
 
+		wcd9378->tx_swr_dev->scp1_val = 0;
+		wcd9378->tx_swr_dev->scp2_val = 0;
+		wcd9378->rx_swr_dev->scp1_val = 0;
+		wcd9378->rx_swr_dev->scp2_val = 0;
+
 		wcd9378_init_reg(component);
 		regcache_mark_dirty(wcd9378->regmap);
 		regcache_sync(wcd9378->regmap);
@@ -4033,7 +4020,7 @@ static int wcd9378_reset(struct device *dev)
 	if (rc) {
 		dev_err(dev, "%s: wcd sleep state request fail!\n",
 				__func__);
-		return rc;
+		return -EPROBE_DEFER;
 	}
 	/* 20us sleep required after pulling the reset gpio to LOW */
 	usleep_range(20, 30);
@@ -4042,7 +4029,7 @@ static int wcd9378_reset(struct device *dev)
 	if (rc) {
 		dev_err(dev, "%s: wcd active state request fail!\n",
 				__func__);
-		return rc;
+		return -EPROBE_DEFER;
 	}
 	/* 20us sleep required after pulling the reset gpio to HIGH */
 	usleep_range(20, 30);
@@ -4442,7 +4429,11 @@ static int wcd9378_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_lock_init;
 
-	wcd9378_reset(dev);
+	ret = wcd9378_reset(dev);
+	if (ret == -EPROBE_DEFER) {
+		dev_err(dev, "%s: wcd reset failed!\n", __func__);
+		goto err_lock_init;
+	}
 
 	wcd9378->wakeup = wcd9378_wakeup;
 

asoc/codecs/wcd937x/wcd937x.c

@@ -1832,6 +1832,11 @@ static int wcd937x_event_notify(struct notifier_block *block,
 		}
 		wcd937x->mbhc->wcd_mbhc.deinit_in_progress = false;
 		break;
+	case BOLERO_SLV_EVT_CLK_NOTIFY:
+		snd_soc_component_update_bits(component,
+			WCD937X_DIGITAL_TOP_CLK_CFG, 0x06,
+				((val >> 0x10) << 0x01));
+		break;
 	default:
 		dev_err(component->dev, "%s: invalid event %d\n", __func__,
 			event);

asoc/pineapple-port-config.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _PINEAPPLE_PORT_CONFIG
@@ -16,6 +16,58 @@
  *  stream_type}
  */
 
+#ifdef CONFIG_SWRM_VER_1P7
+static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
+	{7,    1,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
+	{31,   3,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
+	{63,   5,    31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
+	{7,    2,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
+	{31,   4,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
+	{63,   21,   31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
+	{15,   6,    0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
+	{15,   13,   0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
+};
+
+static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
+	{3,    1,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
+	{31,   3,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
+	{63,   5,    31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB1 */
+	{3,    2,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR2 */
+	{31,   4,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP2 */
+	{63,   21,   31,   0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* SB2 */
+	{15,   6,    0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS1 */
+	{15,   13,   0xFF, 0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x01, 0x00}, /* IVS2 */
+};
+
+static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
+	{3,     0,    0,    0xFF, 0xFF, 1,    0xFF, 0xFF, 1,    0x00, 0x00}, /* HPH/EAR */
+	{63,    0,    0,    3,    6,    7,    0,    0xFF, 0,    0x00, 0x02}, /* HPH_CLH */
+	{31,    11,   11,   0xFF, 0xFF, 4,    1,    0xFF, 0,    0x00, 0x02}, /* HPH_CMP */
+	{7,     9,    0,    0xFF, 0xFF, 0xFF, 0xFF, 1,    0,    0x00, 0x00}, /* LO/AUX */
+	{3,     1,    0,    0xFF, 0xFF, 0xFF, 0xFF, 3,    0,    0x00, 0x00}, /* DSD */
+};
+
+/* Headset + PCM Haptics */
+static struct port_params rx_frame_params_default[SWR_MSTR_PORT_LEN] = {
+	{3,     0,    0,    0xFF, 0xFF, 1,    0xFF, 0xFF, 1,    0x00, 0x00}, /* HPH/EAR */
+	{63,    0,    0,    3,    6,    7,    0,    0xFF, 0,    0x00, 0x02}, /* HPH_CLH */
+	{31,    11,   11,   0xFF, 0xFF, 4,    1,    0xFF, 0,    0x00, 0x02}, /* HPH_CMP */
+	{7,     1,    0,    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0,    0x00, 0x00}, /* LO/AUX */
+	{0,     0,    0,    0xFF, 0xFF, 0xFF, 0xFF, 0,    0,    0x00, 0x00}, /* DSD */
+	{0x18F, 0,    0,    0x8,  0x8,  0x0F, 0x00, 0,    0,    0x00, 0x01}, /* PCM_OUT */
+};
+
+/* Headset(44.1K) + PCM Haptics */
+static struct port_params rx_frame_params_44p1KHz[SWR_MSTR_PORT_LEN] = {
+	{3,     0,    0,    0xFF, 0xFF, 1,    0xFF, 0xFF, 1,    0x00, 0x00}, /* HPH/EAR */
+	{63,    0,    0,    3,    6,    7,    0,    0xFF, 0,    0x00, 0x02}, /* HPH_CLH */
+	{31,    11,   11,   0xFF, 0xFF, 4,    1,    0xFF, 0,    0x00, 0x02}, /* HPH_CMP */
+	{3,     1,    0,    0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0,    0x00, 0x00}, /* LO/AUX */
+	{0,     0,    0,    0xFF, 0xFF, 0xFF, 0xFF, 0,    0,    0x00, 0x00}, /* DSD */
+	{0x1FF, 0,    0,    0x8,  0x8,  0x0F, 0,    0,    0,    0x00, 0x01}, /* PCM_OUT */
+};
+#else
+
 static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
 	{7,    1,    0xFF, 0xFF, 0xFF, 0xFF, 0, 0xFF, 0xFF, 0x00, 0x00}, /* SPKR1 */
 	{31,   3,    7,    0xFF, 0xFF, 0xFF, 1, 0xFF, 0xFF, 0x00, 0x00}, /* CMP1 */
@@ -94,7 +146,9 @@ static struct port_params rx_frame_params_44p1KHz[SWR_MSTR_PORT_LEN] = {
 	{0xFF,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* CMPT */
 	{0xFF,  0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF}, /* IPCM */
 };
+#endif
 
+/* Port configurations to support wcd937x wcd939x */
 static struct swr_mstr_port_map sm_port_map[] = {
 	{RX_MACRO, SWR_UC0, rx_frame_params_default},
 	{RX_MACRO, SWR_UC1, rx_frame_params_dsd},

asoc/pineapple.c

@@ -19,6 +19,7 @@
 #include <linux/soc/qcom/wcd939x-i2c.h>
 #endif
 #include <linux/pm_qos.h>
+#include <linux/nvmem-consumer.h>
 #include <sound/control.h>
 #include <sound/core.h>
 #include <sound/soc.h>
@@ -632,35 +633,13 @@ static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
 };
 
 static struct snd_soc_dai_link msm_wcn_btfm_be_dai_links[] = {
-	{
-		.name = LPASS_BE_SLIMBUS_7_RX,
-		.stream_name = LPASS_BE_SLIMBUS_7_RX,
-		.playback_only = 1,
-		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-			SND_SOC_DPCM_TRIGGER_POST},
-		.init = &msm_wcn_init,
-		.ops = &msm_common_be_ops,
-		/* dai link has playback support */
-		.ignore_pmdown_time = 1,
-		.ignore_suspend = 1,
-		SND_SOC_DAILINK_REG(slimbus_7_rx),
-	},
-	{
-		.name = LPASS_BE_SLIMBUS_7_TX,
-		.stream_name = LPASS_BE_SLIMBUS_7_TX,
-		.capture_only = 1,
-		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
-			SND_SOC_DPCM_TRIGGER_POST},
-		.ops = &msm_common_be_ops,
-		.ignore_suspend = 1,
-		SND_SOC_DAILINK_REG(slimbus_7_tx),
-	},
 	{
 		.name = LPASS_BE_SLIMBUS_8_TX,
 		.stream_name = LPASS_BE_SLIMBUS_8_TX,
 		.capture_only = 1,
 		.trigger = {SND_SOC_DPCM_TRIGGER_POST,
 			SND_SOC_DPCM_TRIGGER_POST},
+		.init = &msm_wcn_init,
 		.ops = &msm_common_be_ops,
 		.ignore_suspend = 1,
 		SND_SOC_DAILINK_REG(slimbus_8_tx),
@@ -1328,7 +1307,10 @@ static struct snd_soc_dai_link msm_pineapple_dai_links[
 			ARRAY_SIZE(msm_va_cdc_dma_be_dai_links) +
 			ARRAY_SIZE(ext_disp_be_dai_link) +
 			ARRAY_SIZE(msm_common_be_dai_links) +
+#ifndef CONFIG_AUDIO_BTFM_PROXY
 			ARRAY_SIZE(msm_wcn_btfm_be_dai_links) +
+#endif
+			ARRAY_SIZE(msm_wcn_be_dai_links) +
 			ARRAY_SIZE(msm_mi2s_dai_links) +
 			ARRAY_SIZE(msm_tdm_dai_links)];
 
@@ -1672,6 +1654,7 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, int w
 			       msm_wcn_be_dai_links,
 			       sizeof(msm_wcn_be_dai_links));
 			total_links += ARRAY_SIZE(msm_wcn_be_dai_links);
+#ifndef CONFIG_AUDIO_BTFM_PROXY
 		} else {
 			rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm", &val);
 			if (!rc && val) {
@@ -1682,6 +1665,7 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev, int w
 				       sizeof(msm_wcn_btfm_be_dai_links));
 				total_links += ARRAY_SIZE(msm_wcn_btfm_be_dai_links);
 			}
+#endif
 		}
 
 		dailink = msm_pineapple_dai_links;
@@ -2291,6 +2275,50 @@ void msm_common_set_pdata(struct snd_soc_card *card,
 	pdata->common_pdata = common_pdata;
 }
 
+static int msm_asoc_parse_soundcard_name(struct platform_device *pdev,
+				struct snd_soc_card *card)
+{
+	struct nvmem_cell *cell = NULL;
+	size_t len = 0;
+	u32 *buf = NULL;
+	u32 adsp_var_idx = 0;
+	int ret = 0;
+
+	/* get adsp variant idx */
+	cell = nvmem_cell_get(&pdev->dev, "adsp_variant");
+	if (IS_ERR_OR_NULL(cell)) {
+		dev_dbg(&pdev->dev, "%s: FAILED to get nvmem cell\n", __func__);
+		goto parse;
+	}
+	buf = nvmem_cell_read(cell, &len);
+	nvmem_cell_put(cell);
+	if (IS_ERR_OR_NULL(buf)) {
+		dev_dbg(&pdev->dev, "%s: FAILED to read nvmem cell\n", __func__);
+		goto parse;
+	}
+	if (len <= 0 || len > sizeof(u32)) {
+		dev_dbg(&pdev->dev, "%s: nvmem cell length out of range: %d\n",
+			__func__, len);
+		kfree(buf);
+		goto parse;
+	}
+
+	memcpy(&adsp_var_idx, buf, len);
+	kfree(buf);
+
+parse:
+	if (adsp_var_idx)
+		ret = snd_soc_of_parse_card_name(card, "qcom,sku-model");
+	else
+		ret = snd_soc_of_parse_card_name(card, "qcom,model");
+
+	if (ret)
+		dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
+			__func__, ret);
+
+	return ret;
+}
+
 static int msm_asoc_machine_probe(struct platform_device *pdev)
 {
 	struct snd_soc_card *card = NULL;
@@ -2345,9 +2373,9 @@ static int msm_asoc_machine_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, card);
 	snd_soc_card_set_drvdata(card, pdata);
 
-	ret = snd_soc_of_parse_card_name(card, "qcom,model");
+	ret = msm_asoc_parse_soundcard_name(pdev, card);
 	if (ret) {
-		dev_err(&pdev->dev, "%s: parse card name failed, err:%d\n",
+		dev_err(&pdev->dev, "%s: parse soundcard name failed, err:%d\n",
 			__func__, ret);
 		goto err;
 	}

build/pitti.bzl

@@ -34,12 +34,6 @@ def define_pitti():
             "lpass_cdc_wsa2_macro_dlkm",
             "lpass_cdc_wsa_macro_dlkm",
             "wsa881x_analog_dlkm",
-            "wsa883x_dlkm",
-            "wsa884x_dlkm",
-            "wcd937x_dlkm",
-            "wcd937x_slave_dlkm",
-            "wcd938x_dlkm",
-            "wcd938x_slave_dlkm",
             "wcd9378_dlkm",
             "wcd9378_slave_dlkm"
         ],

config/pittiauto.conf

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 /*
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 export CONFIG_SND_SOC_MSM_QDSP6V2_INTF=m
 export CONFIG_SND_SOC_PITTI=m
@@ -28,10 +28,6 @@ export CONFIG_LPASS_CDC_RX_MACRO=m
 export CONFIG_SND_SOC_WSA881X_ANALOG=m
 export CONFIG_WSA881X_TEMP_SENSOR_DISABLE=m
 export CONFIG_SND_SOC_WCD9XXX_V2=m
-export CONFIG_SND_SOC_WCD937X=m
-export CONFIG_SND_SOC_WCD937X_SLAVE=m
-export CONFIG_SND_SOC_WCD938X=m
-export CONFIG_SND_SOC_WCD938X_SLAVE=m
 export CONFIG_SND_SOC_WCD9378=m
 export CONFIG_SND_SOC_WCD9378_SLAVE=m
 export CONFIG_SND_SOC_WCD_MBHC=m

config/pittiautoconf.h

@@ -29,12 +29,8 @@
 #define CONFIG_LPASS_CDC_TX_MACRO 1
 #define CONFIG_LPASS_CDC_RX_MACRO 1
 #define CONFIG_SND_SOC_WCD9XXX_V2 1
-#define CONFIG_SND_SOC_WCD937X 1
-#define CONFIG_SND_SOC_WCD937X_SLAVE 1
 #define CONFIG_SND_SOC_WSA881X_ANALOG 1
 #define CONFIG_WSA881X_TEMP_SENSOR_DISABLE 1
-#define CONFIG_SND_SOC_WCD938X 1
-#define CONFIG_SND_SOC_WCD938X_SLAVE 1
 #define CONFIG_SND_SOC_WCD9378 1
 #define CONFIG_SND_SOC_WCD9378_SLAVE 1
 #define CONFIG_SND_SOC_WCD_MBHC 1

dsp/adsp-loader.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2012-2014, 2017-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/init.h>
@@ -348,6 +348,7 @@ static int adsp_loader_probe(struct platform_device *pdev)
 	size_t len;
 	u32 *buf;
 	const char **adsp_fw_name_array = NULL;
+	const char **adsp_dtb_fw_name_array = NULL;
 	int adsp_fw_cnt;
 	u32* adsp_fw_bit_values = NULL;
 	int i;
@@ -504,6 +505,20 @@ static int adsp_loader_probe(struct platform_device *pdev)
 		goto wqueue;
 	}
 
+	adsp_dtb_fw_name_array = devm_kzalloc(&pdev->dev,
+				adsp_fw_cnt * sizeof(char *), GFP_KERNEL);
+
+	/* Read ADSP dtb firmware image names */
+	ret = of_property_read_string_array(pdev->dev.of_node,
+					"adsp-dtb-fw-names",
+					adsp_dtb_fw_name_array,
+					adsp_fw_cnt);
+	if (ret < 0) {
+		dev_dbg(&pdev->dev, "%s: unable to read adsp-dtb-fw-names\n",
+			__func__);
+		goto wqueue;
+	}
+
 	for (i = 0; i < adsp_fw_cnt; i++) {
 		if (adsp_fw_bit_values[i] == adsp_var_idx) {
 			fw_name_size = strlen(adsp_fw_name_array[i]) + 1;
@@ -514,6 +529,15 @@ static int adsp_loader_probe(struct platform_device *pdev)
 				goto wqueue;
 			strlcpy(priv->adsp_fw_name, adsp_fw_name_array[i],
 				fw_name_size);
+
+			fw_name_size = strlen(adsp_dtb_fw_name_array[i]) + 1;
+			priv->adsp_dtb_name = devm_kzalloc(&pdev->dev,
+						fw_name_size,
+						GFP_KERNEL);
+			if (!priv->adsp_dtb_name)
+				goto wqueue;
+			strscpy(priv->adsp_dtb_name, adsp_dtb_fw_name_array[i],
+				fw_name_size);
 			break;
 		}
 	}

include/bindings/qcom,audio-ext-clk.h

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
-/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
- */
+/* Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.*/
+/* Copyright (c) 2023-2024 Qualcomm Innovation Center, Inc. All rights reserved.*/
 
 #ifndef __AUDIO_EXT_CLK_H
 #define __AUDIO_EXT_CLK_H
@@ -23,5 +23,7 @@
 #define AUDIO_LPASS_MCLK_11           14 /* WSA_TX CORE CLK */
 #define AUDIO_LPASS_MCLK_12           15 /* WSA2_TX CORE CLK */
 #define AUDIO_LPASS_MCLK_13           16 /* RX_MCLK2 2X CLK */
-
+#define AUDIO_LPASS_MCLK_14           17 /* HW SEQUNCER MCLK */
+#define AUDIO_LPASS_MCLK_15           18 /* BT_SWR CLK */
+#define AUDIO_LPASS_MCLK_16           19 /* BT_SWR 2X CLK */
 #endif

include/soc/soundwire.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _LINUX_SOUNDWIRE_H
@@ -273,6 +273,8 @@ struct swr_device {
 	bool paging_support;
 	struct irq_domain *slave_irq;
 	bool slave_irq_pending;
+	u8 scp1_val; /*used for v1.2 or class devices*/
+	u8 scp2_val; /*used for v1.2 or class devices*/
 };
 
 static inline struct swr_device *to_swr_device(struct device *dev)

soc/Kbuild

@@ -59,7 +59,11 @@ ifeq ($(KERNEL_BUILD), 0)
 		include $(AUDIO_ROOT)/config/kalamaauto.conf
 		INCS    +=  -include $(AUDIO_ROOT)/config/kalamaautoconf.h
 	endif
-	ifeq ($(CONFIG_ARCH_PINEAPPLE), y)
+	ifeq ($(BOARD_PLATFORM), pineapple)
+		include $(AUDIO_ROOT)/config/pineappleauto.conf
+		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
+	endif
+	ifeq ($(BOARD_PLATFORM), cliffs)
 		include $(AUDIO_ROOT)/config/pineappleauto.conf
 		INCS    +=  -include $(AUDIO_ROOT)/config/pineappleautoconf.h
 	endif

soc/regmap-swr.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
- * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/device.h>
@@ -24,8 +24,7 @@
 #define SCP1_ADDRESS              (0X48)
 #define SCP2_ADDRESS              (0X49)
 #define SDCA_READ_WRITE_BIT       (0x8000)
-u8 g_scp1_val;
-u8 g_scp2_val;
+
 static DEFINE_MUTEX(swr_rw_lock);
 
 static int regmap_swr_reg_address_get(struct swr_device *swr,
@@ -43,24 +42,24 @@ static int regmap_swr_reg_address_get(struct swr_device *swr,
 		scp2_val = temp >> SCP2_ADDRESS_VAL_SHIFT;
 
 		if (scp1_val || scp2_val) {
-			if (scp1_val != g_scp1_val) {
+			if (scp1_val != swr->scp1_val) {
 				ret = swr_write(swr, swr->dev_num, SCP1_ADDRESS, &scp1_val);
 				if (ret < 0) {
 					dev_err(&swr->dev, "%s: write reg scp1_address failed, err %d\n",
 						__func__, ret);
 					return ret;
 				}
-				g_scp1_val = scp1_val;
+				swr->scp1_val = scp1_val;
 			}
 
-			if (scp2_val != g_scp2_val) {
+			if (scp2_val != swr->scp2_val) {
 				ret = swr_write(swr, swr->dev_num, SCP2_ADDRESS, &scp2_val);
 				if (ret < 0) {
 					dev_err(&swr->dev, "%s: write reg scp2_address failed, err %d\n",
 					__func__, ret);
 					return ret;
 				}
-				g_scp2_val = scp2_val;
+				swr->scp2_val = scp2_val;
 			}
 			*reg_addr = (*(u16 *)reg | SDCA_READ_WRITE_BIT);
 			dev_dbg(&swr->dev, "%s: reg: 0x%x, scp1_val: 0x%x, scp2_val: 0x%x, reg_addr: 0x%x\n",

soc/swr-mstr-ctrl.c

@@ -786,15 +786,44 @@ static int swrm_pcm_port_config(struct swr_mstr_ctrl *swrm, u8 port_num,
 		return -EINVAL;
 	}
 
-	if (stream_type == SWR_PDM)
+	switch (stream_type) {
+	case SWR_PCM:
+	case SWR_PDM_32:
+		if (swrm->version != SWRM_VERSION_1_7) {
+			if (dir)
+				reg_addr = SWRM_DIN_DP_PCM_PORT_CTRL(port_num);
+			else
+				reg_addr = SWRM_DOUT_DP_PCM_PORT_CTRL(port_num);
+			reg_val = enable ? 0x3 : 0x0;
+			swr_master_write(swrm, reg_addr, reg_val);
+		} else if (stream_type == SWR_PCM) {
+			if (dir)
+				reg_addr = SWRM_DIN_DP_PCM_PORT_CTRL(port_num);
+			else
+				reg_addr = SWRM_DOUT_DP_PCM_PORT_CTRL(port_num);
+			swr_master_write(swrm, reg_addr, enable);
+		}
+		break;
+	case SWR_PDM:
+	default:
 		return 0;
+	}
+	if (swrm->version == SWRM_VERSION_1_7) {
+		reg_val = SWRM_COMP_FEATURE_CFG_DEFAULT_VAL_V1P7;
 
-	reg_addr = ((dir) ? SWRM_DIN_DP_PCM_PORT_CTRL(port_num) : \
-			SWRM_DOUT_DP_PCM_PORT_CTRL(port_num));
-	reg_val = enable ? 0x3 : 0x0;
-	swr_master_write(swrm, reg_addr, reg_val);
-	dev_dbg(swrm->dev, "%s : pcm port %s, reg_val = %d, for addr %x\n",
-			__func__, enable ? "Enabled" : "disabled", reg_val, reg_addr);
+		if (enable) {
+			if (swrm->pcm_enable_count == 0) {
+				reg_val |= SWRM_COMP_FEATURE_CFG_PCM_EN_MASK;
+				swr_master_write(swrm, SWRM_COMP_FEATURE_CFG, reg_val);
+			}
+			swrm->pcm_enable_count++;
+		} else {
+			if (swrm->pcm_enable_count > 0)
+				swrm->pcm_enable_count--;
+			if (swrm->pcm_enable_count == 0)
+				swr_master_write(swrm, SWRM_COMP_FEATURE_CFG, reg_val);
+		}
+	}
 	return 0;
 }
 
@@ -1692,6 +1721,8 @@ static int swrm_slvdev_datapath_control(struct swr_master *master, bool enable)
 		}
 		clear_bit(DISABLE_PENDING, &swrm->port_req_pending);
 		swrm_cleanup_disabled_port_reqs(master);
+		/* reset enable_count to 0 in SSR if master is already down */
+		swrm->pcm_enable_count = 0;
 		if (!swrm_is_port_en(master)) {
 			dev_dbg(&master->dev, "%s: pm_runtime auto suspend triggered\n",
 				__func__);
@@ -2273,6 +2304,7 @@ handle_irq:
 				swrm->clk_stop_wakeup = false;
 			}
 			break;
+#ifdef CONFIG_SWRM_VER_2P0
 		case SWRM_INTERRUPT_STATUS_CMD_IGNORED_AND_EXEC_CONTINUED:
 			value = swr_master_read(swrm, SWRM_CMD_FIFO_STATUS(swrm->ee_val));
 			dev_err_ratelimited(swrm->dev,
@@ -2281,6 +2313,7 @@ handle_irq:
 			/* Wait 3.5ms to clear */
 			usleep_range(3500, 3505);
 			break;
+#endif
 		case SWRM_INTERRUPT_STATUS_DOUT_RATE_MISMATCH:
 			dev_err(swrm->dev,
 				"%s: SWR Port Channel rate mismatch\n", __func__);
@@ -2348,8 +2381,10 @@ static irqreturn_t swrm_wakeup_interrupt(int irq, void *dev)
 			}
 			mutex_lock(&swrm->irq_lock);
 			if (!irqd_irq_disabled(
-			    irq_get_irq_data(swrm->wake_irq)))
+			irq_get_irq_data(swrm->wake_irq))) {
+				irq_set_irq_wake(swrm->wake_irq, 0);
 				disable_irq_nosync(swrm->wake_irq);
+			}
 			mutex_unlock(&swrm->irq_lock);
 		}
 		mutex_unlock(&swrm->devlock);
@@ -2366,9 +2401,10 @@ static irqreturn_t swrm_wakeup_interrupt(int irq, void *dev)
 			return IRQ_NONE;
 		}
 		mutex_lock(&swrm->irq_lock);
-		if (!irqd_irq_disabled(
-		    irq_get_irq_data(swrm->wake_irq)))
+		if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) {
+			irq_set_irq_wake(swrm->wake_irq, 0);
 			disable_irq_nosync(swrm->wake_irq);
+		}
 		mutex_unlock(&swrm->irq_lock);
 	}
 	pm_runtime_get_sync(swrm->dev);
@@ -2613,6 +2649,14 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm)
 	value[len++] = 0x01;
 #endif
 
+#ifdef CONFIG_SWRM_VER_1P7
+	reg[len] = SWRM_MCP_BUS_CTRL;
+	if (swrm->version < SWRM_VERSION_1_7)
+		value[len++] = 0x2;
+	else
+		value[len++] = 0x2 << swrm->ee_val;
+#endif
+
 	/* Set IRQ to PULSE */
 	reg[len] = SWRM_COMP_CFG;
 	value[len++] = 0x02;
@@ -2827,7 +2871,7 @@ static int swrm_probe(struct platform_device *pdev)
 		dev_err(swrm->dev, "missing port mapping\n");
 		goto err_pdata_fail;
 	}
-
+	swrm->pcm_enable_count = 0;
 	map_length = map_size / (3 * sizeof(u32));
 	if (num_ports > SWR_MSTR_PORT_LEN) {
 		dev_err(&pdev->dev, "%s:invalid number of swr ports\n",
@@ -3031,10 +3075,12 @@ static int swrm_probe(struct platform_device *pdev)
 				& SWRM_COMP_PARAMS_WR_FIFO_DEPTH) >> 10);
 
 	swrm_hw_ver = swr_master_read(swrm, SWRM_COMP_HW_VERSION);
-	if (swrm->version != swrm_hw_ver)
+	if (swrm->version != swrm_hw_ver) {
 		dev_info(&pdev->dev,
 			 "%s: version specified in dtsi: 0x%x not match with HW read version 0x%x\n",
 			 __func__, swrm->version, swrm_hw_ver);
+		swrm->version = swrm_hw_ver;
+	}
 
 	swrm->num_auto_enum = ((swr_master_read(swrm, SWRM_COMP_PARAMS)
                                 & SWRM_COMP_PARAMS_AUTO_ENUM_SLAVES) >> 20);
@@ -3194,7 +3240,7 @@ static int swrm_runtime_resume(struct device *dev)
 {
 	struct platform_device *pdev = to_platform_device(dev);
 	struct swr_mstr_ctrl *swrm = platform_get_drvdata(pdev);
-	int ret = 0;
+	int ret = 0, val = 0;
 	bool swrm_clk_req_err = false;
 	bool hw_core_err = false, aud_core_err = false;
 	struct swr_master *mstr = &swrm->master;
@@ -3238,9 +3284,10 @@ static int swrm_runtime_resume(struct device *dev)
 					return IRQ_NONE;
 				}
 				mutex_lock(&swrm->irq_lock);
-				if (!irqd_irq_disabled(
-				    irq_get_irq_data(swrm->wake_irq)))
+				if (!irqd_irq_disabled(irq_get_irq_data(swrm->wake_irq))) {
+					irq_set_irq_wake(swrm->wake_irq, 0);
 					disable_irq_nosync(swrm->wake_irq);
+				}
 				mutex_unlock(&swrm->irq_lock);
 			}
 			if (swrm->ipc_wakeup)
@@ -3297,10 +3344,16 @@ static int swrm_runtime_resume(struct device *dev)
 			}
 			/*wake up from clock stop*/
 #ifdef CONFIG_SWRM_VER_2P0
+			val = 0x01;
 			swr_master_write(swrm,
-				SWRM_CLK_CTRL(swrm->ee_val), 0x01);
+				SWRM_CLK_CTRL(swrm->ee_val), val);
 #else
-			swr_master_write(swrm, SWRM_MCP_BUS_CTRL, 0x2);
+			if (swrm->version < SWRM_VERSION_1_7)
+				val = 0x2;
+			else
+				val = 0x2 << swrm->ee_val;
+
+			swr_master_write(swrm, SWRM_MCP_BUS_CTRL, val);
 #endif
 			/* clear and enable bus clash interrupt */
 			swr_master_write(swrm,
@@ -3425,8 +3478,12 @@ chk_lnk_status:
 		if (swrm->clk_stop_mode0_supp) {
 			if (swrm->wake_irq > 0) {
 				irq_data = irq_get_irq_data(swrm->wake_irq);
-				if (irq_data && irqd_irq_disabled(irq_data))
+				mutex_lock(&swrm->irq_lock);
+				if (irq_data && irqd_irq_disabled(irq_data)) {
+					irq_set_irq_wake(swrm->wake_irq, 1);
 					enable_irq(swrm->wake_irq);
+				}
+				mutex_unlock(&swrm->irq_lock);
 			} else if (swrm->ipc_wakeup) {
 				//msm_aud_evt_blocking_notifier_call_chain(
 				//	SWR_WAKE_IRQ_REGISTER, (void *)swrm);
@@ -3518,6 +3575,7 @@ int swrm_register_wake_irq(struct swr_mstr_ctrl *swrm)
 			}
 			swrm->wake_irq = dir_apps_irq;
 		}
+		mutex_lock(&swrm->irq_lock);
 		ret = request_threaded_irq(swrm->wake_irq, NULL,
 					   swrm_wakeup_interrupt,
 					   IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
@@ -3525,9 +3583,11 @@ int swrm_register_wake_irq(struct swr_mstr_ctrl *swrm)
 		if (ret) {
 			dev_err_ratelimited(swrm->dev, "%s: Failed to request irq %d\n",
 				__func__, ret);
+			mutex_unlock(&swrm->irq_lock);
 			return -EINVAL;
 		}
 		irq_set_irq_wake(swrm->wake_irq, 1);
+		mutex_unlock(&swrm->irq_lock);
 	}
 	return ret;
 }
@@ -3972,7 +4032,7 @@ static int swrm_suspend(struct device *dev)
 			dev_dbg(swrm->dev, "%s: suspend failed state %d, wlock %d\n",
 				 __func__, swrm->pm_state,
 				 swrm->wlock_holders);
-			return -EBUSY;
+			return 0;
 		} else {
 			dev_dbg(swrm->dev,
 				"%s: done, state %d, wlock %d\n",

soc/swr-mstr-ctrl.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
- * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _SWR_WCD_CTRL_H
@@ -190,6 +190,7 @@ struct swr_mstr_ctrl {
 	int hw_core_clk_en;
 	int aud_core_clk_en;
 	int clk_src;
+	u32 pcm_enable_count;
 	u32 disable_div2_clk_switch;
 	u32 rd_fifo_depth;
 	u32 wr_fifo_depth;

soc/swr-mstr-registers.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2015, 2018-2021 The Linux Foundation. All rights reserved.
- * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _SWRM_REGISTERS_H
@@ -49,7 +49,7 @@
 #define SWRM_INTERRUPT_CLEAR_1(n)                 (SWRM_BASE+0x0228*n)
 #define SWRM_CPU1_INTERRUPT_EN(n)                 (SWRM_BASE+0x0210*n)
 #define SWRM_CPU1_INTERRUPT_EN_1(n)               (SWRM_BASE+0x0230*n)
-#define SWRM_CPU0_CMD_RESPONSE(n)                 (SWRM_BASE+0x0250*n)
+#define SWRM_CPU0_CMD_RESPONSE(n)                 (SWRM_BASE+0x0250+0x4*n)
 
 #define SWRM_CPU1_CMD_FIFO_WR_CMD(n)              (SWRM_BASE+0x031C*n)
 #define SWRM_CPU1_CMD_FIFO_RD_CMD(n)              (SWRM_BASE+0x0320*n)