qcacmn: Device and Target type support for qca6018
Added target and device type support for qca6018. Change-Id: I85382bf053d0a5f34cfaf0cca78a4b66b4265989 CRs-Fixed: 2323023
このコミットが含まれているのは:
@@ -61,6 +61,7 @@ typedef void *hif_handle_t;
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#define HIF_TYPE_QCN7605 17
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#define HIF_TYPE_QCA6390 18
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#define HIF_TYPE_QCA8074V2 19
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#define HIF_TYPE_QCA6018 20
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#ifdef IPA_OFFLOAD
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#define DMA_COHERENT_MASK_IPA_VER_3_AND_ABOVE 37
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@@ -40,5 +40,6 @@ extern struct hostdef_s *IPQ4019_HOSTdef;
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#endif
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extern struct hostdef_s *QCA8074_HOSTdef;
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extern struct hostdef_s *QCA8074V2_HOSTDEF;
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extern struct hostdef_s *QCA6018_HOSTDEF;
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#endif
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@@ -70,6 +70,10 @@ extern "C" {
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#ifndef TARGET_TYPE_QCA8074V2
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#define TARGET_TYPE_QCA8074V2 24
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#endif
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/* For Cypress */
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#ifndef TARGET_TYPE_QCA6018
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#define TARGET_TYPE_QCA6018 25
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#endif
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#ifdef __cplusplus
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}
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@@ -40,6 +40,7 @@ extern struct targetdef_s *IPQ4019_TARGETdef;
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#endif
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extern struct targetdef_s *QCA8074_TARGETdef;
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extern struct targetdef_s *QCA8074V2_TARGETDEF;
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extern struct targetdef_s *QCA6018_TARGETDEF;
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extern struct ce_reg_def *AR6002_CE_TARGETdef;
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extern struct ce_reg_def *AR6003_CE_TARGETdef;
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@@ -57,6 +58,7 @@ extern struct ce_reg_def *IPQ4019_CE_TARGETdef;
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#endif
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extern struct ce_reg_def *QCA8074_CE_TARGETdef;
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extern struct ce_reg_def *QCA8074V2_CE_TARGETDEF;
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extern struct ce_reg_def *QCA6018_CE_TARGETDEF;
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#endif
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@@ -86,7 +86,8 @@ static ssize_t ath_procfs_diag_read(struct file *file, char __user *buf,
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((tgt_info->target_type == TARGET_TYPE_QCA6290) ||
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(tgt_info->target_type == TARGET_TYPE_QCA6390) ||
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(tgt_info->target_type == TARGET_TYPE_QCA8074) ||
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(tgt_info->target_type == TARGET_TYPE_QCA8074V2)))) {
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(tgt_info->target_type == TARGET_TYPE_QCA8074V2) ||
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(tgt_info->target_type == TARGET_TYPE_QCA6018)))) {
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memtype = ((uint32_t)(*pos) & 0xff000000) >> 24;
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offset = (uint32_t)(*pos) & 0xffffff;
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HIF_TRACE("%s: offset 0x%x memtype 0x%x, datalen %zu\n",
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@@ -159,7 +160,8 @@ static ssize_t ath_procfs_diag_write(struct file *file,
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((tgt_info->target_type == TARGET_TYPE_QCA6290) ||
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(tgt_info->target_type == TARGET_TYPE_QCA6390) ||
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(tgt_info->target_type == TARGET_TYPE_QCA8074) ||
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(tgt_info->target_type == TARGET_TYPE_QCA8074V2)))) {
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(tgt_info->target_type == TARGET_TYPE_QCA8074V2) ||
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(tgt_info->target_type == TARGET_TYPE_QCA6018)))) {
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memtype = ((uint32_t)(*pos) & 0xff000000) >> 24;
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offset = (uint32_t)(*pos) & 0xffffff;
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HIF_TRACE("%s: offset 0x%x memtype 0x%x, datalen %zu\n",
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@@ -1001,6 +1001,7 @@ bool ce_srng_based(struct hif_softc *scn)
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case TARGET_TYPE_QCA8074V2:
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case TARGET_TYPE_QCA6290:
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case TARGET_TYPE_QCA6390:
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case TARGET_TYPE_QCA6018:
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return true;
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default:
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return false;
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@@ -2942,6 +2943,7 @@ void hif_ce_prepare_config(struct hif_softc *scn)
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case TARGET_TYPE_QCA8074:
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case TARGET_TYPE_QCA8074V2:
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case TARGET_TYPE_QCA6018:
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if (scn->bus_type == QDF_BUS_TYPE_PCI) {
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hif_state->host_ce_config =
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host_ce_config_wlan_qca8074_pci;
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@@ -828,13 +828,21 @@ int hif_get_device_type(uint32_t device_id,
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break;
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case QCA8074V2_DEVICE_ID:
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*hif_type = HIF_TYPE_QCA8074V2;
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*target_type = TARGET_TYPE_QCA8074V2;
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HIF_INFO(" *********** QCA8074V2 *************\n");
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break;
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case QCA6018_DEVICE_ID:
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case RUMIM2M_DEVICE_ID_NODE0:
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case RUMIM2M_DEVICE_ID_NODE1:
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case RUMIM2M_DEVICE_ID_NODE2:
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case RUMIM2M_DEVICE_ID_NODE3:
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*hif_type = HIF_TYPE_QCA8074V2;
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*target_type = TARGET_TYPE_QCA8074V2;
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HIF_INFO(" *********** QCA8074V2 *************\n");
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case RUMIM2M_DEVICE_ID_NODE4:
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case RUMIM2M_DEVICE_ID_NODE5:
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*hif_type = HIF_TYPE_QCA6018;
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*target_type = TARGET_TYPE_QCA6018;
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HIF_INFO(" *********** QCA6018 *************\n");
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break;
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default:
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@@ -95,6 +95,7 @@
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currently defining this to 0xffff for
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emulation purpose */
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#define QCA8074V2_DEVICE_ID (0xfffe) /* Todo: replace this with actual number */
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#define QCA6018_DEVICE_ID (0xfffd) /* Todo: replace this with actual number */
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/* Genoa */
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#define QCN7605_DEVICE_ID (0x1102) /* Genoa PCIe device ID*/
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#define QCN7605_COMPOSITE (0x9900)
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@@ -104,6 +105,8 @@
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#define RUMIM2M_DEVICE_ID_NODE1 0xabc1
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#define RUMIM2M_DEVICE_ID_NODE2 0xabc2
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#define RUMIM2M_DEVICE_ID_NODE3 0xabc3
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#define RUMIM2M_DEVICE_ID_NODE4 0xaa10
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#define RUMIM2M_DEVICE_ID_NODE5 0xaa11
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#define HIF_GET_PCI_SOFTC(scn) ((struct hif_pci_softc *)scn)
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#define HIF_GET_CE_STATE(scn) ((struct HIF_CE_state *)scn)
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@@ -1983,7 +1983,8 @@ int hif_pci_bus_configure(struct hif_softc *hif_sc)
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/* todo: consider replacing this with an srng field */
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if (((hif_sc->target_info.target_type == TARGET_TYPE_QCA8074) ||
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(hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2)) &&
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(hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2) ||
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(hif_sc->target_info.target_type == TARGET_TYPE_QCA6018)) &&
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(hif_sc->bus_type == QDF_BUS_TYPE_AHB)) {
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hif_sc->per_ce_irq = true;
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}
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@@ -2003,7 +2004,8 @@ int hif_pci_bus_configure(struct hif_softc *hif_sc)
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}
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if (((hif_sc->target_info.target_type == TARGET_TYPE_QCA8074) ||
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(hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2)) &&
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(hif_sc->target_info.target_type == TARGET_TYPE_QCA8074V2) ||
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(hif_sc->target_info.target_type == TARGET_TYPE_QCA6018)) &&
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(hif_sc->bus_type == QDF_BUS_TYPE_PCI))
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HIF_INFO_MED("%s: Skip irq config for PCI based 8074 target",
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__func__);
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@@ -2137,7 +2139,9 @@ static int hif_enable_pci_nopld(struct hif_pci_softc *sc,
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if ((device_id == RUMIM2M_DEVICE_ID_NODE0) ||
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(device_id == RUMIM2M_DEVICE_ID_NODE1) ||
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(device_id == RUMIM2M_DEVICE_ID_NODE2) ||
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(device_id == RUMIM2M_DEVICE_ID_NODE3)) {
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(device_id == RUMIM2M_DEVICE_ID_NODE3) ||
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(device_id == RUMIM2M_DEVICE_ID_NODE4) ||
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(device_id == RUMIM2M_DEVICE_ID_NODE5)) {
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mem = mem + 0x0c000000;
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sc->mem = mem;
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HIF_INFO("%s: Changing PCI mem base to %pK\n",
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@@ -3518,6 +3522,7 @@ int hif_configure_irq(struct hif_softc *scn)
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break;
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case TARGET_TYPE_QCA8074:
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case TARGET_TYPE_QCA8074V2:
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case TARGET_TYPE_QCA6018:
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ret = hif_ahb_configure_irq(sc);
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break;
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default:
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@@ -220,20 +220,20 @@
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#define QCA6018_BOARD_DATA_SZ MISSING
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#define QCA6018_BOARD_EXT_DATA_SZ MISSING
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#define MY_TARGET_DEF QCA6018_TARGETdef
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#define MY_HOST_DEF QCA6018_HOSTdef
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#define MY_CEREG_DEF QCA6018_CE_TARGETdef
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#define MY_TARGET_DEF QCA6018_TARGETDEF
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#define MY_HOST_DEF QCA6018_HOSTDEF
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#define MY_CEREG_DEF QCA6018_CE_TARGETDEF
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#define MY_TARGET_BOARD_DATA_SZ QCA6018_BOARD_DATA_SZ
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#define MY_TARGET_BOARD_EXT_DATA_SZ QCA6018_BOARD_EXT_DATA_SZ
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#include "targetdef.h"
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#include "hostdef.h"
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qdf_export_symbol(QCA6018_CE_TARGETdef);
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qdf_export_symbol(QCA6018_CE_TARGETDEF);
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#else
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#include "common_drv.h"
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#include "targetdef.h"
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#include "hostdef.h"
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struct targetdef_s *QCA6018_TARGETdef;
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struct hostdef_s *QCA6018_HOSTdef;
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struct targetdef_s *QCA6018_TARGETDEF;
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struct hostdef_s *QCA6018_HOSTDEF;
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#endif /*QCA6018_HEADERS_DEF */
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qdf_export_symbol(QCA6018_TARGETdef);
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qdf_export_symbol(QCA6018_HOSTdef);
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qdf_export_symbol(QCA6018_TARGETDEF);
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qdf_export_symbol(QCA6018_HOSTDEF);
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@@ -119,6 +119,12 @@ void hif_target_register_tbl_attach(struct hif_softc *scn, u32 target_type)
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scn->target_ce_def = QCA8074V2_CE_TARGETDEF;
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break;
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#endif
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#if defined(QCA6018_HEADERS_DEF)
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case TARGET_TYPE_QCA6018:
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scn->targetdef = QCA6018_TARGETDEF;
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scn->target_ce_def = QCA6018_CE_TARGETDEF;
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break;
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#endif
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#if defined(QCA6390_HEADERS_DEF)
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case TARGET_TYPE_QCA6390:
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@@ -205,6 +211,12 @@ void hif_register_tbl_attach(struct hif_softc *scn, u32 hif_type)
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scn->hostdef = QCA8074V2_HOSTDEF;
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break;
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#endif
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#if defined(QCA6018_HEADERS_DEF)
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case HIF_TYPE_QCA6018:
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scn->hostdef = QCA6018_HOSTDEF;
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HIF_TRACE("%s: HIF_TYPE_QCA6018", __func__);
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break;
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#endif
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#if defined(QCA6290_HEADERS_DEF)
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case HIF_TYPE_QCA6290:
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scn->hostdef = QCA6290_HOSTdef;
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@@ -442,7 +442,8 @@ void hif_ahb_disable_bus(struct hif_softc *scn)
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/* Should not be executed on 8074 platform */
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if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
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(tgt_info->target_type != TARGET_TYPE_QCA8074V2)) {
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(tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
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(tgt_info->target_type != TARGET_TYPE_QCA6018)) {
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hif_ahb_clk_enable_disable(&pdev->dev, 0);
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hif_ahb_device_reset(scn);
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@@ -545,7 +546,8 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
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/* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */
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if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
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(tgt_info->target_type != TARGET_TYPE_QCA8074V2)) {
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(tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
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(tgt_info->target_type != TARGET_TYPE_QCA6018)) {
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if (hif_ahb_enable_radio(sc, pdev, id) != 0) {
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HIF_INFO("error in enabling soc\n");
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return -EIO;
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@@ -563,7 +565,8 @@ QDF_STATUS hif_ahb_enable_bus(struct hif_softc *ol_sc,
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err_target_sync:
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/* QCA_WIFI_QCA8074_VP:Should not be executed on 8074 VP platform */
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if ((tgt_info->target_type != TARGET_TYPE_QCA8074) &&
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(tgt_info->target_type != TARGET_TYPE_QCA8074V2)) {
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(tgt_info->target_type != TARGET_TYPE_QCA8074V2) &&
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(tgt_info->target_type != TARGET_TYPE_QCA6018)) {
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HIF_INFO("Error: Disabling target\n");
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hif_ahb_disable_bus(ol_sc);
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}
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@@ -668,9 +671,10 @@ void hif_ahb_irq_enable(struct hif_softc *scn, int ce_id)
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regval |= HOST_IE_REG2_CE_BIT(ce_id);
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hif_write32_mb(scn, scn->mem + reg_offset, regval);
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if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
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tgt_info->target_type == TARGET_TYPE_QCA8074V2) {
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tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
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tgt_info->target_type == TARGET_TYPE_QCA6018) {
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/* Enable destination ring interrupts for
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* 8074 and 8074V2
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* 8074, 8074V2 and 6018
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*/
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regval = hif_read32_mb(scn, scn->mem +
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HOST_IE_ADDRESS_3);
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@@ -717,9 +721,10 @@ void hif_ahb_irq_disable(struct hif_softc *scn, int ce_id)
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regval &= ~HOST_IE_REG2_CE_BIT(ce_id);
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hif_write32_mb(scn, scn->mem + reg_offset, regval);
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if (tgt_info->target_type == TARGET_TYPE_QCA8074 ||
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tgt_info->target_type == TARGET_TYPE_QCA8074V2) {
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tgt_info->target_type == TARGET_TYPE_QCA8074V2 ||
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tgt_info->target_type == TARGET_TYPE_QCA6018) {
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/* Disable destination ring interrupts for
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* 8074 and 8074V2
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* 8074, 8074V2 and 6018
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*/
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regval = hif_read32_mb(scn, scn->mem +
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HOST_IE_ADDRESS_3);
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