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@@ -12,6 +12,7 @@
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#include <media/cam_req_mgr.h>
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#include <media/cam_req_mgr.h>
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#include <dt-bindings/msm/msm-camera.h>
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#include <dt-bindings/msm/msm-camera.h>
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+#include "cam_isp_hw_mgr_intf.h"
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#include "cam_ife_csid_core.h"
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#include "cam_ife_csid_core.h"
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#include "cam_isp_hw.h"
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#include "cam_isp_hw.h"
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#include "cam_soc_util.h"
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#include "cam_soc_util.h"
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@@ -19,6 +20,7 @@
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#include "cam_debug_util.h"
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#include "cam_debug_util.h"
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#include "cam_cpas_api.h"
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#include "cam_cpas_api.h"
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#include "cam_subdev.h"
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#include "cam_subdev.h"
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+#include "cam_tasklet_util.h"
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/* Timeout value in msec */
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/* Timeout value in msec */
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#define IFE_CSID_TIMEOUT 1000
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#define IFE_CSID_TIMEOUT 1000
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@@ -1227,6 +1229,8 @@ int cam_ife_csid_path_reserve(struct cam_ife_csid_hw *csid_hw,
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csid_hw->hw_intf->hw_idx, reserve->res_id,
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csid_hw->hw_intf->hw_idx, reserve->res_id,
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path_data->width, path_data->height);
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path_data->width, path_data->height);
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reserve->node_res = res;
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reserve->node_res = res;
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+ csid_hw->event_cb = reserve->event_cb;
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+ csid_hw->priv = reserve->priv;
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end:
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end:
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return rc;
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return rc;
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@@ -1327,8 +1331,10 @@ static int cam_ife_csid_enable_hw(struct cam_ife_csid_hw *csid_hw)
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csid_hw->csid_info->hw_reg_version);
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csid_hw->csid_info->hw_reg_version);
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spin_lock_irqsave(&csid_hw->lock_state, flags);
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spin_lock_irqsave(&csid_hw->lock_state, flags);
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+ csid_hw->fatal_err_detected = false;
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csid_hw->device_enabled = 1;
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csid_hw->device_enabled = 1;
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spin_unlock_irqrestore(&csid_hw->lock_state, flags);
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spin_unlock_irqrestore(&csid_hw->lock_state, flags);
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+ cam_tasklet_start(csid_hw->tasklet);
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return 0;
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return 0;
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@@ -1381,6 +1387,7 @@ static int cam_ife_csid_disable_hw(struct cam_ife_csid_hw *csid_hw)
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CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed",
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CAM_ERR(CAM_ISP, "CSID:%d Disable CSID SOC failed",
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csid_hw->hw_intf->hw_idx);
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csid_hw->hw_intf->hw_idx);
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+ cam_tasklet_stop(csid_hw->tasklet);
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spin_lock_irqsave(&csid_hw->lock_state, flags);
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spin_lock_irqsave(&csid_hw->lock_state, flags);
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csid_hw->device_enabled = 0;
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csid_hw->device_enabled = 0;
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spin_unlock_irqrestore(&csid_hw->lock_state, flags);
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spin_unlock_irqrestore(&csid_hw->lock_state, flags);
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@@ -3353,6 +3360,8 @@ int cam_ife_csid_release(void *hw_priv,
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res = (struct cam_isp_resource_node *)release_args;
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res = (struct cam_isp_resource_node *)release_args;
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mutex_lock(&csid_hw->hw_info->hw_mutex);
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mutex_lock(&csid_hw->hw_info->hw_mutex);
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+ csid_hw->event_cb = NULL;
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+ csid_hw->priv = NULL;
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if ((res->res_type == CAM_ISP_RESOURCE_CID &&
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if ((res->res_type == CAM_ISP_RESOURCE_CID &&
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res->res_id >= CAM_IFE_CSID_CID_MAX) ||
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res->res_id >= CAM_IFE_CSID_CID_MAX) ||
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(res->res_type == CAM_ISP_RESOURCE_PIX_PATH &&
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(res->res_type == CAM_ISP_RESOURCE_PIX_PATH &&
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@@ -4165,16 +4174,208 @@ static int cam_ife_csid_process_cmd(void *hw_priv,
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}
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}
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+static int cam_csid_get_evt_payload(
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+ struct cam_ife_csid_hw *csid_hw,
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+ struct cam_csid_evt_payload **evt_payload)
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+{
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+
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+ spin_lock(&csid_hw->lock_state);
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+
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+ if (list_empty(&csid_hw->free_payload_list)) {
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+ *evt_payload = NULL;
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+ spin_unlock(&csid_hw->lock_state);
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+ CAM_ERR_RATE_LIMIT(CAM_ISP, "No free payload core %d",
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+ csid_hw->hw_intf->hw_idx);
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+ return -ENOMEM;
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+ }
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+
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+ *evt_payload = list_first_entry(&csid_hw->free_payload_list,
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+ struct cam_csid_evt_payload, list);
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+ list_del_init(&(*evt_payload)->list);
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+ spin_unlock(&csid_hw->lock_state);
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+
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+ return 0;
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+}
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+
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+static int cam_csid_put_evt_payload(
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+ struct cam_ife_csid_hw *csid_hw,
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+ struct cam_csid_evt_payload **evt_payload)
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+{
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+ unsigned long flags;
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+
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+ if (*evt_payload == NULL) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid payload core %d",
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+ csid_hw->hw_intf->hw_idx);
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+ return -EINVAL;
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+ }
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+ spin_lock_irqsave(&csid_hw->lock_state, flags);
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+ list_add_tail(&(*evt_payload)->list,
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+ &csid_hw->free_payload_list);
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+ *evt_payload = NULL;
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+ spin_unlock_irqrestore(&csid_hw->lock_state, flags);
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+
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+ return 0;
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+}
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+static char *cam_csid_status_to_str(uint32_t status)
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+{
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+ switch (status) {
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+ case CAM_IFE_CSID_IRQ_REG_TOP:
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+ return "TOP";
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+ case CAM_IFE_CSID_IRQ_REG_RX:
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+ return "RX";
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+ case CAM_IFE_CSID_IRQ_REG_IPP:
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+ return "IPP";
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+ case CAM_IFE_CSID_IRQ_REG_PPP:
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+ return "PPP";
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+ case CAM_IFE_CSID_IRQ_REG_RDI_0:
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+ return "RDI0";
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+ case CAM_IFE_CSID_IRQ_REG_RDI_1:
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+ return "RDI1";
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+ case CAM_IFE_CSID_IRQ_REG_RDI_2:
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+ return "RDI2";
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+ case CAM_IFE_CSID_IRQ_REG_RDI_3:
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+ return "RDI3";
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+ case CAM_IFE_CSID_IRQ_REG_UDI_0:
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+ return "UDI0";
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+ case CAM_IFE_CSID_IRQ_REG_UDI_1:
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+ return "UDI1";
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+ case CAM_IFE_CSID_IRQ_REG_UDI_2:
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+ return "UDI2";
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+ default:
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+ return "Invalid IRQ";
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+ }
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+}
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+
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+static int cam_csid_evt_bottom_half_handler(
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+ void *handler_priv,
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+ void *evt_payload_priv)
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+{
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+ struct cam_ife_csid_hw *csid_hw;
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+ struct cam_csid_evt_payload *evt_payload;
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+ int i;
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+ int rc = 0;
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+ struct cam_isp_hw_event_info event_info;
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+
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+ if (!handler_priv || !evt_payload_priv) {
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+ CAM_ERR(CAM_ISP,
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+ "Invalid Param handler_priv %pK evt_payload_priv %pK",
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+ handler_priv, evt_payload_priv);
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+ return 0;
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+ }
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+
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+ csid_hw = (struct cam_ife_csid_hw *)handler_priv;
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+ evt_payload = (struct cam_csid_evt_payload *)evt_payload_priv;
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+
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+ if (!csid_hw->event_cb || !csid_hw->priv) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP,
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+ "hw_idx %d Invalid args %pK %pK",
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+ csid_hw->hw_intf->hw_idx,
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+ csid_hw->event_cb,
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+ csid_hw->priv);
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+ goto end;
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+ }
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+
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+ if (csid_hw->priv != evt_payload->priv) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP,
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+ "hw_idx %d priv mismatch %pK, %pK",
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+ csid_hw->hw_intf->hw_idx,
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+ csid_hw->priv,
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+ evt_payload->priv);
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+ goto end;
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+ }
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+
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+ CAM_ERR_RATE_LIMIT(CAM_ISP, "idx %d err %d phy %d cnt %d",
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+ csid_hw->hw_intf->hw_idx,
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+ evt_payload->evt_type,
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+ csid_hw->csi2_rx_cfg.phy_sel,
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+ csid_hw->csi2_cfg_cnt);
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+
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+ for (i = 0; i < CAM_IFE_CSID_IRQ_REG_MAX; i++)
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+ CAM_ERR_RATE_LIMIT(CAM_ISP, "status %s: %x",
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+ cam_csid_status_to_str(i),
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+ evt_payload->irq_status[i]);
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+
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+ /* this hunk can be extended to handle more cases
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+ * which we want to offload to bottom half from
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+ * irq handlers
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+ */
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+ event_info.err_type = evt_payload->evt_type;
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+ event_info.hw_idx = evt_payload->hw_idx;
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+
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+ switch (evt_payload->evt_type) {
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+ case CAM_ISP_HW_ERROR_CSID_FATAL:
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+ if (csid_hw->fatal_err_detected)
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+ break;
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+ csid_hw->fatal_err_detected = true;
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+ rc = csid_hw->event_cb(NULL,
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+ CAM_ISP_HW_EVENT_ERROR, (void *)&event_info);
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+ break;
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+
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+ default:
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+ CAM_DBG(CAM_ISP, "CSID[%d] invalid error type %d",
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+ csid_hw->hw_intf->hw_idx,
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+ evt_payload->evt_type);
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+ break;
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+ }
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+end:
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+ cam_csid_put_evt_payload(csid_hw, &evt_payload);
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+ return 0;
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+}
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+
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+static int cam_csid_handle_hw_err_irq(
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+ struct cam_ife_csid_hw *csid_hw,
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+ int evt_type,
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+ uint32_t *irq_status)
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+{
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+ int rc = 0;
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+ int i;
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+ void *bh_cmd = NULL;
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+ struct cam_csid_evt_payload *evt_payload;
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+
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+ CAM_DBG(CAM_ISP, "CSID[%d] error %d",
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+ csid_hw->hw_intf->hw_idx, evt_type);
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+
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+ rc = cam_csid_get_evt_payload(csid_hw, &evt_payload);
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+ if (rc) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP,
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+ "No free payload core %d",
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+ csid_hw->hw_intf->hw_idx);
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+ return rc;
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+ }
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+
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+ rc = tasklet_bh_api.get_bh_payload_func(csid_hw->tasklet, &bh_cmd);
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+ if (rc || !bh_cmd) {
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+ CAM_ERR_RATE_LIMIT(CAM_ISP,
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+ "CSID[%d] Can not get cmd for tasklet, evt_type %d",
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+ csid_hw->hw_intf->hw_idx,
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+ evt_type);
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+ return rc;
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+ }
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+
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+ evt_payload->evt_type = evt_type;
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+ evt_payload->priv = csid_hw->priv;
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+ evt_payload->hw_idx = csid_hw->hw_intf->hw_idx;
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+
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+ for (i = 0; i < CAM_IFE_CSID_IRQ_REG_MAX; i++)
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+ evt_payload->irq_status[i] = irq_status[i];
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+
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+ tasklet_bh_api.bottom_half_enqueue_func(csid_hw->tasklet,
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+ bh_cmd,
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+ csid_hw,
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+ evt_payload,
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+ cam_csid_evt_bottom_half_handler);
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+
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+ return rc;
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+}
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+
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irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
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irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
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{
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{
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struct cam_ife_csid_hw *csid_hw;
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struct cam_ife_csid_hw *csid_hw;
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struct cam_hw_soc_info *soc_info;
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struct cam_hw_soc_info *soc_info;
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const struct cam_ife_csid_reg_offset *csid_reg;
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const struct cam_ife_csid_reg_offset *csid_reg;
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const struct cam_ife_csid_csi2_rx_reg_offset *csi2_reg;
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const struct cam_ife_csid_csi2_rx_reg_offset *csi2_reg;
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- uint32_t i, irq_status_top, irq_status_rx, irq_status_ipp = 0;
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- uint32_t irq_status_rdi[CAM_IFE_CSID_RDI_MAX] = {0, 0, 0, 0};
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- uint32_t irq_status_udi[CAM_IFE_CSID_UDI_MAX] = {0, 0, 0};
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- uint32_t val, val2, irq_status_ppp = 0;
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+ uint32_t irq_status[CAM_IFE_CSID_IRQ_REG_MAX] = {0};
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+ uint32_t i, val, val2;
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bool fatal_err_detected = false;
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bool fatal_err_detected = false;
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uint32_t sof_irq_debug_en = 0;
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uint32_t sof_irq_debug_en = 0;
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unsigned long flags;
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unsigned long flags;
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@@ -4193,23 +4394,27 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
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csi2_reg = csid_reg->csi2_reg;
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csi2_reg = csid_reg->csi2_reg;
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/* read */
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/* read */
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- irq_status_top = cam_io_r_mb(soc_info->reg_map[0].mem_base +
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+ irq_status[CAM_IFE_CSID_IRQ_REG_TOP] =
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+ cam_io_r_mb(soc_info->reg_map[0].mem_base +
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csid_reg->cmn_reg->csid_top_irq_status_addr);
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csid_reg->cmn_reg->csid_top_irq_status_addr);
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- irq_status_rx = cam_io_r_mb(soc_info->reg_map[0].mem_base +
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+ irq_status[CAM_IFE_CSID_IRQ_REG_RX] =
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+ cam_io_r_mb(soc_info->reg_map[0].mem_base +
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csid_reg->csi2_reg->csid_csi2_rx_irq_status_addr);
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csid_reg->csi2_reg->csid_csi2_rx_irq_status_addr);
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if (csid_reg->cmn_reg->num_pix)
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if (csid_reg->cmn_reg->num_pix)
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- irq_status_ipp = cam_io_r_mb(soc_info->reg_map[0].mem_base +
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+ irq_status[CAM_IFE_CSID_IRQ_REG_IPP] =
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+ cam_io_r_mb(soc_info->reg_map[0].mem_base +
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csid_reg->ipp_reg->csid_pxl_irq_status_addr);
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csid_reg->ipp_reg->csid_pxl_irq_status_addr);
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if (csid_reg->cmn_reg->num_ppp)
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if (csid_reg->cmn_reg->num_ppp)
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- irq_status_ppp = cam_io_r_mb(soc_info->reg_map[0].mem_base +
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+ irq_status[CAM_IFE_CSID_IRQ_REG_PPP] =
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+ cam_io_r_mb(soc_info->reg_map[0].mem_base +
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csid_reg->ppp_reg->csid_pxl_irq_status_addr);
|
|
csid_reg->ppp_reg->csid_pxl_irq_status_addr);
|
|
|
|
|
|
if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) {
|
|
if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) {
|
|
- irq_status_rdi[i] =
|
|
|
|
|
|
+ irq_status[i] =
|
|
cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr);
|
|
csid_reg->rdi_reg[i]->csid_rdi_irq_status_addr);
|
|
}
|
|
}
|
|
@@ -4217,7 +4422,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
|
|
|
|
if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) {
|
|
if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) {
|
|
- irq_status_udi[i] =
|
|
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] =
|
|
cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
csid_reg->udi_reg[i]->csid_udi_irq_status_addr);
|
|
csid_reg->udi_reg[i]->csid_udi_irq_status_addr);
|
|
}
|
|
}
|
|
@@ -4225,22 +4430,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
|
|
|
|
spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags);
|
|
spin_lock_irqsave(&csid_hw->hw_info->hw_lock, flags);
|
|
/* clear */
|
|
/* clear */
|
|
- cam_io_w_mb(irq_status_top, soc_info->reg_map[0].mem_base +
|
|
|
|
|
|
+ cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_TOP],
|
|
|
|
+ soc_info->reg_map[0].mem_base +
|
|
csid_reg->cmn_reg->csid_top_irq_clear_addr);
|
|
csid_reg->cmn_reg->csid_top_irq_clear_addr);
|
|
|
|
|
|
- cam_io_w_mb(irq_status_rx, soc_info->reg_map[0].mem_base +
|
|
|
|
|
|
+ cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_RX],
|
|
|
|
+ soc_info->reg_map[0].mem_base +
|
|
csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr);
|
|
csid_reg->csi2_reg->csid_csi2_rx_irq_clear_addr);
|
|
if (csid_reg->cmn_reg->num_pix)
|
|
if (csid_reg->cmn_reg->num_pix)
|
|
- cam_io_w_mb(irq_status_ipp, soc_info->reg_map[0].mem_base +
|
|
|
|
|
|
+ cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_IPP],
|
|
|
|
+ soc_info->reg_map[0].mem_base +
|
|
csid_reg->ipp_reg->csid_pxl_irq_clear_addr);
|
|
csid_reg->ipp_reg->csid_pxl_irq_clear_addr);
|
|
|
|
|
|
if (csid_reg->cmn_reg->num_ppp)
|
|
if (csid_reg->cmn_reg->num_ppp)
|
|
- cam_io_w_mb(irq_status_ppp, soc_info->reg_map[0].mem_base +
|
|
|
|
|
|
+ cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_PPP],
|
|
|
|
+ soc_info->reg_map[0].mem_base +
|
|
csid_reg->ppp_reg->csid_pxl_irq_clear_addr);
|
|
csid_reg->ppp_reg->csid_pxl_irq_clear_addr);
|
|
|
|
|
|
if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) {
|
|
if (csid_reg->cmn_reg->num_rdis <= CAM_IFE_CSID_RDI_MAX) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) {
|
|
- cam_io_w_mb(irq_status_rdi[i],
|
|
|
|
|
|
+ cam_io_w_mb(irq_status[i],
|
|
soc_info->reg_map[0].mem_base +
|
|
soc_info->reg_map[0].mem_base +
|
|
csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr);
|
|
csid_reg->rdi_reg[i]->csid_rdi_irq_clear_addr);
|
|
}
|
|
}
|
|
@@ -4248,7 +4457,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
|
|
|
|
if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) {
|
|
if (csid_reg->cmn_reg->num_udis <= CAM_IFE_CSID_UDI_MAX) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) {
|
|
- cam_io_w_mb(irq_status_udi[i],
|
|
|
|
|
|
+ cam_io_w_mb(irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i],
|
|
soc_info->reg_map[0].mem_base +
|
|
soc_info->reg_map[0].mem_base +
|
|
csid_reg->udi_reg[i]->csid_udi_irq_clear_addr);
|
|
csid_reg->udi_reg[i]->csid_udi_irq_clear_addr);
|
|
}
|
|
}
|
|
@@ -4259,18 +4468,24 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
|
|
|
|
spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags);
|
|
spin_unlock_irqrestore(&csid_hw->hw_info->hw_lock, flags);
|
|
|
|
|
|
- CAM_DBG(CAM_ISP, "irq_status_top = 0x%x", irq_status_top);
|
|
|
|
- CAM_DBG(CAM_ISP, "irq_status_rx = 0x%x", irq_status_rx);
|
|
|
|
- CAM_DBG(CAM_ISP, "irq_status_ipp = 0x%x", irq_status_ipp);
|
|
|
|
- CAM_DBG(CAM_ISP, "irq_status_ppp = 0x%x", irq_status_ppp);
|
|
|
|
|
|
+ CAM_DBG(CAM_ISP, "irq_status_top = 0x%x",
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_TOP]);
|
|
|
|
+ CAM_DBG(CAM_ISP, "irq_status_rx = 0x%x",
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_RX]);
|
|
|
|
+ CAM_DBG(CAM_ISP, "irq_status_ipp = 0x%x",
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_IPP]);
|
|
|
|
+ CAM_DBG(CAM_ISP, "irq_status_ppp = 0x%x",
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_PPP]);
|
|
CAM_DBG(CAM_ISP,
|
|
CAM_DBG(CAM_ISP,
|
|
"irq_status_rdi0= 0x%x irq_status_rdi1= 0x%x irq_status_rdi2= 0x%x",
|
|
"irq_status_rdi0= 0x%x irq_status_rdi1= 0x%x irq_status_rdi2= 0x%x",
|
|
- irq_status_rdi[0], irq_status_rdi[1], irq_status_rdi[2]);
|
|
|
|
|
|
+ irq_status[0], irq_status[1], irq_status[2]);
|
|
CAM_DBG(CAM_ISP,
|
|
CAM_DBG(CAM_ISP,
|
|
"irq_status_udi0= 0x%x irq_status_udi1= 0x%x irq_status_udi2= 0x%x",
|
|
"irq_status_udi0= 0x%x irq_status_udi1= 0x%x irq_status_udi2= 0x%x",
|
|
- irq_status_udi[0], irq_status_udi[1], irq_status_udi[2]);
|
|
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0],
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_UDI_1],
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_UDI_2]);
|
|
|
|
|
|
- if (irq_status_top & CSID_TOP_IRQ_DONE) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_TOP] & CSID_TOP_IRQ_DONE) {
|
|
CAM_DBG(CAM_ISP, "csid top reset complete");
|
|
CAM_DBG(CAM_ISP, "csid top reset complete");
|
|
complete(&csid_hw->csid_top_complete);
|
|
complete(&csid_hw->csid_top_complete);
|
|
csid_hw->is_resetting = false;
|
|
csid_hw->is_resetting = false;
|
|
@@ -4283,78 +4498,99 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
return IRQ_HANDLED;
|
|
return IRQ_HANDLED;
|
|
}
|
|
}
|
|
|
|
|
|
- if (irq_status_rx & BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ BIT(csid_reg->csi2_reg->csi2_rst_done_shift_val)) {
|
|
CAM_DBG(CAM_ISP, "csi rx reset complete");
|
|
CAM_DBG(CAM_ISP, "csi rx reset complete");
|
|
complete(&csid_hw->csid_csi2_complete);
|
|
complete(&csid_hw->csid_csi2_complete);
|
|
}
|
|
}
|
|
|
|
|
|
spin_lock_irqsave(&csid_hw->lock_state, flags);
|
|
spin_lock_irqsave(&csid_hw->lock_state, flags);
|
|
if (csid_hw->device_enabled == 1) {
|
|
if (csid_hw->device_enabled == 1) {
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_LANE0_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 0 over flow",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 0 over flow",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
fatal_err_detected = true;
|
|
fatal_err_detected = true;
|
|
|
|
+ goto handle_fatal_error;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_LANE1_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 1 over flow",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 1 over flow",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
fatal_err_detected = true;
|
|
fatal_err_detected = true;
|
|
|
|
+ goto handle_fatal_error;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_LANE2_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 2 over flow",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 2 over flow",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
fatal_err_detected = true;
|
|
fatal_err_detected = true;
|
|
|
|
+ goto handle_fatal_error;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_LANE3_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 3 over flow",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d lane 3 over flow",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
fatal_err_detected = true;
|
|
fatal_err_detected = true;
|
|
|
|
+ goto handle_fatal_error;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_TG_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d TG OVER FLOW",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d TG OVER FLOW",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
fatal_err_detected = true;
|
|
fatal_err_detected = true;
|
|
|
|
+ goto handle_fatal_error;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_CPHY_EOT_RECEPTION) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d CPHY_EOT_RECEPTION",
|
|
"CSID:%d CPHY_EOT_RECEPTION",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
csid_hw->error_irq_count++;
|
|
csid_hw->error_irq_count++;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_CPHY_SOT_RECEPTION) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d CPHY_SOT_RECEPTION",
|
|
"CSID:%d CPHY_SOT_RECEPTION",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
csid_hw->error_irq_count++;
|
|
csid_hw->error_irq_count++;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_CPHY_PH_CRC) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_CPHY_PH_CRC) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PH_CRC",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PH_CRC",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_CRC) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_CRC) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_CRC",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_CRC",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_ECC) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_ECC) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_ECC",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d ERROR_ECC",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_MMAPPED_VC_DT) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d MMAPPED_VC_DT",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d MMAPPED_VC_DT",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_STREAM_UNDERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d ERROR_STREAM_UNDERFLOW",
|
|
"CSID:%d ERROR_STREAM_UNDERFLOW",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
csid_hw->error_irq_count++;
|
|
csid_hw->error_irq_count++;
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_ERROR_UNBOUNDED_FRAME) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d UNBOUNDED_FRAME",
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP, "CSID:%d UNBOUNDED_FRAME",
|
|
- csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx);
|
|
csid_hw->error_irq_count++;
|
|
csid_hw->error_irq_count++;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
+
|
|
|
|
+handle_fatal_error:
|
|
spin_unlock_irqrestore(&csid_hw->lock_state, flags);
|
|
spin_unlock_irqrestore(&csid_hw->lock_state, flags);
|
|
|
|
|
|
if (csid_hw->error_irq_count >
|
|
if (csid_hw->error_irq_count >
|
|
@@ -4363,26 +4599,33 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_hw->error_irq_count = 0;
|
|
csid_hw->error_irq_count = 0;
|
|
}
|
|
}
|
|
|
|
|
|
- if (fatal_err_detected)
|
|
|
|
|
|
+ if (fatal_err_detected) {
|
|
cam_ife_csid_halt_csi2(csid_hw);
|
|
cam_ife_csid_halt_csi2(csid_hw);
|
|
|
|
+ cam_csid_handle_hw_err_irq(csid_hw,
|
|
|
|
+ CAM_ISP_HW_ERROR_CSID_FATAL, irq_status);
|
|
|
|
+ }
|
|
|
|
|
|
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) {
|
|
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOT_IRQ) {
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL0_EOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL0_EOT_CAPTURED",
|
|
"CSID:%d PHY_DL0_EOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL1_EOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL1_EOT_CAPTURED",
|
|
"CSID:%d PHY_DL1_EOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL2_EOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL2_EOT_CAPTURED",
|
|
"CSID:%d PHY_DL2_EOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL3_EOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL3_EOT_CAPTURED",
|
|
"CSID:%d PHY_DL3_EOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4390,22 +4633,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
}
|
|
}
|
|
|
|
|
|
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) {
|
|
if (csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOT_IRQ) {
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL0_SOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL0_SOT_CAPTURED",
|
|
"CSID:%d PHY_DL0_SOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL1_SOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL1_SOT_CAPTURED",
|
|
"CSID:%d PHY_DL1_SOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL2_SOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL2_SOT_CAPTURED",
|
|
"CSID:%d PHY_DL2_SOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
}
|
|
}
|
|
- if (irq_status_rx & CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_PHY_DL3_SOT_CAPTURED) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PHY_DL3_SOT_CAPTURED",
|
|
"CSID:%d PHY_DL3_SOT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4413,7 +4660,9 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
}
|
|
}
|
|
|
|
|
|
if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) &&
|
|
if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_LONG_PKT_CAPTURE) &&
|
|
- (irq_status_rx & CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) {
|
|
|
|
|
|
+ (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_LONG_PKT_CAPTURED)) {
|
|
|
|
+
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED",
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d LONG_PKT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
@@ -4433,7 +4682,9 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF));
|
|
csid_hw->hw_intf->hw_idx, (val >> 16), (val & 0xFFFF));
|
|
}
|
|
}
|
|
if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) &&
|
|
if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_SHORT_PKT_CAPTURE) &&
|
|
- (irq_status_rx & CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) {
|
|
|
|
|
|
+ (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_SHORT_PKT_CAPTURED)) {
|
|
|
|
+
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED",
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d SHORT_PKT_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
@@ -4449,7 +4700,8 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
}
|
|
}
|
|
|
|
|
|
if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) &&
|
|
if ((csid_hw->csid_debug & CSID_DEBUG_ENABLE_CPHY_PKT_CAPTURE) &&
|
|
- (irq_status_rx & CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) {
|
|
|
|
|
|
+ (irq_status[CAM_IFE_CSID_IRQ_REG_RX] &
|
|
|
|
+ CSID_CSI2_RX_INFO_CPHY_PKT_HDR_CAPTURED)) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED",
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d CPHY_PKT_HDR_CAPTURED",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
@@ -4463,14 +4715,15 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
/*read the IPP errors */
|
|
/*read the IPP errors */
|
|
if (csid_reg->cmn_reg->num_pix) {
|
|
if (csid_reg->cmn_reg->num_pix) {
|
|
/* IPP reset done bit */
|
|
/* IPP reset done bit */
|
|
- if (irq_status_ipp &
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
CAM_DBG(CAM_ISP, "CSID:%d IPP reset complete",
|
|
CAM_DBG(CAM_ISP, "CSID:%d IPP reset complete",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
complete(&csid_hw->csid_ipp_complete);
|
|
complete(&csid_hw->csid_ipp_complete);
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_ipp & CSID_PATH_INFO_INPUT_SOF) &&
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
|
|
+ CSID_PATH_INFO_INPUT_SOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP SOF received",
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP SOF received",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4478,22 +4731,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_hw->irq_debug_cnt++;
|
|
csid_hw->irq_debug_cnt++;
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_ipp & CSID_PATH_INFO_INPUT_EOF) &&
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
|
|
+ CSID_PATH_INFO_INPUT_EOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP EOF received",
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d IPP EOF received",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
- if ((irq_status_ipp & CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
|
|
+ CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d IPP CCIF violation",
|
|
"CSID:%d IPP CCIF violation",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
- if ((irq_status_ipp & CSID_PATH_OVERFLOW_RECOVERY))
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
|
|
+ CSID_PATH_OVERFLOW_RECOVERY))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d IPP Overflow due to back pressure",
|
|
"CSID:%d IPP Overflow due to back pressure",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
- if (irq_status_ipp & CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
|
|
+ CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d IPP fifo over flow",
|
|
"CSID:%d IPP fifo over flow",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4503,14 +4760,17 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_reg->ipp_reg->csid_pxl_ctrl_addr);
|
|
csid_reg->ipp_reg->csid_pxl_ctrl_addr);
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_ipp & CSID_PATH_ERROR_PIX_COUNT) ||
|
|
|
|
- (irq_status_ipp & CSID_PATH_ERROR_LINE_COUNT)) {
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
|
|
+ CSID_PATH_ERROR_PIX_COUNT) ||
|
|
|
|
+ (irq_status[CAM_IFE_CSID_IRQ_REG_IPP] &
|
|
|
|
+ CSID_PATH_ERROR_LINE_COUNT)) {
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
csid_reg->ipp_reg->csid_pxl_format_measure0_addr);
|
|
csid_reg->ipp_reg->csid_pxl_format_measure0_addr);
|
|
|
|
|
|
CAM_ERR(CAM_ISP,
|
|
CAM_ERR(CAM_ISP,
|
|
"CSID:%d irq_status_ipp:0x%x",
|
|
"CSID:%d irq_status_ipp:0x%x",
|
|
- csid_hw->hw_intf->hw_idx, irq_status_ipp);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx,
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_IPP]);
|
|
CAM_ERR(CAM_ISP,
|
|
CAM_ERR(CAM_ISP,
|
|
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x",
|
|
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x",
|
|
csid_hw->ipp_path_config.height,
|
|
csid_hw->ipp_path_config.height,
|
|
@@ -4526,14 +4786,15 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
/*read PPP errors */
|
|
/*read PPP errors */
|
|
if (csid_reg->cmn_reg->num_ppp) {
|
|
if (csid_reg->cmn_reg->num_ppp) {
|
|
/* PPP reset done bit */
|
|
/* PPP reset done bit */
|
|
- if (irq_status_ppp &
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
CAM_DBG(CAM_ISP, "CSID:%d PPP reset complete",
|
|
CAM_DBG(CAM_ISP, "CSID:%d PPP reset complete",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
complete(&csid_hw->csid_ppp_complete);
|
|
complete(&csid_hw->csid_ppp_complete);
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_ppp & CSID_PATH_INFO_INPUT_SOF) &&
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
|
|
+ CSID_PATH_INFO_INPUT_SOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP SOF received",
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP SOF received",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4541,22 +4802,26 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_hw->irq_debug_cnt++;
|
|
csid_hw->irq_debug_cnt++;
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_ppp & CSID_PATH_INFO_INPUT_EOF) &&
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
|
|
+ CSID_PATH_INFO_INPUT_EOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP EOF received",
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP, "CSID:%d PPP EOF received",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
- if ((irq_status_ppp & CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
|
|
+ CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PPP CCIF violation",
|
|
"CSID:%d PPP CCIF violation",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
- if ((irq_status_ppp & CSID_PATH_OVERFLOW_RECOVERY))
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
|
|
+ CSID_PATH_OVERFLOW_RECOVERY))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d IPP Overflow due to back pressure",
|
|
"CSID:%d IPP Overflow due to back pressure",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
|
|
|
|
- if (irq_status_ppp & CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
|
|
+ CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d PPP fifo over flow",
|
|
"CSID:%d PPP fifo over flow",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4566,14 +4831,17 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_reg->ppp_reg->csid_pxl_ctrl_addr);
|
|
csid_reg->ppp_reg->csid_pxl_ctrl_addr);
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_ppp & CSID_PATH_ERROR_PIX_COUNT) ||
|
|
|
|
- (irq_status_ppp & CSID_PATH_ERROR_LINE_COUNT)) {
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
|
|
+ CSID_PATH_ERROR_PIX_COUNT) ||
|
|
|
|
+ (irq_status[CAM_IFE_CSID_IRQ_REG_PPP] &
|
|
|
|
+ CSID_PATH_ERROR_LINE_COUNT)) {
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
csid_reg->ppp_reg->csid_pxl_format_measure0_addr);
|
|
csid_reg->ppp_reg->csid_pxl_format_measure0_addr);
|
|
|
|
|
|
CAM_ERR(CAM_ISP,
|
|
CAM_ERR(CAM_ISP,
|
|
"CSID:%d irq_status_ppp:0x%x",
|
|
"CSID:%d irq_status_ppp:0x%x",
|
|
- csid_hw->hw_intf->hw_idx, irq_status_ppp);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx,
|
|
|
|
+ irq_status[CAM_IFE_CSID_IRQ_REG_PPP]);
|
|
CAM_ERR(CAM_ISP,
|
|
CAM_ERR(CAM_ISP,
|
|
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x",
|
|
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x",
|
|
csid_hw->ppp_path_config.height,
|
|
csid_hw->ppp_path_config.height,
|
|
@@ -4587,14 +4855,14 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
}
|
|
}
|
|
|
|
|
|
for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_rdis; i++) {
|
|
- if (irq_status_rdi[i] &
|
|
|
|
|
|
+ if (irq_status[i] &
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
CAM_DBG(CAM_ISP, "CSID:%d RDI%d reset complete",
|
|
CAM_DBG(CAM_ISP, "CSID:%d RDI%d reset complete",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
complete(&csid_hw->csid_rdin_complete[i]);
|
|
complete(&csid_hw->csid_rdin_complete[i]);
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_rdi[i] & CSID_PATH_INFO_INPUT_SOF) &&
|
|
|
|
|
|
+ if ((irq_status[i] & CSID_PATH_INFO_INPUT_SOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d RDI:%d SOF received",
|
|
"CSID:%d RDI:%d SOF received",
|
|
@@ -4603,23 +4871,23 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_hw->irq_debug_cnt++;
|
|
csid_hw->irq_debug_cnt++;
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_rdi[i] & CSID_PATH_INFO_INPUT_EOF) &&
|
|
|
|
|
|
+ if ((irq_status[i] & CSID_PATH_INFO_INPUT_EOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d RDI:%d EOF received",
|
|
"CSID:%d RDI:%d EOF received",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
|
|
|
|
- if ((irq_status_rdi[i] & CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
|
|
|
|
+ if ((irq_status[i] & CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d RDI :%d CCIF violation",
|
|
"CSID:%d RDI :%d CCIF violation",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
|
|
|
|
- if ((irq_status_rdi[i] & CSID_PATH_OVERFLOW_RECOVERY))
|
|
|
|
|
|
+ if ((irq_status[i] & CSID_PATH_OVERFLOW_RECOVERY))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d RDI :%d Overflow due to back pressure",
|
|
"CSID:%d RDI :%d Overflow due to back pressure",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
|
|
|
|
- if (irq_status_rdi[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d RDI fifo over flow",
|
|
"CSID:%d RDI fifo over flow",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4629,8 +4897,8 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr);
|
|
csid_reg->rdi_reg[i]->csid_rdi_ctrl_addr);
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_rdi[i] & CSID_PATH_ERROR_PIX_COUNT) ||
|
|
|
|
- (irq_status_rdi[i] & CSID_PATH_ERROR_LINE_COUNT)) {
|
|
|
|
|
|
+ if ((irq_status[i] & CSID_PATH_ERROR_PIX_COUNT) ||
|
|
|
|
+ (irq_status[i] & CSID_PATH_ERROR_LINE_COUNT)) {
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
val = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
csid_reg->rdi_reg[i]->csid_rdi_format_measure0_addr);
|
|
csid_reg->rdi_reg[i]->csid_rdi_format_measure0_addr);
|
|
val2 = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
val2 = cam_io_r_mb(soc_info->reg_map[0].mem_base +
|
|
@@ -4638,7 +4906,7 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
);
|
|
);
|
|
CAM_ERR(CAM_ISP,
|
|
CAM_ERR(CAM_ISP,
|
|
"CSID:%d irq_status_rdi[%d]:0x%x",
|
|
"CSID:%d irq_status_rdi[%d]:0x%x",
|
|
- csid_hw->hw_intf->hw_idx, i, irq_status_rdi[i]);
|
|
|
|
|
|
+ csid_hw->hw_intf->hw_idx, i, irq_status[i]);
|
|
CAM_ERR(CAM_ISP,
|
|
CAM_ERR(CAM_ISP,
|
|
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x",
|
|
"Expected:: h: 0x%x w: 0x%x actual:: h: 0x%x w: 0x%x",
|
|
((val2 >>
|
|
((val2 >>
|
|
@@ -4655,14 +4923,15 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
}
|
|
}
|
|
|
|
|
|
for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) {
|
|
for (i = 0; i < csid_reg->cmn_reg->num_udis; i++) {
|
|
- if (irq_status_udi[i] &
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] &
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
BIT(csid_reg->cmn_reg->path_rst_done_shift_val)) {
|
|
CAM_DBG(CAM_ISP, "CSID:%d UDI%d reset complete",
|
|
CAM_DBG(CAM_ISP, "CSID:%d UDI%d reset complete",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
complete(&csid_hw->csid_udin_complete[i]);
|
|
complete(&csid_hw->csid_udin_complete[i]);
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_udi[i] & CSID_PATH_INFO_INPUT_SOF) &&
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] &
|
|
|
|
+ CSID_PATH_INFO_INPUT_SOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_SOF_IRQ)) {
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d UDI:%d SOF received",
|
|
"CSID:%d UDI:%d SOF received",
|
|
@@ -4671,23 +4940,27 @@ irqreturn_t cam_ife_csid_irq(int irq_num, void *data)
|
|
csid_hw->irq_debug_cnt++;
|
|
csid_hw->irq_debug_cnt++;
|
|
}
|
|
}
|
|
|
|
|
|
- if ((irq_status_udi[i] & CSID_PATH_INFO_INPUT_EOF) &&
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] &
|
|
|
|
+ CSID_PATH_INFO_INPUT_EOF) &&
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
(csid_hw->csid_debug & CSID_DEBUG_ENABLE_EOF_IRQ))
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
CAM_INFO_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d UDI:%d EOF received",
|
|
"CSID:%d UDI:%d EOF received",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
|
|
|
|
- if ((irq_status_udi[i] & CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] &
|
|
|
|
+ CSID_PATH_ERROR_CCIF_VIOLATION))
|
|
CAM_WARN_RATE_LIMIT(CAM_ISP,
|
|
CAM_WARN_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d UDI :%d CCIF violation",
|
|
"CSID:%d UDI :%d CCIF violation",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
|
|
|
|
- if ((irq_status_udi[i] & CSID_PATH_OVERFLOW_RECOVERY))
|
|
|
|
|
|
+ if ((irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] &
|
|
|
|
+ CSID_PATH_OVERFLOW_RECOVERY))
|
|
CAM_WARN_RATE_LIMIT(CAM_ISP,
|
|
CAM_WARN_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d UDI :%d Overflow due to back pressure",
|
|
"CSID:%d UDI :%d Overflow due to back pressure",
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
csid_hw->hw_intf->hw_idx, i);
|
|
|
|
|
|
- if (irq_status_udi[i] & CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
|
|
|
|
+ if (irq_status[CAM_IFE_CSID_IRQ_REG_UDI_0 + i] &
|
|
|
|
+ CSID_PATH_ERROR_FIFO_OVERFLOW) {
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
CAM_ERR_RATE_LIMIT(CAM_ISP,
|
|
"CSID:%d UDI fifo over flow",
|
|
"CSID:%d UDI fifo over flow",
|
|
csid_hw->hw_intf->hw_idx);
|
|
csid_hw->hw_intf->hw_idx);
|
|
@@ -4867,6 +5140,19 @@ int cam_ife_csid_hw_probe_init(struct cam_hw_intf *csid_hw_intf,
|
|
ife_csid_hw->udi_res[i].res_priv = path_data;
|
|
ife_csid_hw->udi_res[i].res_priv = path_data;
|
|
}
|
|
}
|
|
|
|
|
|
|
|
+ rc = cam_tasklet_init(&ife_csid_hw->tasklet, ife_csid_hw, csid_idx);
|
|
|
|
+ if (rc) {
|
|
|
|
+ CAM_ERR(CAM_ISP, "Unable to create CSID tasklet rc %d", rc);
|
|
|
|
+ goto err;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ INIT_LIST_HEAD(&ife_csid_hw->free_payload_list);
|
|
|
|
+ for (i = 0; i < CAM_CSID_EVT_PAYLOAD_MAX; i++) {
|
|
|
|
+ INIT_LIST_HEAD(&ife_csid_hw->evt_payload[i].list);
|
|
|
|
+ list_add_tail(&ife_csid_hw->evt_payload[i].list,
|
|
|
|
+ &ife_csid_hw->free_payload_list);
|
|
|
|
+ }
|
|
|
|
+
|
|
ife_csid_hw->csid_debug = 0;
|
|
ife_csid_hw->csid_debug = 0;
|
|
ife_csid_hw->error_irq_count = 0;
|
|
ife_csid_hw->error_irq_count = 0;
|
|
ife_csid_hw->ipp_path_config.measure_enabled = 0;
|
|
ife_csid_hw->ipp_path_config.measure_enabled = 0;
|