Merge 42fc0fe2e561d46f12a793e4a8e6808f0a1f6cfd on remote branch

Change-Id: I3159e29c56d99afb2eb56e6d9f9eee83a1ff6520

Android.mk

@@ -22,7 +22,9 @@ LOCAL_MODULE_KO_DIRS += cnss_genl/cnss_nl.ko
 LOCAL_MODULE_KO_DIRS += cnss_prealloc/cnss_prealloc.ko
 LOCAL_MODULE_KO_DIRS += cnss_utils/cnss_utils.ko
 LOCAL_MODULE_KO_DIRS += icnss2/icnss2.ko
-DLKM_DIR := $(TOP)/device/qcom/common/dlkm
+
+BOARD_COMMON_DIR ?= device/qcom/common
+DLKM_DIR := $(TOP)/$(BOARD_COMMON_DIR)/dlkm
 
 # WLAN_PLATFORM_ROOT needs to be a absolute since it will be used
 # for header files. $(TOP) cannot be used here since it will be

cnss2/main.c

@@ -760,6 +760,28 @@ void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova, size_t size)
 }
 EXPORT_SYMBOL(cnss_audio_smmu_unmap);
 
+int cnss_get_fw_lpass_shared_mem(struct device *dev, dma_addr_t *iova,
+				 size_t *size)
+{
+	struct cnss_plat_data *plat_priv = cnss_bus_dev_to_plat_priv(dev);
+	uint8_t i;
+
+	if (!plat_priv)
+		return -EINVAL;
+
+	for (i = 0; i < plat_priv->fw_mem_seg_len; i++) {
+		if (plat_priv->fw_mem[i].type ==
+		    QMI_WLFW_MEM_LPASS_SHARED_V01) {
+			*iova = plat_priv->fw_mem[i].pa;
+			*size = plat_priv->fw_mem[i].size;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+EXPORT_SYMBOL(cnss_get_fw_lpass_shared_mem);
+
 int cnss_athdiag_read(struct device *dev, u32 offset, u32 mem_type,
 		      u32 data_len, u8 *output)
 {
@@ -2556,6 +2578,9 @@ static void *cnss_get_fw_mem_pa_to_va(struct cnss_fw_mem *fw_mem,
 	u32 local_size;
 
 	for (i = 0; i < mem_seg_len; i++) {
+		if (i == QMI_WLFW_MEM_LPASS_SHARED_V01)
+			continue;
+
 		local_pa = (u64)fw_mem[i].pa;
 		local_size = (u32)fw_mem[i].size;
 		if (pa == local_pa && size <= local_size) {

cnss2/main.h

@@ -132,6 +132,8 @@ struct cnss_pinctrl_info {
 	struct pinctrl_state *sol_default;
 	struct pinctrl_state *wlan_en_active;
 	struct pinctrl_state *wlan_en_sleep;
+	struct pinctrl_state *sw_ctrl;
+	struct pinctrl_state *sw_ctrl_wl_cx;
 	int bt_en_gpio;
 	int wlan_en_gpio;
 	int xo_clk_gpio; /*qca6490 only */

cnss2/pci.c

@@ -504,6 +504,21 @@ static struct cnss_pci_reg pci_scratch[] = {
 	{ NULL },
 };
 
+static struct cnss_pci_reg pci_bhi_debug[] = {
+	{ "PCIE_BHIE_DEBUG_0", PCIE_PCIE_BHIE_DEBUG_0 },
+	{ "PCIE_BHIE_DEBUG_1", PCIE_PCIE_BHIE_DEBUG_1 },
+	{ "PCIE_BHIE_DEBUG_2", PCIE_PCIE_BHIE_DEBUG_2 },
+	{ "PCIE_BHIE_DEBUG_3", PCIE_PCIE_BHIE_DEBUG_3 },
+	{ "PCIE_BHIE_DEBUG_4", PCIE_PCIE_BHIE_DEBUG_4 },
+	{ "PCIE_BHIE_DEBUG_5", PCIE_PCIE_BHIE_DEBUG_5 },
+	{ "PCIE_BHIE_DEBUG_6", PCIE_PCIE_BHIE_DEBUG_6 },
+	{ "PCIE_BHIE_DEBUG_7", PCIE_PCIE_BHIE_DEBUG_7 },
+	{ "PCIE_BHIE_DEBUG_8", PCIE_PCIE_BHIE_DEBUG_8 },
+	{ "PCIE_BHIE_DEBUG_9", PCIE_PCIE_BHIE_DEBUG_9 },
+	{ "PCIE_BHIE_DEBUG_10", PCIE_PCIE_BHIE_DEBUG_10 },
+	{ NULL },
+};
+
 /* First field of the structure is the device bit mask. Use
  * enum cnss_pci_reg_mask as reference for the value.
  */
@@ -786,7 +801,6 @@ static void cnss_pci_update_link_event(struct cnss_pci_data *pci_priv,
 				       enum cnss_bus_event_type type,
 				       void *data);
 
-
 #if IS_ENABLED(CONFIG_MHI_BUS_MISC)
 static void cnss_mhi_debug_reg_dump(struct cnss_pci_data *pci_priv)
 {
@@ -1411,6 +1425,59 @@ static void cnss_pci_soc_scratch_reg_dump(struct cnss_pci_data *pci_priv)
 	}
 }
 
+static void cnss_pci_soc_reset_cause_reg_dump(struct cnss_pci_data *pci_priv)
+{
+	u32 val;
+
+	switch (pci_priv->device_id) {
+	case PEACH_DEVICE_ID:
+		break;
+	default:
+		return;
+	}
+
+	if (in_interrupt() || irqs_disabled())
+		return;
+
+	if (cnss_pci_check_link_status(pci_priv))
+		return;
+
+	cnss_pr_dbg("Start to dump SOC Reset Cause registers\n");
+
+	if (cnss_pci_reg_read(pci_priv, WLAON_SOC_RESET_CAUSE_SHADOW_REG,
+			      &val))
+		return;
+	cnss_pr_dbg("WLAON_SOC_RESET_CAUSE_SHADOW_REG = 0x%x\n",
+		     val);
+
+}
+
+static void cnss_pci_bhi_debug_reg_dump(struct cnss_pci_data *pci_priv)
+{
+	u32 reg_offset, val;
+	int i;
+
+	switch (pci_priv->device_id) {
+	case PEACH_DEVICE_ID:
+		break;
+	default:
+		return;
+	}
+
+	if (cnss_pci_check_link_status(pci_priv))
+		return;
+
+	cnss_pr_dbg("Start to dump PCIE BHIE DEBUG registers\n");
+
+	for (i = 0; pci_bhi_debug[i].name; i++) {
+		reg_offset = pci_bhi_debug[i].offset;
+		if (cnss_pci_reg_read(pci_priv, reg_offset, &val))
+			return;
+		cnss_pr_dbg("PCIE__%s = 0x%x\n",
+			     pci_bhi_debug[i].name, val);
+	}
+}
+
 int cnss_suspend_pci_link(struct cnss_pci_data *pci_priv)
 {
 	int ret = 0;
@@ -1690,6 +1757,8 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
 	u32 sbl_log_def_end = SRAM_END;
 	int i;
 
+	cnss_pci_soc_reset_cause_reg_dump(pci_priv);
+
 	switch (pci_priv->device_id) {
 	case QCA6390_DEVICE_ID:
 		pbl_log_sram_start = QCA6390_DEBUG_PBL_LOG_SRAM_START;
@@ -1739,7 +1808,7 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
 
 	ee = mhi_get_exec_env(pci_priv->mhi_ctrl);
 	if (CNSS_MHI_IN_MISSION_MODE(ee)) {
-		cnss_pr_dbg("Avoid Dumping PBL log data in Mission mode\n");
+		cnss_pr_err("Avoid Dumping PBL log data in Mission mode\n");
 		return;
 	}
 
@@ -1762,7 +1831,7 @@ static void cnss_pci_dump_bl_sram_mem(struct cnss_pci_data *pci_priv)
 
 	ee = mhi_get_exec_env(pci_priv->mhi_ctrl);
 	if (CNSS_MHI_IN_MISSION_MODE(ee)) {
-		cnss_pr_dbg("Avoid Dumping SBL log data in Mission mode\n");
+		cnss_pr_err("Avoid Dumping SBL log data in Mission mode\n");
 		return;
 	}
 
@@ -1836,6 +1905,7 @@ static int cnss_pci_handle_mhi_poweron_timeout(struct cnss_pci_data *pci_priv)
 	} else {
 		cnss_pr_dbg("RDDM cookie is not set and device SOL is low\n");
 		cnss_mhi_debug_reg_dump(pci_priv);
+		cnss_pci_bhi_debug_reg_dump(pci_priv);
 		cnss_pci_soc_scratch_reg_dump(pci_priv);
 		/* Dump PBL/SBL error log if RDDM cookie is not set */
 		cnss_pci_dump_bl_sram_mem(pci_priv);
@@ -2374,7 +2444,6 @@ retry:
 	/* Start the timer to dump MHI/PBL/SBL debug data periodically */
 	mod_timer(&pci_priv->boot_debug_timer,
 		  jiffies + msecs_to_jiffies(BOOT_DEBUG_TIMEOUT_MS));
-
 	ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_POWER_ON);
 	del_timer_sync(&pci_priv->boot_debug_timer);
 	if (ret == 0)
@@ -5675,6 +5744,7 @@ static void cnss_pci_dump_debug_reg(struct cnss_pci_data *pci_priv)
 	cnss_pr_dbg("Start to dump debug registers\n");
 
 	cnss_mhi_debug_reg_dump(pci_priv);
+	cnss_pci_bhi_debug_reg_dump(pci_priv);
 	cnss_pci_soc_scratch_reg_dump(pci_priv);
 	cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_COMMON);
 	cnss_pci_dump_ce_reg(pci_priv, CNSS_CE_09);
@@ -5697,6 +5767,7 @@ static void cnss_pci_mhi_reg_dump(struct cnss_pci_data *pci_priv)
 	if (!cnss_pci_check_link_status(pci_priv))
 		cnss_mhi_debug_reg_dump(pci_priv);
 
+	cnss_pci_bhi_debug_reg_dump(pci_priv);
 	cnss_pci_soc_scratch_reg_dump(pci_priv);
 	cnss_pci_dump_misc_reg(pci_priv);
 	cnss_pci_dump_shadow_reg(pci_priv);
@@ -5760,6 +5831,7 @@ retry:
 	if (!cnss_pci_assert_host_sol(pci_priv))
 		return 0;
 	cnss_mhi_debug_reg_dump(pci_priv);
+	cnss_pci_bhi_debug_reg_dump(pci_priv);
 	cnss_pci_soc_scratch_reg_dump(pci_priv);
 	cnss_schedule_recovery(&pci_priv->pci_dev->dev,
 			       CNSS_REASON_TIMEOUT);
@@ -6071,9 +6143,9 @@ void cnss_pci_collect_dump_info(struct cnss_pci_data *pci_priv, bool in_panic)
 	}
 
 	cnss_mhi_debug_reg_dump(pci_priv);
+	cnss_pci_bhi_debug_reg_dump(pci_priv);
 	cnss_pci_soc_scratch_reg_dump(pci_priv);
 	cnss_pci_dump_misc_reg(pci_priv);
-
 	cnss_rddm_trigger_debug(pci_priv);
 	ret = mhi_download_rddm_image(pci_priv->mhi_ctrl, in_panic);
 	if (ret) {
@@ -6436,6 +6508,7 @@ static void cnss_dev_rddm_timeout_hdlr(struct timer_list *t)
 				       CNSS_REASON_RDDM);
 	} else {
 		cnss_mhi_debug_reg_dump(pci_priv);
+		cnss_pci_bhi_debug_reg_dump(pci_priv);
 		cnss_pci_soc_scratch_reg_dump(pci_priv);
 		cnss_schedule_recovery(&pci_priv->pci_dev->dev,
 				       CNSS_REASON_TIMEOUT);
@@ -6465,6 +6538,7 @@ static void cnss_boot_debug_timeout_hdlr(struct timer_list *t)
 	cnss_pr_dbg("Dump MHI/PBL/SBL debug data every %ds during MHI power on\n",
 		    BOOT_DEBUG_TIMEOUT_MS / 1000);
 	cnss_mhi_debug_reg_dump(pci_priv);
+	cnss_pci_bhi_debug_reg_dump(pci_priv);
 	cnss_pci_soc_scratch_reg_dump(pci_priv);
 	cnss_pci_dump_bl_sram_mem(pci_priv);
 
@@ -7275,6 +7349,8 @@ static int cnss_pci_probe(struct pci_dev *pci_dev,
 
 	cnss_update_supported_link_info(pci_priv);
 
+	init_completion(&pci_priv->wake_event_complete);
+
 	ret = cnss_reg_pci_event(pci_priv);
 	if (ret) {
 		cnss_pr_err("Failed to register PCI event, err = %d\n", ret);
@@ -7319,7 +7395,6 @@ static int cnss_pci_probe(struct pci_dev *pci_dev,
 		cnss_pci_get_link_status(pci_priv);
 		cnss_pci_set_wlaon_pwr_ctrl(pci_priv, false, true, false);
 		cnss_pci_wake_gpio_init(pci_priv);
-		init_completion(&pci_priv->wake_event_complete);
 		break;
 	default:
 		cnss_pr_err("Unknown PCI device found: 0x%x\n",

cnss2/power.c

@@ -880,10 +880,43 @@ int cnss_get_pinctrl(struct cnss_plat_data *plat_priv)
 							       0);
 		cnss_pr_dbg("Switch control GPIO: %d\n",
 			    pinctrl_info->sw_ctrl_gpio);
+
+		pinctrl_info->sw_ctrl =
+			pinctrl_lookup_state(pinctrl_info->pinctrl,
+					     "sw_ctrl");
+		if (IS_ERR_OR_NULL(pinctrl_info->sw_ctrl)) {
+			ret = PTR_ERR(pinctrl_info->sw_ctrl);
+			cnss_pr_dbg("Failed to get sw_ctrl state, err = %d\n",
+				    ret);
+		} else {
+			ret = pinctrl_select_state(pinctrl_info->pinctrl,
+						   pinctrl_info->sw_ctrl);
+			if (ret)
+				cnss_pr_err("Failed to select sw_ctrl state, err = %d\n",
+					    ret);
+		}
 	} else {
 		pinctrl_info->sw_ctrl_gpio = -EINVAL;
 	}
 
+	if (of_find_property(dev->of_node, WLAN_SW_CTRL_GPIO, NULL)) {
+		pinctrl_info->sw_ctrl_wl_cx =
+			pinctrl_lookup_state(pinctrl_info->pinctrl,
+					     "sw_ctrl_wl_cx");
+		if (IS_ERR_OR_NULL(pinctrl_info->sw_ctrl_wl_cx)) {
+			ret = PTR_ERR(pinctrl_info->sw_ctrl_wl_cx);
+			cnss_pr_dbg("Failed to get sw_ctrl_wl_cx state, err = %d\n",
+				    ret);
+		} else {
+
+			ret = pinctrl_select_state(pinctrl_info->pinctrl,
+						   pinctrl_info->sw_ctrl_wl_cx);
+			if (ret)
+				cnss_pr_err("Failed to select sw_ctrl_wl_cx state, err = %d\n",
+					    ret);
+		}
+	}
+
 	/* Find out and configure all those GPIOs which need to be setup
 	 * for interrupt wakeup capable
 	 */

cnss2/reg.h

@@ -100,7 +100,7 @@
 #define MANGO_DEBUG_SBL_LOG_SRAM_MAX_SIZE	48
 #define MANGO_PBL_BOOTSTRAP_STATUS		0x01A10008
 
-#define PEACH_DEBUG_PBL_LOG_SRAM_START		0x01403D98
+#define PEACH_DEBUG_PBL_LOG_SRAM_START		0x01403640
 #define PEACH_DEBUG_PBL_LOG_SRAM_MAX_SIZE	40
 #define PEACH_DEBUG_SBL_LOG_SRAM_MAX_SIZE	48
 #define PEACH_PBL_BOOTSTRAP_STATUS		0x01A10008
@@ -291,6 +291,7 @@
 #define WLAON_RESET_DBG_SW_ENTRY 0x1F80508
 #define WLAON_WL_PMUNOC_CFG_REG 0x1F8050C
 #define WLAON_RESET_CAUSE_CFG_REG 0x1F80510
+#define WLAON_SOC_RESET_CAUSE_SHADOW_REG 0x1F80608
 #define WLAON_SOC_WCSSAON_WAKEUP_IRQ_7_EN_REG 0x1F80514
 #define WLAON_DEBUG 0x1F80600
 #define WLAON_SOC_PARAMETERS 0x1F80604
@@ -359,6 +360,19 @@
 #define PCIE_SCRATCH_1_SOC_PCIE_REG 0x1E04044
 #define PCIE_SCRATCH_2_SOC_PCIE_REG 0x1E0405C
 
+/* PCIE BHIE DEBUG registers */
+#define PCIE_PCIE_BHIE_DEBUG_0 0x1E0E1C0
+#define PCIE_PCIE_BHIE_DEBUG_1 0x1E0E1C4
+#define PCIE_PCIE_BHIE_DEBUG_2 0x1E0E1C8
+#define PCIE_PCIE_BHIE_DEBUG_3 0x1E0E1CC
+#define PCIE_PCIE_BHIE_DEBUG_4 0x1E0E1D0
+#define PCIE_PCIE_BHIE_DEBUG_5 0x1E0E1D4
+#define PCIE_PCIE_BHIE_DEBUG_6 0x1E0E1D8
+#define PCIE_PCIE_BHIE_DEBUG_7 0x1E0E1DC
+#define PCIE_PCIE_BHIE_DEBUG_8 0x1E0E1E0
+#define PCIE_PCIE_BHIE_DEBUG_9 0x1E0E1E4
+#define PCIE_PCIE_BHIE_DEBUG_10 0x1E0E1E8
+
 #define GCC_GCC_SPARE_REG_1 0x1E40310
 #define GCC_PRE_ARES_DEBUG_TIMER_VAL 0x1E40270
 

cnss_genl/monaco_consolidate_defconfig

@@ -0,0 +1,2 @@
+CONFIG_CNSS_GENL=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_genl/monaco_gki_defconfig

@@ -0,0 +1,2 @@
+CONFIG_CNSS_GENL=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_prealloc/monaco_consolidate_defconfig

@@ -0,0 +1,2 @@
+CONFIG_WCNSS_MEM_PRE_ALLOC=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_prealloc/monaco_gki_defconfig

@@ -0,0 +1,2 @@
+CONFIG_WCNSS_MEM_PRE_ALLOC=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_utils/monaco_consolidate_defconfig

@@ -0,0 +1,3 @@
+CONFIG_CNSS_UTILS=m
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_utils/monaco_gki_defconfig

@@ -0,0 +1,3 @@
+CONFIG_CNSS_UTILS=m
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_CNSS_OUT_OF_TREE=y

cnss_utils/wlan_firmware_service_v01.c

@@ -6639,6 +6639,16 @@ struct qmi_elem_info wlfw_tme_lite_info_resp_msg_v01_ei[] = {
 EXPORT_SYMBOL(wlfw_tme_lite_info_resp_msg_v01_ei);
 
 struct qmi_elem_info wlfw_fw_ssr_ind_msg_v01_ei[] = {
+	{
+		.data_type      = QMI_SIGNED_4_BYTE_ENUM,
+		.elem_len       = 1,
+		.elem_size      = sizeof(enum wlfw_fw_ssr_reason_v01),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x01,
+		.offset         = offsetof(struct
+					   wlfw_fw_ssr_ind_msg_v01,
+					   reason_code),
+	},
 	{
 		.data_type      = QMI_EOTI,
 		.array_type       = NO_ARRAY,
@@ -6686,6 +6696,45 @@ struct qmi_elem_info wlfw_bmps_ctrl_resp_msg_v01_ei[] = {
 };
 EXPORT_SYMBOL(wlfw_bmps_ctrl_resp_msg_v01_ei);
 
+struct qmi_elem_info wlfw_lpass_ssr_req_msg_v01_ei[] = {
+	{
+		.data_type      = QMI_SIGNED_4_BYTE_ENUM,
+		.elem_len       = 1,
+		.elem_size      = sizeof(enum wlfw_lpass_ssr_reason_v01),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x01,
+		.offset         = offsetof(struct
+					   wlfw_lpass_ssr_req_msg_v01,
+					   reason_code),
+	},
+	{
+		.data_type      = QMI_EOTI,
+		.array_type       = NO_ARRAY,
+		.tlv_type       = QMI_COMMON_TLV_TYPE,
+	},
+};
+EXPORT_SYMBOL(wlfw_lpass_ssr_req_msg_v01_ei);
+
+struct qmi_elem_info wlfw_lpass_ssr_resp_msg_v01_ei[] = {
+	{
+		.data_type      = QMI_STRUCT,
+		.elem_len       = 1,
+		.elem_size      = sizeof(struct qmi_response_type_v01),
+		.array_type       = NO_ARRAY,
+		.tlv_type       = 0x02,
+		.offset         = offsetof(struct
+					   wlfw_lpass_ssr_resp_msg_v01,
+					   resp),
+		.ei_array      = qmi_response_type_v01_ei,
+	},
+	{
+		.data_type      = QMI_EOTI,
+		.array_type       = NO_ARRAY,
+		.tlv_type       = QMI_COMMON_TLV_TYPE,
+	},
+};
+EXPORT_SYMBOL(wlfw_lpass_ssr_resp_msg_v01_ei);
+
 /**
  * wlfw_is_valid_dt_node_found - Check if valid device tree node present
  *

cnss_utils/wlan_firmware_service_v01.h

@@ -38,6 +38,7 @@
 #define QMI_WLFW_IND_REGISTER_RESP_V01 0x0020
 #define QMI_WLFW_CAL_UPDATE_RESP_V01 0x0029
 #define QMI_WLFW_BMPS_CTRL_RESP_V01 0x005D
+#define QMI_WLFW_LPASS_SSR_RESP_V01 0x005E
 #define QMI_WLFW_AUX_UC_INFO_RESP_V01 0x005A
 #define QMI_WLFW_M3_INFO_REQ_V01 0x003C
 #define QMI_WLFW_PCIE_GEN_SWITCH_REQ_V01 0x0053
@@ -69,6 +70,7 @@
 #define QMI_WLFW_WLAN_HW_INIT_CFG_REQ_V01 0x0058
 #define QMI_WLFW_RESPOND_GET_INFO_IND_V01 0x004B
 #define QMI_WLFW_QDSS_TRACE_DATA_REQ_V01 0x0042
+#define QMI_WLFW_LPASS_SSR_REQ_V01 0x005E
 #define QMI_WLFW_CAL_DOWNLOAD_RESP_V01 0x0027
 #define QMI_WLFW_INI_RESP_V01 0x002F
 #define QMI_WLFW_QDSS_TRACE_MEM_INFO_REQ_V01 0x0040
@@ -193,6 +195,7 @@ enum wlfw_mem_type_enum_v01 {
 	QMI_WLFW_MLO_GLOBAL_MEM_V01 = 8,
 	QMI_WLFW_PAGEABLE_MEM_V01 = 9,
 	QMI_WLFW_AFC_MEM_V01 = 10,
+	QMI_WLFW_MEM_LPASS_SHARED_V01 = 11,
 	WLFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
 };
 
@@ -364,6 +367,20 @@ enum wlfw_bmps_state_enum_v01 {
 	WLFW_BMPS_STATE_ENUM_MAX_VAL_V01 = INT_MAX,
 };
 
+enum wlfw_fw_ssr_reason_v01 {
+	WLFW_FW_SSR_REASON_MIN_VAL_V01 = INT_MIN,
+	WLFW_FW_SSR_REASON_DEFAULT_V01 = 0,
+	WLFW_FW_SSR_REASON_XPAN_V01 = 1,
+	WLFW_FW_SSR_REASON_MAX_VAL_V01 = INT_MAX,
+};
+
+enum wlfw_lpass_ssr_reason_v01 {
+	WLFW_LPASS_SSR_REASON_MIN_VAL_V01 = INT_MIN,
+	WLFW_LPASS_SSR_REASON_NON_CE_V01 = 0,
+	WLFW_LPASS_SSR_REASON_CE_V01 = 1,
+	WLFW_LPASS_SSR_REASON_MAX_VAL_V01 = INT_MAX,
+};
+
 #define QMI_WLFW_CE_ATTR_FLAGS_V01 ((u32)0x00)
 #define QMI_WLFW_CE_ATTR_NO_SNOOP_V01 ((u32)0x01)
 #define QMI_WLFW_CE_ATTR_BYTE_SWAP_DATA_V01 ((u32)0x02)
@@ -1519,9 +1536,9 @@ struct wlfw_tme_lite_info_resp_msg_v01 {
 extern struct qmi_elem_info wlfw_tme_lite_info_resp_msg_v01_ei[];
 
 struct wlfw_fw_ssr_ind_msg_v01 {
-	char placeholder;
+	enum wlfw_fw_ssr_reason_v01 reason_code;
 };
-#define WLFW_FW_SSR_IND_MSG_V01_MAX_MSG_LEN 0
+#define WLFW_FW_SSR_IND_MSG_V01_MAX_MSG_LEN 7
 extern struct qmi_elem_info wlfw_fw_ssr_ind_msg_v01_ei[];
 
 struct wlfw_bmps_ctrl_req_msg_v01 {
@@ -1536,4 +1553,16 @@ struct wlfw_bmps_ctrl_resp_msg_v01 {
 #define WLFW_BMPS_CTRL_RESP_MSG_V01_MAX_MSG_LEN 7
 extern struct qmi_elem_info wlfw_bmps_ctrl_resp_msg_v01_ei[];
 
+struct wlfw_lpass_ssr_req_msg_v01 {
+	enum wlfw_lpass_ssr_reason_v01 reason_code;
+};
+#define WLFW_LPASS_SSR_REQ_MSG_V01_MAX_MSG_LEN 7
+extern struct qmi_elem_info wlfw_lpass_ssr_req_msg_v01_ei[];
+
+struct wlfw_lpass_ssr_resp_msg_v01 {
+	struct qmi_response_type_v01 resp;
+};
+#define WLFW_LPASS_SSR_RESP_MSG_V01_MAX_MSG_LEN 7
+extern struct qmi_elem_info wlfw_lpass_ssr_resp_msg_v01_ei[];
+
 #endif

icnss2/main.c

@@ -4617,6 +4617,7 @@ static void icnss_init_control_params(struct icnss_priv *priv)
 	priv->ctrl_params.bdf_type = ICNSS_BDF_TYPE_DEFAULT;
 
 	if (priv->device_id == WCN6750_DEVICE_ID ||
+	    priv->device_id == WCN6450_DEVICE_ID ||
 	    of_property_read_bool(priv->pdev->dev.of_node,
 				  "wpss-support-enable"))
 		priv->wpss_supported = true;

icnss2/monaco_consolidate_defconfig

@@ -0,0 +1,6 @@
+CONFIG_ICNSS2=m
+CONFIG_ICNSS2_DEBUG=y
+CONFIG_ICNSS2_QMI=y
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_CNSS_OUT_OF_TREE=y
+CONFIG_WCNSS_MEM_PRE_ALLOC=m

icnss2/monaco_gki_defconfig

@@ -0,0 +1,5 @@
+CONFIG_ICNSS2=m
+CONFIG_ICNSS2_QMI=y
+CONFIG_CNSS_QMI_SVC=m
+CONFIG_CNSS_OUT_OF_TREE=y
+CONFIG_WCNSS_MEM_PRE_ALLOC=m

icnss2/power.c

@@ -873,7 +873,7 @@ int icnss_update_cpr_info(struct icnss_priv *priv)
 {
 	struct icnss_cpr_info *cpr_info = &priv->cpr_info;
 
-	if (!cpr_info->vreg_ol_cpr || (!priv->mbox_chan && !priv->qmp)) {
+	if (!cpr_info->vreg_ol_cpr || (!priv->mbox_chan && !priv->use_direct_qmp)) {
 		icnss_pr_dbg("Mbox channel / QMP / OL CPR Vreg not configured\n");
 		return 0;
 	}

inc/cnss2.h

@@ -440,6 +440,8 @@ extern int cnss_audio_smmu_map(struct device *dev, phys_addr_t paddr,
 			       dma_addr_t iova, size_t size);
 extern void cnss_audio_smmu_unmap(struct device *dev, dma_addr_t iova,
 				 size_t size);
+extern int cnss_get_fw_lpass_shared_mem(struct device *dev, dma_addr_t *iova,
+					size_t *size);
 extern int cnss_get_pci_slot(struct device *dev);
 extern int cnss_pci_get_reg_dump(struct device *dev, uint8_t *buffer,
 				 uint32_t len);

wlan_platform_modules.bzl

@@ -10,7 +10,7 @@ _default_module_enablement_list = [
 ]
 
 _cnss2_enabled_target = ["niobe", "pineapple", "sun"]
-_icnss2_enabled_target = ["blair", "pineapple"]
+_icnss2_enabled_target = ["blair", "pineapple", "monaco"]
 
 def _get_module_list(target, variant):
     tv = "{}_{}".format(target, variant)