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@@ -4739,6 +4739,43 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev)
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sde_cfg->dither_luma_mode_support = true;
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sde_cfg->mdss_hw_block_size = 0x158;
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sde_cfg->has_trusted_vm_support = true;
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+ } else if (IS_HOLI_TARGET(hw_rev)) {
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+ sde_cfg->has_cwb_support = false;
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+ sde_cfg->has_qsync = true;
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+ sde_cfg->perf.min_prefill_lines = 24;
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+ sde_cfg->vbif_qos_nlvl = 8;
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+ sde_cfg->ts_prefill_rev = 2;
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+ sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
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+ sde_cfg->delay_prg_fetch_start = true;
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+ sde_cfg->sui_ns_allowed = true;
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+ sde_cfg->sui_misr_supported = true;
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+ sde_cfg->sui_block_xin_mask = 0xC01;
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+ sde_cfg->has_hdr = false;
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+ sde_cfg->has_sui_blendstage = true;
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+ sde_cfg->vbif_disable_inner_outer_shareable = true;
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+ sde_cfg->mdss_hw_block_size = 0x158;
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+ } else if (IS_SHIMA_TARGET(hw_rev)) {
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+ sde_cfg->has_cwb_support = true;
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+ sde_cfg->has_wb_ubwc = true;
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+ sde_cfg->has_qsync = true;
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+ sde_cfg->perf.min_prefill_lines = 35;
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+ sde_cfg->vbif_qos_nlvl = 8;
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+ sde_cfg->ts_prefill_rev = 2;
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+ sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;
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+ sde_cfg->delay_prg_fetch_start = true;
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+ sde_cfg->sui_ns_allowed = true;
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+ sde_cfg->sui_misr_supported = true;
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+ sde_cfg->sui_block_xin_mask = 0xE71;
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+ sde_cfg->has_sui_blendstage = true;
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+ sde_cfg->has_3d_merge_reset = true;
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+ sde_cfg->has_hdr = true;
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+ sde_cfg->has_hdr_plus = true;
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+ set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);
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+ sde_cfg->has_vig_p010 = true;
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+ sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;
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+ sde_cfg->inline_disable_const_clr = true;
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+ sde_cfg->vbif_disable_inner_outer_shareable = true;
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+ sde_cfg->mdss_hw_block_size = 0x158;
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} else {
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SDE_ERROR("unsupported chipset id:%X\n", hw_rev);
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sde_cfg->perf.min_prefill_lines = 0xffff;
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